CTFR 18/734,126 CTFR 80032 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-7, 9-15 and 17-22 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Li (US 2017/0192492) . Regarding claim 1, Li discloses a method performed by a processor system of a computing device for managing power modes of the processor system, comprising: identifying a minimum residency time of at least one low-power mode of the processor system based on current leakage at runtime of the processor system (Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR); identifying a cost of the at least one low-power mode of the processor system based in part on the minimum residency time of the at least one low- power mode of the processor system(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time); determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to a cost of at least one other power mode of the processor system; and configuring the processor system for the at least one low-power mode of the processor system in response to determining that transitioning to the at least one low-power mode of the processor system will result in cost savings(Paragraph 51, processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode), wherein the cost is energy consumed in transitioning into the low-power mode and operating in the low-power mode for a duration of the minimum residency time(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time). Regarding claim 2, Li discloses method of claim 1, wherein identifying a minimum residency time of at least one low-power mode of the processor system based on actual current leakage at runtime of the processor system comprises identifying the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system and an operating speed at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR); Regarding claim 3, Li discloses method of claim 2, further comprising: identifying the actual current leakage at runtime of the processor system; and updating the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR). Regarding claim 4, Li discloses method of claim 1, further comprising: identifying an expected current leakage of the processor system; and identifying a minimum residency time of the at least one low-power mode of the processor system based on the expected current leakage of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 5, Li discloses method of claim 3, further comprising updating the minimum residency time of the at least one low-power mode of the processor system based on an expected current leakage of the processor system based on the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 6, Li discloses method of claim 1, wherein: the at least one low-power mode of the processor system includes a first low-power mode and a second low-power mode; determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to the cost of the at least one other power mode of the processor system comprises determining whether transitioning to the second low-power mode results in an energy savings as compared to transitioning to the first low-power mode; and configuring the processor system for the at least one low-power mode of the processor system in response to determining that transitioning to the at least one low-power mode of the processor system will result in cost savings comprises configuring the processor system for the second low-power mode in response to identifying that the cost of the second low-power mode will result in cost savings as compared to transitioning to the first low-power mode(Paragraphs 26, 51, the first power saving mode and the second power saving mode have different power saving efficiencies in different scenarios. In an embodiment, when a residency time in a power saving mode is longer than a threshold, the second power saving mode provides more power saving than the first power saving mode; however, when the residency time is shorter than the threshold, the second power saving mode provides less power saving than the first power saving mode. Processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode). Regarding claim 7, Li discloses method of claim 1, further comprising: identifying that each of a plurality of processor systems connected to a shared power source are configured in a low-power mode, the plurality of processor systems including the processor system; identifying a remaining time in a minimum residency time of the low- power mode of each of the plurality of processor systems, the minimum residency time of the low-power mode of each of the plurality of processor systems including the minimum residency time of the at least one low-power mode of the processor system; determining whether transitioning to a low-power mode of the shared power source will result in cost savings as compared to transitioning to the low-power mode of each of the plurality of processor systems based on the remaining time in the minimum residency time of the low-power mode of each of the plurality of processor systems; and configuring the shared power source for the low-power mode of the shared power source in response to determining that transitioning to a low-power mode of the shared power source will result in cost savings as compared to transitioning to the low-power mode of each of the plurality of processor systems(Paragraphs 14, 30, 51 the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time. Processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode; Paragraph 34 discloses the energy consumption (E1) during the residency time RT in the first power saving mode is calculated according to Eq. 1, where t1 denotes to a first latency for the first power saving mode, and is a sum of the first entrance latency t1N and the first exit latency t1X.). Regarding claim 9, Li discloses a computing device, comprising: a processor system comprising a framework module and an idle governor module(Paragraph 20, the core 121 includes processing circuits 130 and a power mode control circuit 140 coupled together. The processing circuits 130 include various circuit components (not shown), such as arithmetic logic unit (ALAI) for arithmetic and logic operations, registers, and the like. The power mode control circuit 140 controls the processing circuits 130 to enter different power modes, wherein: the framework module is configured to: identify a minimum residency time of at least one low-power mode of the processor system based on current leakage at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR); and identify a cost of the at least one low-power mode of the processor system based in part on the minimum residency time of the at least one low-power mode of the processor system(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time); and the idle governor module is configured to: determine based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to a cost of at least one other power mode of the processor system; and configure the processor system for the at least one low-power mode of the processor system in response to determining that transitioning to the at least one low-power mode of the processor system will result in cost savings(Paragraph 51, processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode), wherein the cost is energy consumed in transitioning into the low-power mode and operating in the low-power mode for a duration of the minimum residency time(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time; Paragraph 34 discloses the energy consumption (E1) during the residency time RT in the first power saving mode is calculated according to Eq. 1, where t1 denotes to a first latency for the first power saving mode, and is a sum of the first entrance latency t1N and the first exit latency t1X.). Regarding claim 10, Li discloses computing device of claim 9, wherein identifying a minimum residency time of at least one low-power mode of the processor system based on actual current leakage at runtime of the processor system comprises identifying the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system and an operating speed at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR). Regarding claim 11, Li discloses computing device of claim 10, further comprising: identifying the actual current leakage at runtime of the processor system; and updating the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR). Regarding claim 12, Li discloses computing device of claim 9, further comprising: identifying an expected current leakage of the processor system; and identifying a minimum residency time of the at least one low-power mode of the processor system based on the expected current leakage of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 13, Li discloses computing device of claim 3, further comprising updating the minimum residency time of the at least one low-power mode of the processor system based on an expected current leakage of the processor system based on the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 14, Li discloses computing device of claim 9, wherein: the at least one low-power mode of the processor system includes a first low-power mode and a second low-power mode; determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to the cost of the at least one other power mode of the processor system comprises determining whether transitioning to the second low-power mode results in an energy savings as compared to transitioning to the first low-power mode; and configuring the processor system for the at least one low-power mode of the processor system in response to determining that transitioning to the at least one low-power mode of the processor system will result in cost savings comprises configuring the processor system for the second low-power mode in response to identifying that the cost of the second low-power mode will result in cost savings as compared to transitioning to the first low-power mode(Paragraphs 26, 51, the first power saving mode and the second power saving mode have different power saving efficiencies in different scenarios. In an embodiment, when a residency time in a power saving mode is longer than a threshold, the second power saving mode provides more power saving than the first power saving mode; however, when the residency time is shorter than the threshold, the second power saving mode provides less power saving than the first power saving mode. Processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode). Regarding claim 15 Li discloses computing device of claim 9, further comprising: identifying that each of a plurality of processor systems connected to a shared power source are configured in a low-power mode, the plurality of processor systems including the processor system; identifying a remaining time in a minimum residency time of the low- power mode of each of the plurality of processor systems, the minimum residency time of the low-power mode of each of the plurality of processor systems including the minimum residency time of the at least one low-power mode of the processor system; determining whether transitioning to a low-power mode of the shared power source will result in cost savings as compared to transitioning to the low- power mode of each of the plurality of processor systems based on the remaining time in the minimum residency time of the low-power mode of each of the plurality of processor systems; and configuring the shared power source for the low-power mode of the shared power source in response to determining that transitioning to a low-power mode of the shared power source will result in cost savings as compared to transitioning to the low-power mode of each of the plurality of processor systems(Paragraphs 14, 30, 51 the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time. Processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode). Regarding claim 17, Li discloses non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations for managing power modes of a processor system(Paragraph 9, The processing unit is configured to execute the software instructions to select a power saving mode from the at least the first power saving mode and the second power saving mode based on the threshold, and enter the determined power saving mode) comprising: identifying a minimum residency time of at least one low-power mode of the processor system based on current leakage at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR); identifying a cost of the at least one low-power mode of the processor system based in part on the minimum residency time of the at least one low- power mode of the processor system(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time); determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to a cost of at least one other power mode of the processor system; and configuring the processor system for the at least one low-power mode of the processor system in response to determining that transitioning to the at least one low-power mode of the processor system will result in cost savings(Paragraph 51, processing circuits determine a power saving mode based on the idle time and the target residency parameters. In an example, the processing circuits 130 compare the idle time with the target residency time TR. When the predicted idle time is longer than the target residency time TR, the processing circuits 130 determine to enter the second power saving mode). Regarding claim 18, Li discloses non-transitory processor-readable medium of claim 17, wherein the stored processor-executable instructions are further configured to cause the processor of the computing device to perform operations further comprising: identifying the actual current leakage at runtime of the processor system; and updating the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current under a present operation condition, and uses the Eq. 4 to determine the target residency time TR). Regarding claim 19, Li discloses non-transitory processor-readable medium of claim 17, wherein the stored processor-executable instructions are further configured to cause the processor of the computing device to perform operations further comprising: identifying an expected current leakage of the processor system; and identifying a minimum residency time of the at least one low-power mode of the processor system based on the expected current leakage of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 20, Li discloses method of claim 19, wherein the stored processor-executable instructions are further configured to cause the processor of the computing device to perform operations further comprising updating the minimum residency time of the at least one low-power mode of the processor system based on an expected current leakage of the processor system based on the minimum residency time of the at least one low-power mode of the processor system based on the actual current leakage at runtime of the processor system(Paragraph 42, the target residency time TR can be determined using any suitable technique. In an example, Eq. 4 is used to determine the target residency time TR. For example, processing circuits 130 suitably measure the active current and the leakage current I under a present operation condition, and uses the Eq. 4 to determine the target residency time TR. In another example, the target residency time is pre-determined for a combination of operational parameters and is stored in association with the operational parameters. Thus, when the operational parameters are determined, the corresponding target residency time can be determined). Regarding claim 21, Li discloses method of claim 1, further comprising: determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to one or more preconfigured cost thresholds(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time) Regarding claim 22, Li discloses computing device of claim 9, further comprising: determining based on the identified cost of the at least one low-power mode whether transitioning to the at least one low-power mode of the processor system will result in cost savings compared to one or more preconfigured cost thresholds(Paragraphs 14, 30, the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time) Response to Arguments Applicant's arguments have been fully considered but they are not persuasive. Applicant argues that paragraphs 14 and 30 of Li do not disclose the cost is energy consumed in transitioning into the low-power mode and operating in the low-power mode for a duration of the minimum residency time. Examiner respectfully disagrees. Paragraphs 14, 30 disclose the electronic device 100 is configured to have multiple power saving modes that can have different power saving efficiency in different scenarios. Threshold parameters are determined and are associated with the power saving modes. The threshold parameters are used by the electronic device 100 to determine a suitable power saving mode to enter under certain scenario. Due to the different entrance/exit latencies, the first power saving mode and the second power saving mode have different power saving efficiencies under different residency time). Paragraph 34 discloses the energy consumption (E1) during the residency time RT in the first power saving mode is calculated according to Eq. 1, where t1 denotes to a first latency for the first power saving mode, and is a sum of the first entrance latency t1N and the first exit latency t1X. This equation calculates the energy cost of transition related energy and the energy cost while residing in the power state and thus discloses the claimed the cost is energy consumed in transitioning into the low-power mode and operating in the low-power mode for a duration of the minimum residency time. Thus, Applicant’s arguments are not found persuasive. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMESH G PATEL/Primary Examiner, Art Unit 2187 Application/Control Number: 18/734,126 Page 2 Art Unit: 2176 Application/Control Number: 18/734,126 Page 3 Art Unit: 2176 Application/Control Number: 18/734,126 Page 4 Art Unit: 2176 Application/Control Number: 18/734,126 Page 5 Art Unit: 2176 Application/Control Number: 18/734,126 Page 6 Art Unit: 2176 Application/Control Number: 18/734,126 Page 7 Art Unit: 2176 Application/Control Number: 18/734,126 Page 8 Art Unit: 2176 Application/Control Number: 18/734,126 Page 9 Art Unit: 2176 Application/Control Number: 18/734,126 Page 10 Art Unit: 2176 Application/Control Number: 18/734,126 Page 11 Art Unit: 2176 Application/Control Number: 18/734,126 Page 12 Art Unit: 2176 Application/Control Number: 18/734,126 Page 13 Art Unit: 2176 Application/Control Number: 18/734,126 Page 14 Art Unit: 2176 Application/Control Number: 18/734,126 Page 15 Art Unit: 2176 Application/Control Number: 18/734,126 Page 16 Art Unit: 2176
Prosecution Insights