DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 3 – 5 are objected to for the following informalities:
It appears that in claim 3 line 2 that the character “n” should appear after the character “a” and before “integer multiple.”
Claims 4 and 5 depend on claim 3 and are objected to for the objection to claim 3.
Appropriate action is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 lines 2 and 6 recite the limitation “a host processor.” This makes it impossible to be certain if the later instance intends to introduce a new instance of “a host processor” or to refer to the original instance of the limitation. For claim interpretation purposes the later instance is read as “the host processor.”
Claims 15 – 20 depend on claim 4 and are rejected to for the same rejection to claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 12 – 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bellubbi et al. (hereinafter Bellubbi, US 2023/0102089) in view of Clark et al. (hereinafter Clark, US 5,361,356).
Regarding claim 1, Bellubbi discloses:
a method of managing a unified virtual memory (UVM), the method performed by
an electronic device comprising an accelerator and a host processor (see at least ph. [0427] for the GPU(s) including unified memory technology that utilizes using single unified virtual address spaces for CPUs and GPUs (host and an accelerator (GPU) that are part of the computing system/device), the method comprising:
in response to a memory request from the accelerator (see at least ph. [0472] describes aspects of GPU and CPU accessing memory pages, which are examples then of memory requests being issued), allocating to the accelerator, from among virtual address spaces of the UVM (from ph. [0472] when the GPU is accessing the memory pages it will have them allocated to itself upon the system completion of it accessing those pages), a virtual address of first virtual address reserved for the accelerator (from ph. [0427] where the unified memory allows the virtual memory address space for the GPU and therefore simplifying the programming and porting of the GPU applications related to the memory page accesses from that memory, indicating then that the GPU/accelerator has its own space (as the CPU is not accessing these GPU related applications)); and
in response to a memory request from the host processor, allocating to the host
processor, from among the virtual address spaces, a virtual address of second virtual address that are exclusive of the first virtual address (from ph. [0427] discloses the CPU(s) looking up its page tables for virtual-to-physical mapping of addresses and sending them to the GPU, and this indicates that the CPU had its own access and not the GPU, and these are described as part of the unified memory technology that allows unified address spaces for both the CPU and GPU).
Bellubi does not expressly disclose, however, Clark discloses:
virtual address subspaces (see at least col. 6 ln. 16 – 29 for new type of virtual address spaces called subspaces).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Bellubi by the teachings of Clark in order to more efficiently utilize address spaces for common utilizations but still maintain atomization.
Regarding claim 14, Bellubbi discloses:
a device for managing a virtual memory (the device of at least Fig. 16 that allows the functioning of the virtual memory features of at least ph. [0427]), the device comprising:
a host processor configured to, in response to a memory request from an accelerator, allocate to the accelerator, from among virtual address spaces, a virtual address of first virtual address reserved for the accelerator (at least ph. [0427] discloses the CPU using its virtual-to-physical mapping of addresses and sending them to the GPU which is part of the unified memory technology that supports unified virtual address spaces for the CPU and GPU and this by the GPU and response from the CPU indicates they CPU was requested to supply the needed data to the GPU and then we see that the GPU is able to itself simplify its own programming and porting of applications with its space, indicating that it’s the space for the GPU itself); and
a host processor allocation device configured to, in response to a memory request from a host processor, allocate to the host processor, from among the virtual address spaces, a virtual address of second virtual address that are exclusive of the first virtual address subspaces (at least ph. [0427] discloses the CPU using its virtual-to-physical mapping of addresses and sending them to the GPU which is part of the unified memory technology that supports unified virtual address spaces for the CPU and GPU and this by the GPU and response from the CPU indicates they CPU was requested to supply the needed data to the GPU and we note that the CPU has access to its own memory spaces that the GPU did not access).
Bellubi does not expressly disclose, however, Clark discloses:
virtual address subspaces (see at least col. 6 ln. 16 – 29 for new type of virtual address spaces called subspaces).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Bellubi by the teachings of Clark in order to more efficiently utilize address spaces for common utilizations but still maintain atomization.
Regarding claims 2 and 15, the rejections of claims 1 and 14 are incorporated and Bellubbi discloses:
dividing, among the virtual address spaces of the UVM, the first virtual address
and the second virtual address subspaces by reserving the first virtual address for the accelerator before the memory request from the accelerator and before the memory request from the host processor (at least ph. [0427] discloses the CPU using its virtual-to-physical mapping of addresses and sending them to the GPU which is part of the unified memory technology that supports unified virtual address spaces for the CPU and GPU and this by the GPU and response from the CPU indicates they CPU was requested to supply the needed data to the GPU and the mapping tables of the CPU then were in existence before the sending and requestion of the information, if not it would require the creation thereof, which is not require by the reference as it simply access the table for the mapping information).
Bellubi does not expressly disclose, however, Clark discloses:
virtual address subspaces (see at least col. 6 ln. 16 – 29 for new type of virtual address spaces called subspaces).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Bellubi by the teachings of Clark in order to more efficiently utilize address spaces for common utilizations but still maintain atomization.
Regarding claim 12, the rejection of claim 1 is incorporated and Bellubbi discloses:
a compute unified device architecture (CUDA) implemented at least in part by the host processor and the accelerator (see at least ph. [0072] that discloses that CUDA is available as a software resource and therefore processing of processes associated with the handling of the CPUs and GPUs in at least ph. [0427] will be used/implemented in their respective executions).
Regarding claims 13 and 20 the rejections of claims 1 and 14 are incorporated and Bellubbi discloses:
a non-transitory computer-readable storage medium storing instructions that, when executed by the host processor and/or the accelerator, cause the host processor and/or
the accelerator to perform the method of claim 1 (see at least Fig. 16 for such a medium utilized on the computing device disclosed that implements the features disclosed throughout the reference that require computing instructions to be performed).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bellubbi in view of Clark and further in view of Backensto et al. (hereinafter Clark, US 5,361,356).
Regarding claim 10, the rejection of claim 1 is incorporated and Bellubbi virtual address spaces for the GPU/accelerator and host processors in the rejection of claim 1.
Bellubbi and Clark do not expressly disclose, however, Backensto discloses:
restoring a virtual address allocated to the program in the first virtual address subspaces reserved for the program in response to a checkpoint restoration request (see col. 25 ln. 46 – 62 for restore g pages from checkpoints as part of virtual machine infrastructure and the restoration is to the same virtual address occupied within the address space of the original process where the checkpoint originated and this occurs for any number of programs with respective virtual address, including first address spaces); and
restoring a virtual address allocated to the program in the second virtual address subspaces in response to the checkpoint restoration request (see col. 25 ln. 46 – 62 for restore g pages from checkpoints as part of virtual machine infrastructure and the restoration is to the same virtual address occupied within the address space of the original process where the checkpoint originated and this occurs for any number of programs with respective virtual address, including second address spaces).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Bellubi, as modified by Clark, by the teachings of Backensto in order to more efficiently utilize address spaces for common utilizations but still maintain atomization.
Regarding claim 11, the rejection of claim 10 is incorporated and Bellubbi discloses:
multiple accelerators including the accelerator (see at least ph. [0427] for multiple GPUs as disclosed, which are accelerators and any one of them at a given time is a given GPU that is performing processes).
Bellubi does not expressly disclose, however, Clark discloses:
virtual address subspaces (see at least col. 6 ln. 16 – 29 for new type of virtual address spaces called subspaces).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Bellubi by the teachings of Clark in order to more efficiently utilize address spaces for common utilizations but still maintain atomization.
Bellubbi and Clark do not expressly disclose, however, Backensto discloses:
restoring of the virtual address allocated to the program comprises restoring a virtual address specifically allocated to a corresponding program in first virtual address reserved for each program (see col. 25 ln. 46 – 62 for restore g pages from checkpoints as part of virtual machine infrastructure and the restoration is to the same virtual address occupied within the address space of the original process where the checkpoint originated and this occurs for any number of programs each with a respective virtual address,).
Allowable Subject Matter
Claims 3 – 9 and 16 - 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
References Cited Not Relied Upon
Kayi et al. (US 2023/008048) discloses the use of global virtual address space memory with shared virtual address view for memory that is distributed across various accelerator devices.
Napier et al. (US 11,314,508) discloses a virtual address space that corresponds to external memory devices and FPGA block RAM (FPGA is an accelerator).
Appu et al. (US 2021/0142438) discloses GPUs (an accelerator) and CPUs sharing the same virtual address space.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG C DORAIS whose telephone number is (571)270-3371. The examiner can normally be reached M-F 9:00 am - 6:00pm.
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/CRAIG C DORAIS/Primary Examiner, Art Unit 2198
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