DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/04/2024 was filed with the instant application for consideration. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 14 of U.S. Patent No. 10,897,738 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because :The instant application claim common subject matter, as follows: (since all the claims recited similar limitations, examiner only shows independent claims 1, 10, 18 and 21-22 as example in claim comparison table):
Instant application: 18/734,324
U.S. Patent No. : US 10,897,738 B2
A semiconductor device comprising: an application processor comprising:
a first processor core configured to process a first amount of data per unit time; and
a second processor core configured to process a second amount of data per unit time, which is smaller than the first amount of data, and
a communication processor configured to receive a data packet and generate an alarm signal and send the alarm signal to the application processor,
wherein the application processor activates the first processor core or the second processor core with a first power with a first power level provided to the application processor, and the application processor activates the first processor core or the second processor core with a second power with a second power level smaller than the first power level provided to the application processor in response to the alarm signal from the communication processor.
An application processor comprising:
a first processor core that processes a first amount of data per unit time; and
a second processor core that processes a second amount of data per unit time, which is larger than the first amount of data,
wherein the application processor activates the first processor core or the second processor core based on at least one of a size of a data packet received wirelessly from an external device by a communications processor and an amount of power supplied to the communications processor wherein the power supplied to the communications processor is indicated by an amount of current supplied to the communications processor,
wherein the application processor activates: the first processor core in response to determining the amount of current supplied to the communications processor is equal to a first magnitude, and the second processor core in response to determining the amount of the current supplied to the communications processor is equal to a second magnitude that is larger than the first magnitude.
10. A semiconductor device comprising: an application processor comprising: a first processor core configured to process a first amount of data per unit time; and a second processor core configured to process a second amount of data per unit time, which is smaller than the first amount of data, a lookup table used to determine whether to activate the first processor core or the second processor core; and a communication processor configured to receive a data packet, generate an alarm signal based on a size of the data packet and the lookup table, and send the alarm signal to the application processor, wherein the application processor activates the first processor core or the second processor core based on the alarm signal from the communication processor.
18. A method for operating a semiconductor device including an application processor comprising a first processor core configured to process a first amount of data per unit time and a second processor core configured to process a second amount of data per unit time smaller than the first amount of data, and a communication processor configured to receive a data packet and process the data packet, the method comprising: monitoring, by the application processor, a power provided to the application processor or the communication processor; and activating, by the application processor, the first processor or the second processor in response to a power level of the monitored power.
3. A system on chip (SoC) comprising: an application processor comprising: a first processor core that processes a first amount of data per unit time, and a second processor core that processes a second amount of data per unit time, which is larger than the first amount of data; a communications processor that wirelessly receives a message signal via an antenna from an external device and determines a size of a data packet within the message signal; and a power management integrated circuit (IC) that supplies power to the communications processor, wherein the application processor activates the first processor core or the second processor core based on at least one of an amount of the power supplied to the communications processor by the power management IC and the size of the data packet wherein the amount of power supplied to the communications processor by the power management IC is indicated by an amount of current supplied to the communications processor by the power management IC wherein the amount of power supplied to the communications processor by the power management IC is indicated by an amount of current supplied to the communications processor by the power management IC.
21. A semiconductor device comprising: an application processor comprising a first processor core configured to process a first amount of data per unit time and a second processor core configured to process a second amount of data per unit time smaller than the first amount of data; and a communication processor configured to receive a data packet and process the data packet, wherein the application processor is configured to monitor a power provided to the application processor or the communication processor, and activate the first processor or the second processor in response to a power level of the monitored power.
22. A semiconductor device comprising: an application processor comprising: a first processor core configured to process a first amount of data per unit time; and a second processor core configured to process a second amount of data per unit time, which is smaller than the first amount of data, and a communication processor configured to receive a data packet and generate an alarm signal and send the alarm signal to the application processor, wherein the application processor activates the first processor core or the second processor core with a first power with a first power level provided to the application processor in response to the alarm signal from the communication processor, and the application processor activates the first processor core or the second processor core with a second power with a second power level smaller than the first power level provided to the application processor.
14. A computer program stored on a non-transitory computer-readable medium for execution by an application processor of a system on chip (SoC) to activate a first processor core or a second processor core of the application processor, the first processor core processing a first amount of data per unit time, the second processor core processing a second amount of data per unit time, which is larger than the first amount of data, and the application processor being in communication with a communications processor of the SoC that wirelessly receives a data packet within a message signal via an antenna, the computer program comprising instructions that: activate the first processor core or the second processor core based on at least one of an amount of power supplied to the communications processor by a power management integrated circuit (IC) of the SoC and a size of the data packet wherein the power supplied to the communications processor is indicated by an amount of current supplied to the communications processor, wherein the application processor activates: the first processor core in response to determining the amount of current supplied to the communications processor is equal to a first magnitude, and the second processor core in response to determining the amount of the current supplied to the communications processor is equal to a second magnitude that is larger than the first magnitude.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Vanka et al (US 20150261583 A1), hereinafter, “Vanka” in view of Naim et al (US 10,383124 B1), hereinafter, “Naim” further in view of Rao et al (CN 102783072 A), hereinafter, “Rao”.
Regarding claim 1, Vanka discloses: A semiconductor device (Vanka: fig 1, CPU 110 a semiconductor device, para [0033], where, “discrete electronic components, an integrated circuit, an application-specific integrated circuit having appropriately configured semiconductor devices and resistive elements”) comprising: an application processor (Vanka: fig 1 and fig 4, CPU 110, , para [0060]-[0062], where, in fig 1, PCD 100 including an “application processor”) comprising: a first processor core configured to process a first amount of data per unit time (Vanka: fig 1 and fig 4, First Core 410 equivalent to “first processor core”, para [0060], where, data received by the first processing component for processing per unit time such as byte per second); and
a second processor core configured to process a second amount of data per unit time (Vanka: fig 1 and fig 4, Second Core 420 equivalent to “second processor core”, para [0062] and [0065], where, data received by the second processing component for processing per unit time such as byte per second);
wherein the application processor activates the first processor core or the second processor core with a first power with a first power level provided to the application processor (Vanka: para [0025], where, “the terms "workload,", "process load," "process workload," and "graphical workload" are used interchangeably and “generally directed toward the processing burden” (equivalent to “alarm”), or percentage of processing burden, that is associated with, or may be assigned to, a given processing component”, fig 5-6, para [0111], where, extend processor cores in order to sending data packets to the appropriate destination cores), and the application processor activates the first processor core or the second processor core (Vanka: fig 5-6, para [0111], where, extend processor cores in order to sending data packets to the appropriate destination cores),
Vanka does not explicitly teach, however, Naim teaches: first amount of data per unit time and second amount of data per unit time, which is smaller than the first amount of data, and a communication processor configured to receive a data packet and generate an alarm signal and send the alarm signal to the application processor;
Naim teaches: first amount of data per unit time and second amount of data per unit time, which is smaller than the first amount of data, and a communication processor configured to receive a data packet (Naim: para (3), where, “receiving a second user data packet having a second packet size, the second user data packet assigned a second quality of service class identifier, wherein the second data packet size is larger than the first data packet size”);
and generate an alarm signal and send the alarm signal to the application processor (Naim: para (12), where, “As time progresses, with the acknowledgement of previously unacknowledged data packets, data packet size gradually increases until a saturation point is reached, beyond which the data packets no longer increase in size. Data packets are often segmented into different TCP regions, based on maturity of the TCP session and/or the size of the data packets”. These regions indicate data packets size and session maturity (equivalent to “generating alarm”);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Vanka with the teaching of Naim, to incorporate “calculating packet data size” for the advantage of optimizing for the quality of service (Naim: [col 1, lines (55-56)]);
Neither Vanka nor Naim explicitly teach: the application processor activates the first processor core or the second processor core with a second power with a second power level smaller than the first power level provided to the application processor in response to the alarm signal from the communication processor.
Rao teaches: the application processor activates the first processor core or the second processor core with a second power with a second power level smaller than the first power level provided to the application processor in response to the alarm signal from the communication processor (Rao: claim 7, where, teaches packet size to change transmission power; para [0052], where, “the provided Ks=L 25 in power control rules described in 3GPP TS 36.213 (relative to Ks=O), the LTE standard allows adjust the UE emitting power spectral density in different transport block sizes (accurately speaking, modulation and coding scheme). Correspondingly, if station 10 grant the UE 20 changes the transport block size, the base station 10 sets the power control rule Ks=L 25. This may use a particular indicator sending scheduling grant is executed in the step S320 of FIG. 3. when the selecting smaller packet size defined from UE 20, it also reduces the emitting power spectral density, the advantage of this is by generating less interference, improve the UE battery life and improves system performance. Of course, if the larger packet size is selected, the UE can increase its emitting power spectral density”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Vanka with the teaching of Naim, to incorporate “the application processor activates the first processor core or the second processor core with a second power with a second power level smaller than the first power level provided to the application processor in response to the alarm signal from the communication processor” in order to improve the UE battery life and improves system performance (Rao: para [0052]);
Regarding claims 10 and 21-22, the claim includes features identical to the subject matter mentioned in the rejection to claim 1 above. The claims are mere reformulation of claim 1 in order to define the corresponding information processing apparatus, and the rejection to claim 1 is applied hereto. Additionally, the claim includes a look-up table. However, Vanka discloses the look-up table (Vanka: para [0073]).
Regarding claim 18, the claim includes features identical to the subject matter mentioned in the rejection to claim 1 above. The claims are mere reformulation of claim 1 in order to define the corresponding packet classification method, and the rejection to claim 1 is applied hereto.
Regarding claim 2, Vanka modified by Naim further modified by Rao disclose: The semiconductor device of claim 1 (Vanka: fig 1, CPU 110 a semiconductor device, para [0033], where, “discrete electronic components, an integrated circuit, an application-specific integrated circuit having appropriately configured semiconductor devices and resistive elements”), wherein the communication processor generates the alarm signal in response to determining the received data packet being a normal message between a large-volume message and the normal message (Rao: para [0010], where, “user equipment can further receiving a scheduling grant, including indicator (equivalent to “alarm”) indicates user equipment from the transmission block size is permitted through selected transmission mode defined in the block size change the uplink transmission of packet size. If the indicator indicates that user equipment is permitted by transmission way of block size change”).
Regarding claim 3, Vanka modified by Naim further modified by Rao disclose:3. The semiconductor device of claim 1 (Vanka: fig 1, CPU 110 a semiconductor device, para [0033], where, “discrete electronic components, an integrated circuit, an application-specific integrated circuit having appropriately configured semiconductor devices and resistive elements”), further comprising: a power management integrated circuit (PMIC) that supplies power to the application processor and the communication processor, wherein the PMIC provide a first amount current to the application processor to provide the first power to the application processor (Vanka: fig 5, module 524 and module 534 equivalent to “power management integrated circuit (IC), para [0084], perform the power management, para [0051], where, instruction may be executed by one or more core in the multicore CPU 110 in order to enable DCVS aware inter-processor communications); and the PMIC provide a second amount current smaller than the first amount current (Naim: para (3), where, “receiving a second user data packet having a second packet size, the second user data packet assigned a second quality of service class identifier, wherein the second data packet size is larger than the first data packet size”); to the application processor to provide the second power to the application processor (Vanka: fig 1 and 4, para [0078]).
Regarding claims 4 and 13, Vanka modified by Naim further modified by Rao disclose: further comprising: a sensor (Vanka: fig 1, module 157A and module 157B are the sensors, para [0047]);
a communications proc, wherein the communications processor is configured to provide the alarm signal to the application processor after the application processor (Rao: para [0010], where, “user equipment can further receive a scheduling grant, including indicator (equivalent to “alarm”) indicates user equipment from the transmission block size is permitted through selected transmission mode defined in the block size change the uplink transmission of packet size. If the indicator indicates that user equipment is permitted by transmission way of block size change”), has been awakened by a signal received by the sensor in response to a user touching a touch sensor (Vanka: fig 2 A, 2B, para [0052]-[0053], where, percentage work load equivalent to “predetermined size of data”, fig 1, “touch screen controller 130” is coupled to the multi-core CPU 110).
Regarding claims 5 and 14, Vanka modified by Naim further modified by Rao disclose: further comprising: a dynamic random access memory (DRAM) device (Naim: col 3, lines 45-54), wherein the application processor and the communications processor are configured to share the DRAM device (Naim: col 3, lines45-54).
Regarding claims 6 and 15, Vanka modified by Naim further modified by Rao disclose: wherein the application processor is configured to use a first area of the DRAM device and the communications processor uses a second area of the DRAM device (Naim: col 3, lines45-54).
Regarding claims 7 and 16, Vanka modified by Naim further modified by Rao disclose: The semiconductor device of claim 1 (Vanka: fig 1, CPU 110 a semiconductor device, para [0033], where, “discrete electronic components, an integrated circuit, an application-specific integrated circuit having appropriately configured semiconductor devices and resistive elements”), wherein the application processor and the communications processor are disposed in a first chip (Vanka: fig 1 and fig 4, CPU 110, para [0060]-[0062], where, in fig 1, PCD 100 includes an “application processor” and communication processor which may be termed as first chip).
Regarding claims 8 and 17, Vanka modified by Naim further modified by Rao disclose: The semiconductor device of claim 7, wherein the power management integrated circuit (IC) is disposed outside the first chip (Vanka: fig 1 and 4, para [0033], where, “portions of the system, may be implemented in hardware or software. If implemented in hardware, the devices can include any, or a combination of, the following technologies, which are all well known in the art: discrete electronic components, an integrated circuit, an application-specific integrated circuit having appropriately configured semiconductor devices and resistive elements”).
Regarding claim 9, Vanka modified by Naim further modified by Rao disclose: The semiconductor device of claim 1, wherein the application processor comprises a lookup table (Vanka: para [0073], where, a look-up table is referred) used to determine whether to activate the first processor core or the second processor core (Vanka: fig 5-6, para [0111], where, extend processor cores in order to sending data packets to the appropriate destination cores).
Regarding claims 11 and 12, Vanka modified by Naim further modified by Rao disclose: The semiconductor device of claim 10, wherein the communication processor generates the alarm signal (Naim: para (12), where, “As time progresses, with the acknowledgement of previously unacknowledged data packets, data packet size gradually increases until a saturation point is reached, beyond which the data packets no longer increase in size. Data packets are often segmented into different TCP regions, based on maturity of the TCP session and/or the size of the data packets”. These regions indicate data packets size and session maturity (equivalent to “generating alarm”);
if the size of the data packet is below a second value in the lookup table (Vanka: para [0073], where, an alarm was generated), and the application processor activates the second processor core based on the alarm signal (Vanka: fig 5-6, para [0111], where, extend processor cores in order to sending data packets to the appropriate destination cores).
Regarding claims 19 and 20, Vanka modified by Naim further modified by Rao disclose:19. The method of claim 18, wherein monitoring the power comprises monitoring the power to the communication processor (Vanka: fig 1 and 4, PCD100 includes application processor and communication processor monitors the DCVS module 424, para [0024]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIZAM U AHMED whose telephone number is (571)272-9561. The examiner can normally be reached Mon-Fry, 7:00 AM-6:00 PM PST.
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/NIZAM U AHMED/Primary Examiner, Art Unit 2461
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