DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The recitations “an n comparator”, “an n+1 comparator”, and “an n-1 comparator” in claims 1-15 make the claims are unclear and/or indefinite (e.g., when the value of “n” is zero or negative). It is also unclear how do “an n comparator”, “an n+1 comparator”, and “an n-1 comparator” relate to “a plurality of comparators” as cited in the independent claims 1 and 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al., “A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS”, IEEE Transactions on Circuits and Systems-l: Regular Papers, Vol. 69, No. 10, October 2022, pp. 3954-3964 (cited by the applicant).
Regarding claim 1, Lee et al. (Fig. 2a) discloses “an analog-to-digital converter, ADC, using a plurality of capacitor digital-to-analog converters, CDACs, (CDACs of figure 2(a)) the ADC comprising:
a plurality of comparators (C1...C6);
a plurality of CDACs (CDACAP, CDACBP, CDACAN, CDACBN) each configured to generate a reference voltage (reference voltages respectively generated); and
a switch circuit (e.g. multiplexers upstream of C2) configured to connect one CDAC among the plurality of CDACs (e.g. CDACAP, CDACBP) to an n+1 comparator (e.g. C2), based on a digital value output from an n comparator (C1, whose output provides the selection signals (S2)) among the plurality of comparators, wherein the n+1 (C2) comparator is configured to output a digital value based on a result of comparing the reference voltage of one CDAC among the plurality of CDACs with an input voltage (VINP, VINN; see also figure 3(b), section Il. B)”.
Regarding claim 2, Lee et al. (Fig. 2a) discloses the ADC of claim 1, further comprising: a logic circuit (SAR Logic) configured to sample a digital value output from an n-1 comparator among the plurality of comparators, wherein the plurality of CDACs are each configured to generate the reference voltage, based on the sampled digital value (SAR Logic sampling D[1:6] and producing the digital values for CDACAP, CDACBP, CDACAN, CDACBN at each cycle.
Regarding claim 3, Lee et al. (Fig. 2a) discloses the ADC of claim 2, wherein the logic circuit includes a plurality of successive approximation register (SAR) logic circuits (2 SAR Logics are shown in Fig. 2a), and the plurality of SAR logic circuits are configured to sample the digital value output from the n-1 comparator, and transfer the sampled digital value to the plurality of CDACs respectively connected to the plurality of SAR logic circuits (SAR Logics sampling D[1:6] and producing the digital values for CDACAP, CDACBP, CDACAN, CDACBN at each cycle).
Regarding claim 4, Lee et al. (Fig. 2a) discloses the ADC of claim 3, wherein the logic circuit includes a storage unit storing the sampled digital value, and the storage unit is connected to the plurality of SAR logic circuits (the flip-flops in Fig. 6 constituting the storage unit).
Regarding claim 5, Lee et al. (Fig. 2a) discloses the ADC of claim 3, wherein the plurality of CDACs include a first CDAC configured to generate a first reference voltage when the digital value output from the n comparator is expected to be 1, based on the sampled digital value; and a second CDAC configured to generate a second reference voltage when the digital value output from the n comparator is expected to be 0, based on the sampled digital value (section III.B, in particular “CDACNA are set to produce a threshold voltage of + 1/2VREF in a differential standpoint (CDACPA - CDACNA) for the case where the value of MSB is 1, and CDACPB - CDACNB produces -1/2VREF, corresponding to the case where MSB is 0”.
Regarding claim 6, Lee et al. (Fig. 2a) discloses the ADC of claim 5, wherein the switch circuit (upstream multiplexers of C1…C6) is configured to transfer the first reference voltage of the first CDAC to the n+1 comparator when the digital value output from the n comparator is 1, and transfer the second reference voltage of the second CDAC to the n+1 comparator when the digital value output from the n comparator is 0 (section III, B, second paragraph).
Regarding claim 7, Lee et al. (Fig. 2a) discloses the ADC of claim 1, wherein the plurality of CDACs are configured to generate the respective reference voltages before the digital value is output from the n comparator (Abstract, in particular” Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations.”).
Regarding claim 8, Lee et al. (Fig. 2a) discloses the ADC of claim 1, wherein the plurality of CDACs are connected to each other in parallel (Fig. 2a).
Regarding claim 9, Lee et al. (Fig. 2a) discloses the ADC of claim 1, further comprising: at least one clock generator configured to generate a clock with respect to each of the plurality of comparators (Fig. 2a; CKG Gen. blocks).
Regarding claim 10, Lee et al. (Fig. 2a) discloses the ADC of claim 2, wherein the n comparator (e.g., comparator C2) is a comparator configured to operate in a current step, the n-1 comparator is a comparator (C1) configured to operate in a step previous to the current step, and the n+1 comparator (C3) is a comparator configured to operate in a step subsequent to the current step (Fig. 2a).
Regarding claim 11, Lee et al. (Fig. 2a) discloses “an analog-to-digital converter, ADC, using a plurality of capacitor digital-to-analog converters, CDACs, (CDACs of figure 2(a)) the ADC comprising:
a plurality of comparators (C1...C6);
a first CDAC (CDACAP, CDACBP) configured to generate a first reference voltage (its output) based on a digital value output from an n-1 comparator among the plurality of comparators a second CDAC (CDACAN, CDACBN) configured to generate a second reference voltage based on the digital value output from the n-1 comparator among the plurality of comparators (see e.g., section III.B concerning the conversion of the bit MSB-2: “[...] for the next (MSB-2) bit comparison, the CDAC outputs should make switching trajectories depending on the value of MSB. If the value of MSB is 1, the input voltage has to be compared with +1/4VREF and +3/4VREF as the value of the (MSB-1)th bit is being speculated. On the other hand, if the value of MSB is 0, the input has to be compared with -1/4VREF and -3/4VREF'); and
a switch circuit (e.g. multiplexers upstream of C1...6) configured to connect the first CDAC or the second CDAC to an n+1 comparator based on a digital value output from an n comparator among the plurality of comparators, wherein the n+1 comparator is configured to output a digital value based on a result of comparing the first reference voltage or the second reference voltage with an input voltage (VinP, VinN; see also figure 3(b), section II.B)”.
Regarding claim 12, Lee et al. (Fig. 2a) discloses the ADC of claim 11, further comprising: a logic circuit (SAR Logic) configured to sample a digital value output from an n-1 comparator, wherein the first reference voltage or the second reference voltage is generated based on the sampled digital (SAR Logic sampling D[1:6] and producing the digital values for CDACAP, CDACBP, CDACAN, CDACBN at each cycle).
Regarding claim 13, Lee et al. (Fig. 2a) discloses the ADC of claim 11, wherein the switch circuit (upstream multiplexers of C1…C6) is configured to transfer the first reference voltage of the first CDAC to the n+1 comparator when the digital value output from the n comparator is 1, and transfer the second reference voltage of the second CDAC to the n+1 comparator when the digital value output from the n comparator is 0 (section III, B, second paragraph).
Regarding claim 14, Lee et al. (Fig. 2a) discloses the ADC of claim 11, wherein the first CDAC is configured to generate the first reference voltage and the second CDAC is configured to generate the second reference voltage before the digital value is output from the n comparator (Abstract, in particular” Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations.”).
Regarding claim 15, Lee et al. (Fig. 2a) discloses the ADC of claim 11, wherein the first CDAC and the second CDAC are connected to each other in parallel (Fig. 2a).
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845