DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on is acknowledged.
It is argued by the Applicants that the search and examination of all the claims may be made without serious burden.
However, MPEP 808.02 identifies 3 options to support the burden requirement:
different field of search
separate classification with separate field of search
separate status with separate field of search
Each of these requirements includes a separate field of search component.
Separate field of search means it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JENG et al. 20180068978.
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Regarding claim 1, fig. 2K of JENG discloses a semiconductor package comprising:
a lower redistribution wiring layer 20 having first redistribution wirings, the lower redistribution wiring layer having a first region (region directly below 36) and a second region (region directly below 50) surrounding the first region (region of 50 is bigger than region of 36 and therefore surrounding the first region);
a semiconductor chip 36 on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
at least one bridge die stack (stack 50 is a type of bridge) on the second region of the lower redistribution wiring layer and including a plurality of bridge dies (bottom three 52 dies) sequentially stacked on one another, each bridge die of the plurality of bridge dies including a plurality of through-vias 56 that are electrically connected to the first redistribution wirings;
a sealing member 58 on the lower redistribution wiring layer covering the semiconductor chip and the at least one bridge die stack; and
an upper redistribution wiring layer (as labeled by examiner above) on (the bottom of) the sealing member and including second redistribution wirings electrically connected to the plurality of through-vias of the at least one bridge die stack.
Regarding claim 20, fig. 2K of JENG A semiconductor package comprising:
a first redistribution wiring layer having first redistribution wirings, the first redistribution wiring layer having a chip mounting region and a peripheral region surrounding the chip mounting region;
a semiconductor chip on the chip mounting region of the first redistribution wiring layer;
a plurality of bridge die stacks (36 and bottom 52 forms one stack and second 52 and third 52 form another stack) on the peripheral region of the first redistribution wiring layer, each bridge die stack including a plurality of sequentially stacked bridge dies 36 and bottom 52 for one stack and second 52 and third 52 for the second stack), each bridge die including a plurality of through- vias (36C and 56) configured to be electrically connected to substrate pads of a package substrate (see fig. 2K configuration);
a sealing member 58 covering the semiconductor chip and the plurality of bridge die stacks on the first redistribution wiring layer; and
a second redistribution wiring layer on the sealing member and including a second redistribution wirings electrically connected to the plurality of through- vias.
Regarding claim 3, it would have been necessary the case the JENG discloses wherein the plurality of through-vias are arranged in an array within the plurality of bridge dies when viewed from a plan view.
Regarding claim 4, par [0031] of JENG discloses that the through via structures 36C are through silicon vias (TSVs) and par [024] the chip with through via structures is an active device chip including TSVs integrated therein], as such JENG necessary discloses wherein each bridge die of the plurality of bridge dies of the at least one bridge die stack comprises: a silicon substrate having a first surface and a second surface opposite to the first surface; the plurality of through-vias penetrating the silicon substrate; a first insulating layer (alternating layer between 52s) in the first surface of the silicon substrate exposing first ends of the plurality of through-vias; and a second insulating layer (alternating layer between 52s where one layer is first and the layer is second with respect one another) in the second surface of the silicon substrate exposing second ends of the plurality of through-vias (see fig. 2K configuration).
Regarding claim 5, fig. 2K of JENG discloses wherein a first insulating layer of a first bridge die among the at least one bridge die stack and a second insulating layer of a second bridge die stacked on the first bridge die are bonded to each other, and a through-via of the first bridge die and a corresponding through-via of the second bridge die are bonded to each other.
Regarding claim 7, fig. 2K of JENG discloses wherein the at least one bridge die stack further comprises: a plurality of connection pads (surface of 56s), each connection pad of the plurality of connection pads respectively on the second ends of the plurality of through-vias on a second insulating layer of a lowermost bridge die; and a protective layer 59 on the second insulating layer of the lowermost bridge die exposing the plurality of connection pads.
Regarding claim 8, fig. 2K of JENG discloses wherein the at least one bridge die stack further includes a plurality of conductive bumps 54 each respectively on the plurality of connection pads.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 9-10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over JENG.
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Regarding claim 1, fig. 4K of JENG discloses a semiconductor package comprising:
a lower redistribution wiring layer 20 having first redistribution wirings, the lower redistribution wiring layer having a first region (region directly below 30) and a second region (region directly below 50) surrounding the first region (region of 50 is bigger than region of 36 and therefore surrounding the first region);
a chip 30 on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
at least one bridge die stack (stack 50 is a type of bridge) on the second region of the lower redistribution wiring layer and including a plurality of bridge dies (bottom three 52 dies) sequentially stacked on one another, each bridge die of the plurality of bridge dies including a plurality of through-vias 56 that are electrically connected to the first redistribution wirings;
a sealing member 58 on the lower redistribution wiring layer covering the semiconductor chip and the at least one bridge die stack; and
an upper redistribution wiring layer 70 on (the bottom of) the sealing member and including second redistribution wirings electrically connected to the plurality of through-vias of the at least one bridge die stack.
JENG does not disclose that the chip 30 is a semiconductor chip.
However, it would have been obvious to for a package comprising wherein the chip is a semiconductor chip in order to use semiconductor technology of almost 100 years in order ensure working and cost effective chip.
Regarding claim 20, fig. 4K of JENG a semiconductor package comprising:
a first redistribution wiring layer 20 having first redistribution wirings, the first redistribution wiring layer having a chip mounting region (region under 30) and a peripheral region surrounding the chip mounting region (region under 50);
a chip 30 on the chip mounting region of the first redistribution wiring layer;
a plurality of bridge die stacks (stack 50 and 36 on left form one stack and stack of 50 and 36 or right form another stack = stacks) on the peripheral region of the first redistribution wiring layer, each bridge die stack including a plurality of sequentially stacked bridge dies (stack of three 52s on bottom of 50 and 36), each bridge die including a plurality of through- vias (56 and 36C) configured to be electrically connected to substrate pads 22s (fig. 4H) of a package substrate;
a sealing member 58 covering the semiconductor chip and the plurality of bridge die stacks on the first redistribution wiring layer; and
a second redistribution wiring layer on the sealing member and including a second redistribution wirings electrically connected to the plurality of through- vias.
Regarding claim 2, JENG discloses claim 1, but does not discloses of wherein the at least one bridge die stack has a rectangular shape when viewed from a plan view.
However, note the MPEP addresses changes in shape under MPEP §2144.04.IV, which provides guidance on obviousness rejections based on modifications in size, proportion, or shape. The key principle is that if a claimed invention differs from prior art only in its shape or relative dimensions, and the change does not affect performance or function, it is typically not patentably distinct from the prior art (Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777, Fed. Cir. 1984).
As such it would have been obvious to form a package wherein the at least one bridge die stack has a rectangular shape when viewed from a plan view in order to meet the applicant’s design specification.
Regarding claim 6, it would have been obvious to form a package comprising wherein the first insulating layer and the second insulating layer include silicon oxide, silicon nitride, or silicon carbon nitride as these are well known insulators.
Regarding claims 9-10, JENG does not disclose wherein each of the plurality of through-vias has a diameter within a range of 100 um to 300 um; wherein each through-via of the plurality of through-vias has a height within a range of 380 um to 760 um.
The MPEP recognizes that merely changing the size or proportion of a prior art device or process usually does not make it patentably distinct. For example, in In re Rinehart, the court held that simply scaling up a prior art process that could already be scaled does not establish patentability for the scaled-up version. Similarly, in Gardner v. TEC Syst., Inc., a claimed device differing only in relative dimensions from prior art was not patentably distinct if it performed the same function as the prior art device.
As such it would have been obvious to form a package comprising wherein each of the plurality of through-vias has a diameter within a range of 100 um to 300 um; wherein each through-via of the plurality of through-vias has a height within a range of 380 um to 760 um in order to meet the applicant’s design specification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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