DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected for indefiniteness.
Regarding claim 12, the claim recites, "the electronic component includes a region on the protruded structure and a region on the opening." The use of "a region" twice in this limitation is improper usage of antecedent basis. To further prosecution, Examiner will assume the claim should read, "the electronic component includes a region on the protruded structure and a second region on the opening." Proper correction is required.
Regarding claim 19, the claim recites, "the semiconductor is spaced apart from the electronic component." The is insufficient antecedent support for "the semiconductor." To further prosecution, Examine will assume the claim should read, "the semiconductor chip is spaced apart from the electronic component." Proper correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Shin (US 20250126717 A1) .
The applied reference has a common assignee of “Samsung” with the instant application despite being listed under “Samsung Electronics” compared to “Samsung Electro-Mechanics.” Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Shin teaches an electronic component package (10C, Fig 10) comprising: a substrate (110) including an insulating layer (111),
a wiring layer (121) including a first connection pad (1211R: 1211 on right side) and a second connection pad (1211L: 1211 on left side),
a protection layer (200) disposed on (shown on) the insulating layer (111), and
at least one protruded structure (202) disposed on (shown on) the protection layer (200), wherein
an opening (1211O: opening in 111 for pads 1211) exposing (shown exposing) at least a portion of each of the first connection pad (1211R) and the second connection pad (1211L) is defined in (shown in) the protection layer (200);
an electronic component (20) disposed on (shown on) the substrate (110), wherein
the electronic component (20) includes a first electrode (21R: 21 on right side) electrically connected (shown electrically connected) to the first connection pad (1211R) and a second electrode (21L: 21 on left side) electrically connected (shown electrically connected) to the second connection pad (1211L); and
a molding material (M: not shown; well known to be used during the molding process; It is obvious Shin would use molding material to mold the electronic component to the substrate since Shin's objective is to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) disposed on (disposed on) the substrate (110) to mold (mold, [0050], well known in the art) the electronic component (20), wherein
the protruded structure (202) includes a first protruded structure (202R: 202 on right side) supporting (shown supporting) the first electrode (21R) and a second protruded structure (202L: 202 on left side) supporting (shown supporting) the second electrode (21L).
Regarding claim 2, Shin teaches the package of claim 1 and goes on to teach wherein: each of the first connection pad (1211R, Fig 10) and the second connection pad (1211L) is embedded (shown embedded) in the insulating layer (111) and exposed (shown exposed) to an upper surface (111T: top surface of 111) facing (shown facing) the electronic component (20) of the insulating layer (111).
Regarding claim 3, Shin teaches the package of claim 1 and goes on to teach wherein: the electronic component package (10C, Fig 10) further includes a first connection structure (12R: 12 on right side) and a second connection structure (12L: 12 on left side) spaced apart (shown spaced apart) from each other,
the first connection structure (12R) is interposed between (shown between) the first electrode (21R) and the first connection pad (1211R) to electrically connect (shown electrically connected) the first electrode (21R) to the first connection pad (1211R), and
the second connection structure (12L) is interposed between (shown between) the second electrode (21L) and the second connection pad (1211L) to electrically connect (shown electrically connected) the second electrode (21L) and the second connection pad (1211L),
some regions (21R_A: portion of 21R directly over 202R) of the first electrode (21R) are disposed on (shown on) the first protruded structure (202R), and
other regions (21R_B: portion of 21R directly over 12R) of the first electrode (21R) are disposed on (shown on) the first connection structure (12R), and
some regions (21L_A: portion of 21L directly over 202L) of the second electrode (21L) are disposed on (shown on) the second protruded structure (202L), and
other regions (21L_B: portion of 21L directly over 12L) of the second electrode (21L) are disposed on (shown on) the second connection structure (12L).
Regarding claim 4, Shin teaches the package of claim 3 and goes on to teach wherein: the electronic component (20, Fig 10) further includes a body (22) interposed between (shown between) the first electrode (21R) and the second electrode (21L), and
the molding material (M) fills a space (212) between (shown between) the first connection structure (202R) and the second connection structure (202L).
Regarding claim 5, Shin teaches the package of claim 3 and goes on to teach wherein: the first connection structure (12R, Fig 10) extends onto (shown extending onto, Fig 9) a top surface (202R_T: top surface of 202R, shown as 202a in Fig 9) of the first protruded structure (202R) so that a portion (12R_A: portion of 12R that is directly above 202a) of the first connection structure (12R) is interposed between (shown between) the first electrode (21R) and the first protruded structure (202R), and
the second connection structure (12L) extends onto (shown extending onto) a top surface (202L_T: top surface of 202L, shown as 200a in Fig 9) of the second protruded structure (202L) so that a portion (12L_A: portion of 12L that is directly above 202a) of the second connection structure (12L) is interposed between (shown between) the second electrode (21L) and the second protruded structure (202L).
Regarding claim 6, Shin teaches the package of claim 1 and goes on to teach wherein: the opening (1211O, Fig 10) of the protection layer (200) further exposes a region (212A: region of 111 between 1211R and 1211L) between (shown between) the first connection pad (1211R) and the second connection pad (1211L) of the insulating layer (111).
Regarding claim 7, Shin teaches the package of claim 6 and goes on to teach wherein: the molding material (M, not shown) fills (inherent in the design since Shin's objective is to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) at least a part of a space (212) between (shown between) the electronic component (20) and the region (212A) exposed by the opening (1211O) of the insulating layer (111).
Regarding claim 8, Shin teaches the package of claim 1 and goes on to teach wherein: the protruded structure (202, Fig 10) includes equal material (200 includes 201 and 202, [0120]) as the protection layer (200).
Regarding claim 9, Shin teaches the package of claim 1 and goes on to teach wherein: the protection layer (200, Fig 10) and the protruded structure (202) include an insulating material (solder resist, [0120]).
Regarding claim 10, Shin teaches the package of claim 1 and goes on to teach wherein the electronic component (20, Fig 10) is a multi-layer ceramic capacitor (MLCC) (chip-type capacitor, [0077]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 20250126717 A1) as applied to claims 1-10 above, and further in view of Kang (US 20220053631 A1).
Regarding claim 11, Shin teaches the package of claim 10 the protruded structure (202), the electronic component (20), and goes on to teach further comprising: a semiconductor chip (11, Fig 10) disposed on (shown on) the substrate (110) and electrically connected (shown electrically connected) to the wiring layer (121);
the molding material (M) molds (mold, [0050], well known in the art) the semiconductor chip (20) along with the electronic component (20).
Shin fails to explicitly teach the protruded structure includes a third protruded structure, wherein the third protruded structure is interposed between the semiconductor chip and the electronic component.
However, Kang teaches the protruded structure includes a third protruded structure (130, Fig 3), wherein
the third protruded structure (130) is interposed between (shown between) the semiconductor chip and the electronic component.
Shin and Kang are considered analogous to the claimed invention because both are from the same field of endeavor of electronic component packages. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Shin with the features of Kang to create an electronic component package wherein the protruded structure includes a third protruded structure, wherein the third protruded structure is interposed between the semiconductor chip and the electronic component to provide a component package which may have a reduced size (Kang, [0004]).
Claims 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 20250126717 A1), and further in view of the obviousness of known technique.
Regarding claim 12, Shin teaches an electronic component package (10C, Fig 10) comprising: a substrate (110) including an insulating layer (111),
a wiring layer (121) including a connection pad (1211),
a protection layer (200) disposed on (shown on) the insulating layer (111), and
at least one protruded structure (202) disposed on (shown on) the protection layer (200), wherein
an opening (212) is defined in (shown in) the protection layer (200) and the protruded structure (202) is adjacent (shown adjacent) to the opening (212);
an electronic component (20) disposed on (shown on) the substrate (110) and electrically connected (shown electrically connected) to the connection pad (1211); and
a molding material (M: not shown; well known to be used during the molding process; It is obvious Shin would use molding material to mold the electronic component to the substrate since it is possible to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) disposed on (disposed on) the substrate (110) to mold (mold, [0050], well known in the art) the electronic component (20) and … a resin (resin, [0087]) and a filler (silica, [0087]), wherein
the opening (212) exposes (shown exposed) at least part of the connection pad (1211) and the insulating layer (111) adjacent (shown adjacent) to the connection pad (1211), wherein
the electronic component (20) includes a region (21) on (shown on) the protruded structure (202) and a region (22) on (shown on) the opening (212), and wherein
a gap (gap: space from top surface of 111 to bottom surface of 22) between (shown between) the region (22) on the opening (212) of the electronic component (20) and the substrate (110) is larger (shown larger) than an average particle diameter (the average particle diameter of silica is well known to be smaller than the components of Shin's invention and since the size of the gap is shown to be comparable to the size of the components, the diameter of the filler would be much smaller so it is possible to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) of the filler (filler).
Shin fails to explicitly teach a molding material … including a resin and a filler.
However, Shin teaches a base product of a molding material made out of an insulator which the claimed invention can be seen as an improvement in that to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).
Shin goes on to teach a known technique of resins including inorganic fillers such as silica and reinforcing materials such as glass fiber may be used for insulating materials, [0087], that is comparable to the base product.
Shin’s known technique, as cited above for insulating layers, would have been recognized by one skilled in the art as applicable to the base product of the molding material and the results would have been predictable and resulted to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]) which results in an improved product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding claim 13, Shin teaches the package of claim 12 and goes on to teach wherein: the connection pad (1211, Fig 10) is embedded (shown embedded) in the insulating layer (111) and exposed (shown exposed) to an upper surface (111T: top surface of 111) facing (shown facing) the electronic component (20) of the insulating layer (111).
Regarding claim 14, Shin teaches the package of claim 12 and the gap (gap, Fig 10) between the region (22) on the opening (212) of the electronic component (20) and the substrate (110).
Shin fails to explicitly teach the gap between the region on the opening of the electronic component and the substrate is 46 µm or more.
However, in cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. Paragraph [0067] of the instant application's specification states, "For example, the thickness t1 of the first protection layer 141 may be around 6µm to 14µm, and the thickness t2 of the protruded structure 150 may be around 40µm or more. In one embodiment, a sufficient gap between the electronic component 200 and the substrate 100 may be secured by adjusting the thickness of the protruded structure 150 disposed on the first protection layer 141."
While claim 4 limits the gap between the region on the opening of the electronic component and the substrate to 46 µm or more, the cited paragraph above is silent to the criticality of the size of the gap, and instead indicates on of ordinary skill in the art would find it obvious to adjust the size of the gap to ensure it is possible to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).
As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553, 555, 188 USPQ 7, 9 (CCPA 1975).
Regarding claim 15, Shin teaches the package of claim 12 and goes on to teach wherein: the filler (filler, [0087], Fig 10) includes silica (SiO₂) (silica, [0087]).
Regarding claim 16, Shin teaches the package of claim 12 and goes on to teach wherein: a thickness (202aT: total thickness of 202a in vertical direction, Fig 10) of the protruded structure (202) is thicker (shown thicker) than a thickness (200bT: total thickness of 202b in vertical direction) of the protection layer (202) along a thickness direction (Z: vertical direction in Fig 10).
Regarding claim 17, Shin teaches the package of claim 12 and goes on to teach wherein: the molding material (M, not shown, Fig 10) fills (fills, inherent in the design since Shin’s objective is to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) at least a part of a space (gap: space from top surface of 111 to bottom surface of 22) between (shown between) the substrate (110) and the region (22) on the opening (212) of the electronic component (20).
Regarding claim 18, Shin teaches the package of claim 12 and goes on to teach wherein: the region (21, Fig 10) on the protruded structure (202) of the electronic component (20) is one of electrodes (electrode portion, [0078]) of the electronic component (20).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 20250126717 A1), in view of Akiyama (US 20250046712 A1), and further in view of Kang (US 20220053631 A1).
Regarding claim 19, Shin teaches an electronic component package (10C, Fig 10) comprising: a substrate (110) including an insulating layer (111),
a wiring layer (121) including a first connection pad (1211) and a second connection pad (1212: pads of layer 121 directly connected to 13 of chip 11),
a protection layer (200) disposed on (shown on) the insulating layer (111), and
at least one protruded structure (202) disposed on (shown on) the protection layer (200), wherein
an opening (211/211A: opening in 200 for component 20 and chip 11 to connect to pads of wiring layer 121) exposing (shown exposing) at least a portion of each of the first connection pad (1211) and the second connection pad (1212) is defined in (shown in) the protection layer (200);
an electronic component (20) disposed on (shown on) the substrate (110) and electrically connected (shown electrically connected) to the first connection pad (1211);
a semiconductor chip (11) disposed on (shown on) the substrate (110), wherein
the semiconductor (11) is spaced apart (shown spaced apart) from the electronic component (20) and electrically connected (shown electrically connected) to the second connection pad (1212);
a plurality of conductive bumps (13) electrically connecting (shown electrically connected) the semiconductor chip (11) to the second connection pad (1212);
a molding material (M: not shown; well known to be used during the molding process; It is obvious Shin would use molding material to mold the electronic component to the substrate since it is possible to prevent mold void defects under the surface-mounted component during the molding process, and to suppress physical and electrical interference effects between the surface mounted component and the circuit board (Shin, [0195]).) disposed on (disposed on) the substrate (110) to mold (mold, [0050], well known in the art) the electronic component (20) and the semiconductor chip (11), wherein
the protruded structures (202) include a first protruded structure (202R: 202 on right side), a second protruded structure (202L: 202 on left side),
the first protruded structure (202R) and the second protruded structure (202L) support (shown supporting) the electronic component (20).
Shin fails to explicitly teach an underfill resin interposed between the semiconductor chip and the substrate and covering the conductive bumps; the protruded structures include a third protruded structure, and the third protruded structure blocks at least one side of the semiconductor chip on a plane.
However, Akiyama teaches an underfill resin (81, Fig 1) interposed between (shown between) the semiconductor chip and the substrate and covering (shown covering) the conductive bumps.
Kang teaches the protruded structure includes a third protruded structure (130, Fig 3), and
the third protruded structure (130) blocks (shown blocking) at least one side of the semiconductor chip on a plane (XY: horizontal and vertical plane shown in Fig 4).
Shin, Akiyama, and Kang are considered analogous to the claimed invention because all are from the same field of endeavor of electronic component packages. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Shin with the features of Akiyama and Kang to create an electronic component package wherein an underfill resin interposed between the semiconductor chip and the substrate and covering the conductive bumps; the protruded structures include a third protruded structure, and the third protruded structure blocks at least one side of the semiconductor chip on a plane because in this type of semiconductor device, an underfill material is added to a gap between a wiring substrate and an electronic component to protect the portion where the wiring substrate is connected to the electronic component from external stress and the like so that the connection reliability is improved (Akiyama, [0003]) and to provide a component package which may have a reduced size (Kang, [0004]).
Regarding claim 20, the combination of Shin, Akiyama, and Kang discloses the package of claim 19. Shin goes on to teach wherein: the first protruded structure (202R, Fig 10) and the second protruded structure (202L) include a same material (solder resist, [0120]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoon (US 20120074566 A1) - package with guide rings
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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