DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 06/05/2024.
Information disclosed and list on PTO 1449 was considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee Nam Jae (DE102021201252A1)
Regarding claim 1, Lee nam Jae discloses a memory device (Figure 2) comprising:
memory cells (Figure 2, MC) coupled in series between one or more first selection transistors (Figure 2, DST) coupled in series to a source line (Figure 2, SL) and one or more second selection transistors (Figure 2, SST) coupled in series to a bit line (Figure 2, BL); and
a control unit (Figure 1, 35) configured to apply, during a forcing period (Figure 3) that is part of a rising period (Figure 3) during which an increasing erase voltage (Figure 3, Vers) is applied to the bit line (Figure 3, BL1-BLA), an increasing selection voltage (Figure 3, Vs=Vers-V1) to local selection lines coupled to the one or more first selection transistors and the one or more second selection transistors (Figure 3, DSL1,DSL2,DSL3,SSL).
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113
872
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Greyscale
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107
876
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Greyscale
Regarding claim 2, Lee nam Jae discloses wherein the control unit is configured to increase the selection voltage in a stepwise manner (Figure 3, T1-T4) during the forcing period.
Regarding claim 3, Lee nam Jae discloses wherein the control unit is configured to increase the selection voltage (Figure 3, DS1-DS3, SSL) by at least one step during the forcing period (Figure 3, Vs).
Regarding claim 4, Lee nam Jae discloses wherein the forcing period begins after the rising period begins and ends before the rising period ends (Figure 3, Va, V1,V2,V3).
Regarding claim 5, Lee nam Jae discloses wherein the control unit is configured to apply a ground voltage (Figure 3, SSL, 0V) to the local selection lines during the rising period until the forcing period begins.
Regarding claim 6, Lee nam Jae discloses wherein the control unit is configured to float the local selection lines from an end of the forcing period until an end of an erase period during which a voltage at the bit line is maintained at a target erase voltage.
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67
899
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Greyscale
Regarding claim 16, Lee nam Jae discloses a memory device (Figure 2) comprising:
memory cells (Figure 2, MC) coupled in series between one or more first selection transistors (Figure 2, DST) coupled in series to a source line (Figure 2, SL) and one or more second selection transistors (Figure 2, SST) coupled in series to a bit line (Figure 2, BL); and
a control unit (Figure 1, 35) configured to increase voltages (Figure 3, Vpre) of the local selection lines to a target selection voltage (Figure 3, Vers) during a rising period (Figure 3, (1),(2),(3) during which rising period an increasing erase voltage is applied to the bitline (Figure 3, BL1-BL4), and configured to floating the local selection lines (Figure 3, DSL1,DSL2,DSL3,SSL) before an end of the rising period (Figure 3).
Regarding claim 17, Lee nam Jae discloses wherein the control unit is configured to float the local selection lines (Figure 3, DSL, SSL) until an end of an erasing period (Figure 3, Ve), during which erasing period a voltage at the bit line (Figure 3, Vers) is maintained at a target erase voltage (Figure 3, Vers) after the rising period.
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46
936
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee nam Jae as applied to claims 7-10 above, and further in view of Yang (9,490,021).
Lee nam Jae discloses the claimed invention except for the connection unit. Yang discloses a connection unit (figure 5, 320) to connect between global and local selection lines to transfer voltages from global to local memory device. It would have been obvious to one having ordinary skill in the art at the time the invention was made to connect between global and local area in a memory device by a connection unit as taught by Yang, can see explain in claims 11-20 by Yang.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang (U.S. 9,490,021).
Regarding claims 11,16, Yang discloses a memory device (Figure 1) comprising:
memory cells (Figure 2B) coupled in series between one or more first selection transistors (Figure 2B, C) coupled in series to a source line (Figure 2B, SL) and one or more second selection transistors coupled in series to a bit line (Figure 2B, BL); and
a control unit (Figure 5, 30) including a connection unit (Figure 5, 320) coupled between global selection lines (Figure 5, GSSL, GDSL) and local selection lines coupled to the one or more first selection transistors (Figure 5, DSL) and the one or more second selection transistors (Figure 5, SSL), configured to enable the connection unit during at least part of a rising period until a forcing period ends (Column 8, lines 15-32), during which rising period an increasing erase voltage is applied to the bit line (Figure 6, BL, Column 8, lines 33-35) and configured to disable the connection unit at an end of the forcing period (Figure 6, Column 8, lines 64067, Column 9, lines 1-25).
Regarding claims 12, Yang discloses wherein the control unit is configured to increase voltages at the global selection lines during the forcing period (Figure 6, DSL, SSL).
Regarding claims 13, Yang discloses wherein the control unit is configured to maintain the global selection lines at a ground voltage during the rising period until the forcing period begins (Figure 6, DSL, SSL, T0-T1).
Regarding claims 14, Yang discloses wherein the control unit is configured to float the local selection lines from the end of the forcing period until an end of an erasing period (Figure 6, DSL).
Regarding claim 15, Yang discloses wherein the control unit is configured to maintain voltages of the global selection lines at voltages at the end of the forcing period from the end of the forcing period until an end of an erasing period (Column 7, lines 55-67, Column 8, lines 1-2).
Regarding claim 17, Yang discloses wherein the control unit is configured to float the local selection lines (Figure 6, DSL) until an end of an erasing period, during which erasing period a voltage at the bit line (Figure 6, BL) is maintained at a target erase voltage (Figure 6, Verase) after the rising period.
Regarding claim 18, Yang discloses wherein the control unit comprises: a connection unit (Figure 5, 320, NT) coupled between the local selection lines and global selection lines and configured to transfer voltages applied to the global selection lines to corresponding local selection lines (Column 7, lines 40-67, Column 8, lines 1-2); and
a voltage supply unit (Figure 1, 30) coupled to the global selection lines (Figure 5, 310), GSSL, GDSL), wherein the voltage supply unit is configured to increase the voltages at the global selection lines to the target selection voltage during the rising period (Column 7, lines 54-67, Column 8, lines 1-2).
Regarding claim 19, Yang discloses wherein the control unit is configured to float the local selection lines (Figure 6, DSL) by disabling the connection unit.
Regarding claim 20, Yang discloses wherein the voltage supply unit is configured to maintain the global selection lines at the target selection voltage from a time when the local selection lines are floated until an erasing period ends (Column 1, lines 19-29, Column 9, lines 7-12).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THONG QUOC LE whose telephone number is (571)272-1783. The examiner can normally be reached 7:30AM-5:30PM.
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/THONG Q LE/ Primary Examiner, Art Unit 2827