Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in EP on 04/04/2024. It is noted, however, that applicant has not filed a certified copy of the EP24382347.3 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Subject Matter Eligibility Analysis Step 1:
Claims 1-8 recite a machine (“A system, comprising”), one of the four statutory categories of patentable subject matter. Claims 9-16 recite a process (“A computer-implemented method, comprising”), one of the four statutory categories of patentable subject matter. Claims 17-20 recite an article of manufacture (“A computer program product …”), one of the four statutory categories of patentable subject matter.
Regarding Claim 1:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Claim 1 therefore recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
“a memory that stores computer-executable components” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“a processor that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“a recommendation component that employs a machine learning model to ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
The additional elements as disclosed above alone or in combination do not integrate the judicial exception into practical application as they are merely generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above. Therefore, Claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
“a memory that stores computer-executable components” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“a processor that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“a recommendation component that employs a machine learning model to ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
The additional elements as disclosed above alone or in combination do not recite significantly more than the abstract idea itself as they are merely generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above. Therefore, Claim 1 is subject-matter ineligible.
Regarding Claim 9:
The claim recites a process that performs the method of the system as described in claim 1. Therefore, claim 9 is rejected for the same reasons as disclosed for claim 1. The limitations for additional elements of claim 9 are analyzed below.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Please see Step 2A Prong 1 analysis of claim 1
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“generating, by a system operatively coupled to a processor, via a machine learning model …” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claim 17:
The claim recites an article of manufacture that performs the method of the system as described in claim 1. Therefore, claim 17 is rejected for the same reasons as disclosed for claim 1. The limitations for additional elements of claim 17 are analyzed below.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Please see Step 2A Prong 1 analysis of claim 1
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“A computer program product for solving problems related to quantum computing, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by at least one processor to cause the at least one processor to” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 2 and 10:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“a training component that trains the machine learning model ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“performing a first stage of training by employing a training set comprising defined problems previously executed on quantum hardware and respective combinations of entities comprising quantum circuits, algorithms, quantum hardware units, error mitigation or error correction techniques, and quantum procedures, employed to execute the defined problems on the quantum hardware, to train the machine learning model, and employing a different machine learning model to ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
“performing a second stage of training by employing the training set supplemented with the new combinations of entities and solutions generated by execution of the defined problems with the new combinations of entities as feedback information to retrain the machine learning model” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 3, 11, and 18:
Subject Matter Eligibility Analysis Step 2A Prong 1: None
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“wherein the input further comprises one or more datasets corresponding to the defined problem, and wherein the combination of entities further comprises parameters for solving the defined problem” (merely specifies a particular technological environment in which the abstract idea is to take place, ie. a field of use, and thus does not integrate the abstract idea into a practical application nor cannot provide significantly more than the abstract idea itself - see MPEP 2106.05(h))
Regarding Claims 4, 12, and 19:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“wherein the recommendation component ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 5, 13, and 20:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“an optimization component that ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 6 and 14:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“wherein the recommendation component ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 7 and 15:
Subject Matter Eligibility Analysis Step 2A Prong 1: None
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“wherein the combination of entities and the at least a second combination of entities are executed in parallel on a quantum computing platform to generate respective results for the defined problem based on the combination of entities and the at least a second combination of entities” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Regarding Claims 8 and 16:
Subject Matter Eligibility Analysis Step 2A Prong 1:
“” (a mental process that can be performed in the human mind with the aid of pen and paper, i.e. judgement)
Subject Matter Eligibility Analysis Step 2A Prong 2 & 2B:
“an analysis component that ” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US20240330738A1) in view of Beisel “Configurable Readout Error Mitigation in Quantum Workflows”.
Regarding claim 1, Shi teaches:
“A system, comprising: a memory that stores computer-executable components; and a processor that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise” (abstract, [0205], A computing device consists of one or more processor and a memory to perform customized compilation job plan for each quantum circuit.)
“a recommendation component that employs a machine learning model to generate, based on an input, a recommendation comprising a combination of entities comprising, one or more quantum circuits, one or more algorithms, one or more quantum hardware units, ” ([0030-0031, 0035-0036, 0058, 0068-0069, 0071, 0078, Figure 1], The system provides quantum circuit compilation service that consist of optimization of mapping of logical quantum circuits to quantum hardware devices. In one embodiment, the compilation service may utilize a reinforcement-learning-based trained model. A quantum algorithm development kit includes an interface to allow customers to input quantum tasks, algorithms, or circuits. The compilation results include an efficient mapping of a quantum circuit on the components of a quantum processing unit. The mapping optimization may involve the use of an SAT solver, SMT solver, or reinforcement-learning model. In some embodiment, the quantum circuit compilation service outputs a software container comprising the quantum circuit job plan and modular compilation pass instructions. The results from executing the customer’s quantum task are available to the customer.)
Shi does not explicitly disclose an implementation of “one or more error mitigation or error correction techniques”. However, Beisel discloses in the same field of endeavor:
“…, a recommendation comprising a combination of entities comprising, … , one or more error mitigation or error correction techniques, …” ([pg. 13, Section 4, par. 1; pg. 13-15, Section 4.1, par. 4; pg. 19, Figure 9], The proposed framework describes automating readout error mitigation in quantum workflow. In some embodiment, the system checks for a suitable mitigator based on the quantum device and the set of measured qubits. If a suitable mitigator is found, it is used to mitigate errors. Otherwise, calibration data is retrieved to compute a mitigator. Figure 9 describes a workflow for selecting a particular mitigation method.)
It would be obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of “one or more error mitigation or error correction techniques” from Beisel into the teaching of Shi. Doing so can optimize the execution of complex quantum computing tasks by incorporating a readout error mitigation configuration into a quantum workflow. (Beisel, abstract).
Regarding claim 9:
Claim 9 recites a process that performs the method of the system as described in Claim 1. Therefore claim 9 is rejected under the same reasons mentioned for claim 1.
Regarding Claim 17:
The claim recites an article of manufacture that performs the method of the system as described in claim 1. Therefore, claim 17 is rejected for the same reasons as disclosed for claim 1. The limitations for additional elements of claim 17 are analyzed below:
“A computer program product for solving problems related to quantum computing, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by at least one processor to cause the at least one processor to” ([0205, 0210], A computing device consists of one or more processor and a memory to perform customized compilation job plan for each quantum circuit. The computer-accessible medium is configured to store at least a subset of program instructions and data.)
Regarding claims 2 and 10, Shi in view of Beisel teaches:
“a training component that trains the machine learning model to generate the recommendation without executing the input on a quantum computing platform, wherein training the machine learning model comprises” ([Shi, 0152-0155, Figure 14], The RL-based quantum circuit router consists of components for using a reinforcement learning-based machine learning model to generate mappings of logical quantum circuits to quantum hardware devices. Monte Carlo Tree Search algorithm is employed to identify predicted outcomes of various actions and determine a loss associated with selecting those various actions. The quantum circuit mapping problem is solved without executing the input into a quantum computing system.)
“performing a first stage of training by employing a training set comprising defined problems previously executed on quantum hardware and respective combinations of entities comprising quantum circuits, algorithms, quantum hardware units, ” ([Shi, 0156-0158, 0161-0162], The logical quantum circuit cache may store logical quantum circuits submitted by customers and logical quantum circuits used to train the model of the RL-based quantum circuit router. Experience replay buffer may store quantum circuit mapping determination scenarios that have already been completed by RL-based quantum circuit router such that experience replay buffer grows over time. The policy network and value network work together to determine the actions and rewards to guide the reinforcement learning model in quantum circuit mapping. Beisel (pg. 13-15, Section 4.1, par. 4) discloses a workflow to implement a mitigator for a quantum device.)
“performing a second stage of training by employing the training set supplemented with the new combinations of entities and solutions generated by execution of the defined problems with the new combinations of entities as feedback information to retrain the machine learning model” ([Shi, 0158, 0164-0165], The trained reinforcement learning model may be applied to a given quantum circuit mapping problem of a customer of service provider network. The quantum compilation service can leverage multiple RL-based quantum circuit routing instances to run the quantum circuit mapping problem for a certain set of qubit technologies.)
Regarding claims 3, 11, and 18, Shi teaches:
“wherein the input further comprises one or more datasets corresponding to the defined problem, and wherein the combination of entities further comprises parameters for solving the defined problem” ([0058, 0082, 0103-0104], Customers may define quantum objects, such as quantum tasks. Recommendations may be based on known data about the quantum objects previously submitted by the customer. The quantum circuit compilation service may include an optimization module for pass parameter tuning.)
Regarding claims 4, 12, and 19, Shi teaches:
“wherein the recommendation component recommends the combination of entities based on one or more constraints selected from a group comprising at least one of the one or more quantum circuits, the one or more algorithms, the one or more quantum hardware units, the one or more error mitigation or error correction techniques, the one or more quantum procedures, hybrid procedures and parameters” ([0068, 0097, 0127], Quantum circuit mapping may be constraint by gate scheduling conditions, qubit mapping conditions, SWAP operand selection conditions. Additionally, customers can apply constraints such as convergence criteria, a confidence threshold, a budgeted cost for performing compilation, and the number of iterations.)
Regarding claims 5, 13, and 20, Shi teaches:
“an optimization component that applies various optimizations at an algorithm level, based on knowledge of techniques previously employed to solve the defined problem, to customize an algorithm of the one or more algorithms” ([0068-0071, 0082, 0162, Figure 1], The optimization problem service can be configured to implement SAT solving instances, in addition to instances of other optimization problem solving techniques. The compilation service may use a RL-based trained model as the mapping paradigm. The RL-based model store various quantum circuit mapping problems that have been previously solved and can be used in similar scenario.)
Regarding claims 6 and 14, Shi teaches:
“wherein the recommendation component recommends at least a second combination of entities to solve the defined problem, wherein the at least a second combination of entities comprises additional or fewer entities than the combination of entities” ([0031, 0036, Figure 3], Optimization compilation passes may be performed throughout the compilation process. Optimization compilation passes may reduce gate count, reduce swap gates, and re-arrange qubit allocation to reduce circuit depth. Each optimization compilation pass reduces complexity and error during execution of the compiled quantum circuit by reducing circuit depth.)
Claims 7-8, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US20240330738A1) in view of Beisel “Configurable Readout Error Mitigation in Quantum Workflows” and Zhu (US20240428106A1).
Regarding claims 7 and 15, Shi in view of Beisel teaches:
“wherein ” ([0083, 0108, Figure 1], The quantum computing service may execute the compiled artifact at a local QPU. Shi discloses executing the compiled circuit on a quantum hardware provider and does not explicitly disclose executing multiple circuits in parallel.)
Shi in view of Beisel does not explicitly disclose an implementation of “wherein the combination of entities and the at least a second combination of entities are executed in parallel on a quantum computing platform …”. However, Zhu discloses in the same field of endeavor:
“wherein the combination of entities and the at least a second combination of entities are executed in parallel on a quantum computing platform to generate respective results for the defined problem based on the combination of entities and the at least a second combination of entities” ([0047-0049, 0052, Figure 5B], The architecture search method for designing quantum circuits includes a search step and a performance estimation step. Candidate quantum circuits are searched based on different combinations of gate configurations and are ranked based on the performance of the circuits. The quantum architecture search algorithm aims to find the best quantum circuit for a specific task.)
It would be obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of “wherein the combination of entities and the at least a second combination of entities are executed in parallel on a quantum computing platform” from Zhu into the teaching of Shi in view of Beisel. Doing so can improve the performance of a quantum circuit to execute specific tasks by implementing an adaptive diversity-based quantum circuit architecture search to find the optimal quantum circuit (Zhu, abstract, par. 55).
Regarding claims 8 and 16, Shi in view of Beisel and Zhu teaches:
“an analysis component that analyzes the respective results against evaluation metrics for the defined problem to identify an optimal combination of entities for solving the defined problem” ([Zhu, 0048, 0052], The optimizer determines how each of the candidates performs according to a given metric. The metric may be gate minimization or energy minimization.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY MAC whose telephone number is (703)756-1517. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abdullah Kawsar can be reached at (571) 270-3169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY MAC/Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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