Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 5, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LUO (US 20180307614 A1), hereinafter “Luo”, in view of KI (US 20220113915 A1), hereinafter “Ki”.
With regards to claim 1, Luo teaches An apparatus comprising:
a memory; and ((¶0010) The memory cells in the memory unit are seen as the claimed memory.)
a tensor access circuit having a memory mapper to configure a memory map based on a memory command associated with an access operation of the memory, ((¶0022 and ¶0024, Fig. 1) Both the memory mapper (120) and the address translator (130) can be circuits and are located inside the memory controller (110). (¶0019-¶0020) The memory mapper (120) provides memory maps in relation to tensor memory commands. (Applicants spec ¶0024) The tensor access circuit in the applicant’s specification is made up of a memory mapper and an address translator. Therefore, the memory mapper (120) and the address translator (130) together are interpreted to be the claimed tensor access circuit. (¶0017, FIG. 1) The memory mapper (120) is interpreted to be the claimed memory mapper used to configure a memory map based on a memory command associated with an access operation of the memory.)
wherein the memory map comprises a specific sequence of memory access instructions to access to the memory via a bus. ((¶0017 and ¶0036, FIG. 1 and FIG. 5) The memory map includes one or more specific sequences of memory access instructions to access memory units (140a and 140b) via a bus.)
Luo teaches a memory command, memory access instructions, and a bus, but does not teach:
a CXL command, CXL instruction, and a CXL bus;
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation.
However, Ki does teach:
a CXL command, CXL instruction, and a CXL bus; (paragraphs 0041, 0045, and 0068; Fig. 2);
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation (paragraphs 0077 and 0090. It should be noted that the “vector transfer” is a type of “tensor operation”.)
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 2, Luo teaches wherein the specific sequence of memory access instructions is specific to a type of the memory command. ((¶0018) The memory commands including row memory commands or column memory commands is interpreted to be the type of memory command. (¶0017-¶0018) The memory map, including the one or more sequences of memory access instructions, can be selected to be specific to a type of memory command. This is interpreted to be the claimed specific sequence of instructions is specific to a type of the command. This is interpreted to be the claimed specific sequence of instructions that is specific to a type of the command.)
Luo teaches the memory access instructions and the memory command, but does not teach:
CXL instructions and the CXL command.
However, Ki does teach:
CXL instructions and the CXL command. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 3, Luo teaches wherein the type of memory command comprises a diagonal memory command, a determinant memory command, or any matrix memory command. ((¶0018-¶0019) The memory commands based on tensor operations include types of memory commands including a diagonal memory command, a determinant memory command, or any matrix memory command.)
Luo teaches the memory command, but does not teach:
The CXL command.
However, Ki does teach:
The CXL command. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 4, Luo teaches wherein each memory access instruction of the specific sequence of memory access instructions comprises an instruction for a respective address of a memory cell of the memory. ((¶0017) Each memory access instruction may include an instruction for a respective address of a memory cell of the plurality of memory cells. The memory cell of the plurality of memory cells is interpreted as the claimed memory cell of the memory.)
Luo teaches the memory access instructions, but does not teach:
The CXL instructions.
However, Ki does teach:
The CXL instructions. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 5, Luo teaches further comprising a memory controller including the tensor access circuit. ((¶0011, FIG. 1) The memory controller (110) is interpreted to be the claimed memory controller (110). The memory controller (110) includes a memory mapper (120) and an address translator (130), which together are interpreted to be the tensor access circuit.)
With regards to claim 6, Luo teaches further comprising a processor including the memory controller, wherein the processor is coupled to the memory via the bus. ((¶0011, FIG. 1) The processor (105) that implements the memory controller (110) is interpreted to be the claimed processor including the memory controller. Figure 1 shows the memory controller (110) inside of the processor (105). (¶0036, FIG. 5) Figure 5 shows the processor (505) being coupled to the memory via the bus (580).)
Luo teaches the bus, but does not teach:
The CXL bus.
However, Ki does teach:
The CXL bus. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 7, Luo teaches further comprising a memory unit including the memory. ((¶0010) The memory unit containing memory cells are interpreted to represent the memory unit including the memory.)
Luo teaches a memory unit including the memory, but does not teach:
a CXL device including the memory.
However, Ki does teach:
a CXL device including the memory. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 8, Luo teaches further comprising a memory system including the memory mapper. ((¶0034, FIG. 5) The memory system (502) includes the memory controller (510) that includes a memory mapper (520) and an address translator (530). (FIG. 5 and FIG. 1) The numbered elements of Figure 5 include analogous functionality to those numbered elements of Figure 1 including the memory controller (110) and all its components (memory mapper 120 and address translator 130).)
Luo teaches a memory system, but does not teach:
A CXL device.
However, Ki does teach:
A CXL device. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 10, Luo teaches further comprising a memory interface coupled to the tensor access circuit and configured to communicate with the memory. ((¶0011, Fig. 1) Luo’s memory controller (110), interpreted to have the tensor access circuit, has a memory interface (135a and 135b) that is interpreted to be the memory interface coupled to the tensor access circuit. (¶0012) The memory controller (110) provides access commands to the memory via the memory interfaces (135a and 135b). This is interpreted to be the memory interface configured to communicate with the memory.)
Luo teaches the memory interface, but does not teach:
A CXL interface.
However, Ki does teach:
A CXL interface. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 11, Luo teaches wherein the memory mapper is configured to provide the memory map to the memory via the memory interface. ((¶0017) The memory mapper (120) provides a memory map to the memory unit (140a and 140b) via an address terminal of the memory interface (135a and 135b).)
Luo teaches a memory interface, but does not teach:
A CXL interface.
However, Ki does teach:
A CXL interface. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 12, Luo teaches an apparatus comprising:
a memory unit having a memory; ((¶0010) The memory cells in the memory unit are seen as the claimed memory.)
a processor coupled to the memory unit via a bus and comprising having a tensor access circuit, ((¶0011, FIG. 1) The processor (105) that is coupled to memory units (140a and 140b) interpreted to be the claimed processor. Figure 1 shows the memory units (140a and 140b) coupled to the processor (105). (¶0036, FIG. 5) Figure 5 shows the processor (505) being coupled to the memory (540) via the bus (580). (¶0022 and ¶0024, Fig. 1) Both the memory mapper (120) and the address translator (130) can be circuits and are located inside the memory controller (110). (¶0019-¶0020) The memory mapper (120) provides memory maps in relation to tensor memory commands. (Applicants spec ¶0024) The tensor access circuit in the applicant’s specification is made up of a memory mapper and an address translator. Therefore, the memory mapper (120) and the address translator (130) together are interpreted to be the claimed tensor access circuit. This interpretation is consistent with the 112b rejection given above.)
wherein the tensor access circuit is configured to configure a memory map based on a memory command associated with an access operation of the memory, ((¶0017) Luo teaches that the memory mapper (120), interpreted to be part of the claimed tensor access circuit, configures the claimed memory map based on a memory command associated with the claimed access operation of the memory.)
wherein the memory map comprises a specific sequence of memory access instructions to access to the memory via the bus. ((¶0017) Luo teaches that the claimed memory map comprises a specific sequence of memory access instructions to access the memory via the memory interface (135).)
Luo teaches a memory unit, a bus, a memory command, and memory access instructions, but does not teach:
a compute express link (CXL) device having a memory, a CXL bus, CXL command, and CXL instructions;
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation.
However, Ki does teach:
a compute express link (CXL) device having a memory, a CXL bus, CXL command, and CXL instructions; (paragraphs 0041, 0045, and 0068; Fig. 2);
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation (paragraphs 0077 and 0090. It should be noted that the “vector transfer” is a type of “tensor operation”.)
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 13, Luo teaches wherein a type of memory command comprises a diagonal memory command, a determinant memory command, or any matrix memory command. ((¶0018-¶0019) The memory commands based on tensor operations include types of memory commands including a diagonal memory command, a determinant memory command, or any matrix memory command.)
Luo teaches a memory command, but does not teach:
A CXL command.
However, Ki does teach:
A CXL command. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 14, Luo teaches wherein each memory access instruction of the specific sequence of memory access instructions comprises an instruction for a respective address of a memory cell of the memory. ((¶0017) Each memory access instruction may include an instruction for a respective address of a memory cell of the plurality of memory cells. The memory cell of the plurality of memory cells is interpreted as the claimed memory cell of the memory.)
Luo teaches memory access instructions, but does not teach:
CXL instructions.
However, Ki does teach:
CXL instructions. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 16, Luo teaches A method comprising:
obtaining an access command associated with an access operation of a memory accessible via a bus; ((¶0029, FIG. 3) The memory command is interpreted to be the claimed access command. The memory access operation is interpreted to be the claimed access operation. (¶0010) The memory cells of the memory unit are interpreted to represent the memory. (¶0029, FIG. 3) Luo obtains the claimed access command associated with the access operation of the memory accessible via a bus. (¶0017, FIG. 1) The memory is accessible through an interconnect that connects the memory units (140a and 140b) to memory interface (135a and 135b), which can be seen in figure 1. (¶0036) This interconnect is interpreted to include the bus (580).)
retrieving a memory map for the access operation based on the access command; and ((¶0029, FIG.3) The memory mapper (120) being able to retrieve a memory map from stored memory based off an access command is interpreted as retrieving the claimed memory map for the access operation based on the access command.)
performing the access operation associated with the memory of a memory unit via the bus based on the memory map. ((¶0030, FIG. 3) The memory unit (140a and 140b) is able to receive the retrieved memory map, which is the access operation, based on the memory map. This is interpreted to be the performing of the access operation associated with the memory via the bus based on the memory map.)
Luo teaches a bus, a memory accessible via a bus, and the memory of a memory unit, but does not teach:
a compute express link (CXL) bus, a memory accessible via a CXL bus, and the memory of a CXL device;
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation.
However, Ki does teach:
a compute express link (CXL) bus, a memory accessible via a CXL bus, and the memory of a CXL device; (paragraphs 0041, 0045, and 0068; Fig. 2);
wherein the CXL command includes instructions to access the memory in a pattern used in a tensor operation (paragraphs 0077 and 0090. It should be noted that the “vector transfer” is a type of “tensor operation”.)
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 17, Luo teaches wherein the memory map includes a specific sequence of memory access instructions to access a plurality of memory cells of the memory. ((Abstract) The memory map comprising a specific sequence of memory access instructions to access at least one memory cell of the memory array is interpreted to be the claimed memory map including a specific sequence of memory access instructions to access a plurality of memory cells of the memory.)
With regards to claim 18, Luo teaches further comprising accessing respective addresses of a plurality of memory cells based on the memory map to perform the access operation via the bus. ((¶0017) The memory map includes one or more a specific sequences of memory access instructions to access memory cells. Each memory access instruction includes an instruction for a respective address of a memory cell of the plurality of memory cells. (¶0017, FIG. 1) The memory is accessible through an interconnect that connects the memory units (140a and 140b) to memory interface (135a and 135b), which can be seen in figure 1. (¶0036) This interconnect is interpreted to include the bus (580). The memory access instructions being used to access the memory cells is interpreted to be the claimed accessing respective addresses of the plurality of memory cells based on the memory map to perform the access operation via the bus. This interpretation is consistent with the 112b rejection given above.)
Luo teaches the bus, does not teach:
The CXL bus.
However, Ki does teach:
The CXL bus. (paragraphs 0041, 0045, and 0068; Fig. 2).
Luo and Ki are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Luo’s system such that CXL is used to transfer input data to the memory as disclosed by Ki. The motivation would have been to reduce or eliminate unnecessary data transfers and/or enable more efficient data transfers (Ki, paragraph 0090).
With regards to claim 20, Luo teaches further comprising retrieving a memory map from a memory coupled to a processor. ((¶0010) The memory cells of the memory unit are interpreted to be the claimed memory. (¶0011, FIG.1) The processor 105 coupled to memory units (140a and 140b) is interpreted to be the claimed processor. (¶0029, FIG. 3) A memory mapper of a memory controller may retrieve a memory map from a stored memory, such as the memory cells of the memory unit, based on an access command. This is interpreted to be the claimed retrieving of a memory map from a memory coupled to a processor.)
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over LUO (US 20180307614 A1), in view of KI (US 20220113915 A1) as applied to claim 8 and 12 above, and further in view of Duan (US 20220244870 A1), hereinafter Duan.
With regards to claim 9, Luo in view of Ki teaches further comprising a processor ((Luo: ¶0011, FIG. 1) The processor (105) is interpreted to be the claimed processor.) coupled to the CXL device via the CXL bus, … (Ki: paragraphs 0041, 0045, and 0068; Fig. 2).
Luo in view of Ki does not teach:
wherein the CXL device is configured to route the specific sequence of CXL instructions to the memory via the processor.
However, Duan does teach:
wherein the CXL device is configured to route the specific sequence of CXL instructions to the memory via the processor. ((¶0029-¶0030, FIG. 6) The device (615) can cache data from both host-attached memory (610) and the host-managed device memory (620). (¶0029, FIG. 4) The device (615) is interpreted to be a CXL device. The device (615) being able to cache data into the Host-Attached memory (610) via the Host (605) is interpreted as the claimed CXL unit configured to route the specific sequence of CXL instructions to the memory via the processor. This interpretation is consistent with the 112b rejection given above.)
Luo in view of Ki and Duan are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus disclosed by Luo in view of Ki to route data from a CXL device to the memory via the processor using the teaching of Duan. The motivation would have been to have coherent data between the CXL device and the processor for improved system optimization. (Duan: ¶0046)
With regards to claim 15, Luo in view of Ki teaches the processor, ((Luo: ¶0011, FIG. 1) The processor (105) that is coupled to memory units (140a and 140b) interpreted to be the claimed processor.)
the CXL instructions, (Ki: paragraphs 0041, 0045, and 0068; Fig. 2).
the memory, ((Luo: ¶0010) The memory cells in the memory unit are seen as the claimed memory. (Ki: paragraphs 0041, 0045, and 0068; Fig. 2).
and the CXL bus. (Ki: paragraphs 0041, 0045, and 0068; Fig. 2).
Luo in view of Ki does not teach:
wherein the processor is configured to route the specific sequence of CXL instructions to the memory via the CXL bus.
However, Duan does teach:
wherein the processor is configured to route the specific sequence of CXL instructions to the memory via the CXL bus. ((¶0029) The device (615) is interpreted to be a CXL device. (¶0030, FIG. 6) The host (605) can cache data in both the host-attached memory (610) and host-managed device memory (620). The host (605) is interpreted to include the processor. The host (605) would have to use a type of interconnect to send data to the host-managed device memory (620). (¶0001, FIG. 1) The communication link (115) following the CXL protocol standard is interpreted to include the CXL bus. (¶0030, FIG. 6) The caching of data from the host (605) to the host-managed device memory (620) is interpreted to be the claimed processor routing the specific sequence of CXL instructions to the memory via the CXL bus.)
Luo in view of Ki and Duan are analogous art because they are from the same field of endeavor, that being Data Storage Systems. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus disclosed by Luo in view of Ki to route data from the processor to the memory via the CXL bus using the teaching of Duan. The motivation would have been to have coherent data between the CXL device and the processor for improved system optimization. (Duan: ¶0046)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Arpan P. Savla whose telephone number is (571)272-1077. The examiner can normally be reached M-F, 10AM-6PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
