DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments (11/25/2025) with respect to the art rejection of at least independent claims 1, 12 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The 11/25/2025 amendment to the specification ([0044]) is acceptable and has been entered.
Claim Objections
Claims 12-14, 16-17, 21 are objected to because of the following informality:
Claim 12, line 2 the recited “of crest factor reduction circuitry” should be “of a crest factor reduction circuitry”.
Dependent claims 13-14, 16-17, 21 are also objected to since they depend on objected claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-13, 16-19, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. (U.S. 2021/0176107).
With respect to claim 1, Hou et al. disclose: crest factor reduction circuitry (refer to at least the CFR reduction circuitry of Fig. 7 [0023], [0020], at least lines 1-10 of [0120] and transmitter of Fig. 2 [0018] comprising a CFR function [0045], [0080] and refer to related [0052]-[0053]. Alternatively refer to the CFR reduction circuitry of Fig. 10, [0026], [0095]) comprising a clip and filter block (Fig. 7, refer to the components to the left of the DUCs corresponding to the claimed “clip and filter block” or the components to the right of the adder corresponding the claimed “clip and filter block” and at least [0053]-[0054], [0077], [0079] refer to at least the disclosed “…multi-band signals are clipped and filtered in two steps”, or both components to the left of the DUCs and to the right of the adder correspond to the claimed “clip and filter block” . Alternatively refer to the CFR reduction circuitry of Fig. 10, the components to the left of the DACs corresponds to the claimed “clip and filter block”, or the components to the right of the power combiner correspond to the claimed “clip and filter block”, and at least [0095], or both the components to the left of the DACs and the right of the power combiner correspond to the claimed “clip and filter block”) and a frequency shift block (Fig. 7, the DUCs (digital upconverters correspond to the claimed “frequency shift block” and refer to at least [0078]. Alternatively refer to Fig. 10, the analog frequency upconverters (mixers which receive signals out of local oscillators) correspond to the claimed “frequency shift block” [0095]) the crest factor reduction circuitry configured to receive an input signal (Fig. 7 refer to an input signal (e.g. one or more of the signals (SIG. B1, SIG. B2, SIG. BN), Step1 of [0053], [0076]-[0077]), and to generate an output signal based on shifting a frequency spectrum of the input signal to be centered about a carrier frequency of the output signal (Fig. 7 frequency shifting using each of the DUCs outputs one or more output signals, [0078] “…RF frequency of operation…” and Fig. 2, [0080]. Alternatively in Fig. 7 the SIG. OUT corresponds to the claimed output. In the embodiment of Fig. 10 the input and output signal correspond to one or more of Sig. B1….Sig. Bn, and one or more of the outputs of the frequency shift block, and CFR Step 1 is performed. Alternatively in Fig. 10 the Sig. Out corresponds to the claimed output signal generated based on CFR 1 and CFR 2 (and frequency shifting). The frequency shifting is performed on an altered (subjected to processing) version of the respective input signals) the output signal having a reduced peak-to-average power ratio (PAPR) relative to the input signal ([0053] Step 1 [0073]-[0074]. The CFR operation reduces the PARP of the output signal as compared to the input signal [0008], [0061]. Alternatively in Fig. 7, signal SIG. OUT has a reduced PAPR relative to the input signal according to CFR 1 and CFR 2 steps, [0008], [0075], [0079]. In Fig. 10 the Sig, Out has a reduced PARP compared to the input signal (one or more of Sign. B1,…Sig. BN)); and a transmitter coupled to the crest factor reduction circuitry and configured to transmit a radio frequency (RF) signal based on the output signal (refer to Fig. 2, for example the claimed transmitter comprises the Power Amplifier, Band Filters and Antenna [0080]. For the embodiment of Fig. 10, the claimed transmitter comprises a Power Amplifier, Band Filters and an Antenna).
With respect to claim 2, Hou et al. disclose: wherein the input signal comprises a digital signal, and the frequency shift block comprises a digital frequency shift (DFS) block (refer to the Digital Upconverters (DUCs) of Fig. 7 and Fig. 2 and at least [0073]-[0074]).
With respect to claim 5, Hou et al. disclose: wherein the clip and filter block comprises a clipping sub-block configured to clip an amplitude of the input signal according to a clipping threshold to generate a clipped signal (Fig. 7, the clip and filter block comprises the components to the left of the DUC, and refer to [0077], the claimed clipping sub-block comprises the envelope amplitude determining components, the threshold comparison block and the scaling blocks [0077] refer to the (amplitude) scaled input signal(s), [0053] Step 1, and [0077]. Alternatively, the claimed clipping sub-block comprises the envelope amplitude determining components, the threshold comparison block, the scaling blocks, filter(s) and subtractors(s). The subtraction of the channel noise from the input signal(s) generates (noise) clipped signal(s) . In the embodiment of Fig. 10, consider a similar limitation analysis).
With respect to claim 8, Hou et al. disclose: wherein the clip and filter block comprises a first clip and filter block (Fig. 7 or Fig. 10, first clip and filter block corresponds to the components to the left of the DUCs (Fig.7) or the components to the left of the DACs of Fig. 10), the crest factor reduction circuitry comprising a set of blocks (set of blocks comprises the blocks of the first clip and filter block of Fig. 7 or Fig. 10 and the blocks of a second clip and filter block (components to the right of the adder of Fig. 7 or to the right of the power combiner of Fig. 10)) comprising the first clip and filter block (refer above) disposed before the frequency shift block (before or to the left of the DUCs (Fig. 7) or to the left of the mixers (of Fig. 10), relative to a flow of data of the input signal through the crest factor reduction circuitry, and a second clip and filter block disposed after the frequency shift block (the claimed second clip and filter block comprises the components to the right of the adder (Fig. 7) or the right of the power combiner (Fig. 10) .
With respect to claim 9, Hou et al. wherein the crest factor reduction circuitry comprises a plurality of sets of blocks (Fig. 7, refer to the plurality of sets of blocks (per input signal) to the left of the adder). Fig. 10 refer to the plurality of sets of blocks (per input signal) to the left of the power combiner), wherein each set of blocks of the plurality of sets of blocks comprises one or more respective clip and filter blocks (per input signal, refer to the components to the left of the respective DUC in Fig. 7. Per input signal, refer to the components to the left of the mixers (frequency shift block)) and a respective frequency shift block (the respective DUC (Fig. 7) or the respective mixer (Fig. 10)), a set of blocks of the plurality of sets of blocks comprising the clip and filter block and the frequency shift block (refer above to the components of Fig. 7 or Fig. 10)).
With respect to claim 10, Hou et al., disclose: wherein the respective frequency shift block of each set of blocks of the plurality of sets of blocks is configured to shift a frequency spectrum of the input signal or an intermediate signal corresponding to an altered version of the input signal to be centered about a different frequency (Fig. 7, refer to the DUC(s) functioning on respective altered versions of respective input signals. Fig. 10 refer to the mixer(s) functioning on respective altered versions of respective input signals).
With respect to claim 11, Hou et al. disclose: wherein the different frequency of each set of blocks of the plurality of sets of blocks corresponds to a different carrier frequency of the RF signal (as already explained above and refer to at least lines 1-5 of [0078] and at least lines 1-7 of [0076], [0077] as related to Fig. 7 and lines 1-7 of [0076]-[0077] and [0095] as related to Fig. 10).
Claim 12 is rejected based on the rationale used to reject claim 1 above. Refer to all the portions of Hou et al. already cited above The claimed “clip and filter circuitry” comprises the components that perform clipping and filtering on the per signal and on the combined multiband signal in Fig. 7 or Fig. 10. The claimed “clipping and filtering” of lines 5-6 is performed on one or more of the SIG. B1….SIG.BN by the components to the left of the DUC(s) of Fig. 7 or performed on one or more the Sig. B1….Sign BN by the components to the left of the mixer(s) of Fig. 10). The claimed third signal is generated by one or more of the DUCs of Fig. 7 or the one or more mixers of Fig. 10). The claimed “clipping and filtering” of lines 10-11 is performed by the components to the right of the adder of Fig. 7 or to the right of the power combiner of Fig. 10).
Claim 13 is rejected based on the rationale used to reject claim 4 above and the second signal of claim 13 is a frequency modulated signal with channel noise removed ([0077]).
With respect to claim 16, Hou et al. disclose: wherein the clip and filter circuitry comprises: a clipping sub-block configured to clip an amplitude of the first signal according to a clipping threshold to generate a clipped signal (Fig. 7 refer for example to a scaler “X” which corresponds to the claimed “clipping sub-block” which clips (scales) the first signal according to Threshold 1 [0077]); and a filtering sub-block configured to filter the clipped signal (refer to the channel filter band 1 (a filter) per [0077]. Alternatively refer to Fig. 10, and a scaler “X” which clips based on Threshold 1 and the ChannelFilter Band 1).
With respect to claim 17, Hout et al. disclose: wherein the clip and filter circuitry comprises a plurality of sets of sub-blocks in series (Fig. 7, e.g. refer to 2 sets of sub-blocks in series, e.g. the scaler “X” and channel filter band 1 and the clipping block that comprises Threshold 2 and band-stop filter. Fig. 10, refer to 2 sets of sub-blocks in series, e.g. the scaler “X” and channel filter Band 1 and the Class-C amplifier that clips [0077] using Threshold 2 and the Band-Stop Filter), wherein each set of sub-blocks of the plurality of sets of sub-blocks comprises a respective clipping sub-block (the scaler and the component which uses Threshold 2 in Fig. 7. The scaler and the class- C amplifier in Fig. 10) and a respective filtering sub-block (Channel Filter Band 1 and Band-Stop filter in Fig. 7. The Channel Filter Band 1 and the Band-stop Filter in Fig. 10).
Claim 21 is rejected based on the rationale used to reject claim 12 above. The per band clip and filter (Stage 1 components) and the respective DUCs correspond to the claimed “plurality of circuits” (Fig. 7 and [0076]-[0077], [0078]). The per band clip and filter (Stage 1 components) and the respective mixers correspond to the claimed “plurality of circuits” (Fig. 10 and [0076]-[0077], [0095]).
Claim 18 is rejected based on the rationale used to reject claim 12 above. Additionally refer [0100] “…access node 1100”, “computer program including instructions…”, “non-transitory computer readable medium such as a memory” of [0100] Also [0096] Fig. 11 corresponds to radio access node 1100 “…one or more functions…as described herein…”. Regarding the claimed “component carrier” refer to Fig. 3 spectrum of a signal going into the antenna (e.g. Fig. 2 and related to Fig. 7 or Fig. 10) comprising signals having a respective carrier that corresponds to the claimed “component carrier”.
With respect to claim 19, Hou et al., disclose: wherein the first signal or the third signal is clipped and filtered using a plurality of clipping stages and a plurality of filtering stages (refer the parallel clipping stages clipping the first signal (e.g. the first input signal comprises SIG. B1 and SIGB2 in Fig. 7…or the first input signal comprises Sig B1.and Sing. B2 in Fig. 10. Refer to the plurality (2) of filtering stages in “parallel”).
Claim 22 is rejected based on the rationale used to reject claim 18 above. The claimed fifth signal corresponds to an additional SIG. Bx (compared to the rejection of claim 18) or an additional Sig Bx (as compared to the rejection of claim 18). Clip and filtering is performed by the “branch” used to apply CFR Stage 1 (Fig. 7 or Fig. 10) to the fifth signal. The shift a frequency spectrum of the sixth signal is performed by the respective DUC or mixer (Fig. 7 or Fig. 10). The clip and filter the seventh signal is performed (in the combined multiband signal) in CFR Stage 2 (Fig. 7 or Fig. 10) and output the eight signal (SIG OUT or Sig Out).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hou et al. (U.S. 2021/0176107) in view of Rick et al. (U.S. 2008/0013639).
With respect to claim 3, Hou et al. do not disclose: wherein the DFS block
comprises a coordinate rotation digital computer (CORDIC).
Implementing digital upconversion, Rick et al. disclose: a DFS block
comprises a coordinate rotation digital computer (CORDIC) ([0073], [0057] and approximate middle of [0028] “Each rotator 214 operates as a digital upconverter…").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the frequency shift block (DUC(s)) of Hou et al. using respective CORDIC(s)(part of a respective rotator which operates as a frequency upconverter) as taught by Rick et al. to use known suitable components (including CORDIC) to specifically implement the DUC(s) of Hou et al. with a reasonable expectation of success.
With respect to claim 4, Hou et al. disclose: wherein the input signal comprises a frequency modulated signal, and wherein (one or more of the DUC(s) of Fig. 7) is configured to shift a frequency spectrum of the frequency modulated signal to be centered about the carrier frequency (for example refer to [0076], “…each of these N signals consists of one carrier or multiple closely spaced carriers. For example each input signal can be the complex baseband signal consisting of all carriers within a single band…” Based on the above, the input signal (Fig. 7) corresponds to the claimed frequency modulated signal. And refer to the function of the one or more DUCs in at least lines 1-3 of [0078]).
Hou et al. do not expressly disclose: the frequency shift block (interpreted as comprising a CORDIC, due to the interpretation that the term “frequency shift block” of claim 4 is invoking 35 U.S.C. 112(f). Refer to the previous Office Action section Claim Interpretation).
Implementing digital upconversion, Rick et al. disclose: a coordinate rotation digital computer (CORDIC) (part of digital upconverter implemented by a rotator, [0073], [0057] and approximate middle of [0028] “Each rotator 214 operates as a digital upconverter…").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the frequency shift block (DUC(s)) of Hou et al. using respective CORDIC(s)(part of a respective rotator which operates as a frequency upconverter) as taught by Rick et al. to use known suitable components (including CORDIC) to specifically implement the DUC(s) of Hou et al. with a reasonable expectation of success.
Allowable Subject Matter
Claims 7, 14, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Regarding claim 14, the minor informality of claim 12 needs to be corrected).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Berangi et al. (U.S. 2005/0163248) refer to the clip-filter-clip-filter (CFCF) circuit of Fig. 12.
Fomin et al. (U.S. 10,826,739) refer to the CFR architecture of Fig. 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA VLAHOS whose telephone number is (571)272-5507. The examiner can normally be reached M 8:00-4:00, TWRF 8:00-2:00.
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SOPHIA VLAHOS
Examiner
Art Unit 2633
/SOPHIA VLAHOS/Primary Examiner, Art Unit 2633 1/12/2026