DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) were submitted on 06/05/24 and 12/05/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claim 18 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/22/26. Applicant further elected Species 1 drawn to figures 1A and 1B without traverse.
Drawings
The drawings were received on 06/05/24. These drawings are acceptable.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 lines 1-2 “the gate driver of claim 1,wherein the high side signal forwarding circuit” appears it should be replaced with “the gate driver of claim 2, wherein the high side signal forwarding circuit”. The high side signal forwarding circuit was introduced in claim 2 and would lack antecedent basis if claim 3 was dependent on claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 12-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Wu (US 10637348 B1).
Regarding claim 1, Wu discloses a gate driver configured to drive a high side switch (fig 2, gate driver 200 and high-side transistor 291/Q1), comprising: a low voltage control logic (fig 2, dead-time control circuit 210) configured to: receive a high side control signal (fig 2, VTH_HS) and a timing control signal (fig 2, IN/201 programmable delay chains); and generate an internal pulsed high side control signal based on the high side control signal and the timing control signal (fig 2, signal HS_ON from first pulse signal PP1 and first delay count DLY_1); and a high side switch control circuit (fig 2, high-side driver HS_Driver 221) coupled to the low voltage control logic (see connection in fig 2 to 210) and configured to control the high side switch based on the internal pulsed high side control signal (see fig 2, PP1 input to 214), wherein the high side switch control circuit comprises a high side support function circuit, and wherein the high side support function circuit is configured to be enabled based on a first pulse of the internal pulsed high side control signal and to be activated based on a second pulse of the internal high side pulsed control signal (col 2 lines 13-32 explains first, second, third, and fourth time instances of a first and a second pulse signals that initiate the output driver circuit signals; also see claim 1).
Regarding claim 2, Wu discloses the gate driver of claim 1, further comprising: an insulation barrier between the low voltage control logic and the high side switch control circuit, wherein the insulation barrier is configured to electrically isolate the low voltage control logic from the high side switch control circuit (implicit; the use of isolated gate drivers and digital isolators is so standard that it’s assumed in the system architecture and in safety‑critical or regulated applications, it is explicitly required by design documents, safety analysis, and compliance testing); and a high side signal forwarding circuit (fig 2, level shifter 223) coupled between the low voltage control logic and the high side switch control circuit (fig 2, 223 is coupled between 210 and 221), wherein the high side signal forwarding circuit is configured to provide the internal pulsed high side control signal from the low voltage control logic to the high side switch control circuit across the insulation barrier (fig 2, 223 receives pulsed high side control signal HS_ON and delivers signal to 221).
Regarding claim 3, Wu discloses the gate driver claim 2, wherein the high side signal forwarding circuit is one of a level shift circuit, a coreless transformer, an optocoupler or a solid state relay (Wu fig 2, level shifter 223).
Regarding claim 4, Wu discloses the gate driver claim 1, wherein the low voltage control logic is further configured to: generate the first pulse of the internal pulsed high side control signal (figs 2 and 3, HS_ON from PP1 and DLY_1 inputs) based on a leading edge of the high side control signal (figs 2 and 3, RISE signal to 211; col 6 lines 29-67 describes utilizing the rising and falling edge of the HS_ON and LS_ON signals) and generate the second pulse of the internal pulsed high side control signal (figs 2 and 3, HS_ON) by comparing a high side ramp-up signal (figs 2 and 3, DLY_1) and the timing control signal (fig 2, IN/201 input to DLY_CHAIN) the high side ramp-up signal a non-zero signal slope upon reception of the leading edge of the high side control signal (fig 3, see non-zero signal DLY_1 when PP1 is high).
Regarding claim 5, Wu discloses the gate driver of claim 4, wherein the low voltage control logic comprises: a first high side edge triggered pulse generator configured to generate the first pulse of the internal pulsed high side control signal based on the leading edge of the high side control signal (figs 2 and 3, see VTH_HS, RISE and FALL inputs to 211); and a high side support function activation signal circuit (fig 2, circuit including 211, 214, and 216) configured to generate the second pulse of the internal pulsed high side control signal (figs 2 and 3, HS_ON), wherein the high side support function activation signal circuit comprises: a high side leading edge triggered ramp-up circuit configured to provide the high side ramp-up signal responsive to the leading edge of the high side control signal (fig 2, circuit 211 receiving RISE and FALL signals to output PP1 signal); a high side ramp-up signal comparator configured to compare the high side ramp-up signal with the timing control signal (fig 2, 214), and to output a high side comparison signal based on the comparison (fig 2, DLY_1); and a second high side edge triggered pulse generator configured to generate the second pulse of the internal pulsed high side control signal based on a leading edge of the high side comparison signal (fig 2, DLY_CHAIN block with HS_ON output).
Regarding claim 12, Wu discloses the gate driver claim 1, wherein the gate driver is further configured to drive a half-bridge comprising the high side switch and a low side switch (fig 2, half bridge including high-side transistor 291/Q1 and low-side transistor 292/Q2), wherein the low voltage control logic is further configured to: receive a low side control signal (fig 2, VTH_LS) and generate a low side support function activation signal (fig 2, PP2) based on the low side control signal and the timing control signal (fig 2, IN/201 programmable delay chains) wherein the gate driver further comprises: a low side switch control circuit (fig 2, low-side driver LS_Driver 222 and fixed delay 224) coupled to the low voltage control logic (fig 2, driver 222 is coupled to dead-time control circuit 210) and configured to control the low side switch based on the low side control signal (fig 2, LS_Driver 222 controls LS switch Q2), wherein the low side switch control circuit comprises a low side support function circuit (col 6 lines 10-11 “supporting circuitry”; fig 2, fixed delay circuit 224), and wherein the low side support function circuit is configured to be activated based on the low side support function activation signal (fig 2, second gate control signal LS_ON).
Regarding claim 13, Wu discloses the gate driver of claim 12, wherein the low voltage control logic is further configured to: generate the low side support function activation signal by comparing a low side ramp-up signal and the timing control signal (fig 2, 214; col 5 lines 59-65 signal LS_On based on the input switching signal IN and the first and second delay counts, DLY_1 and DLY_2 compared in the DLY_CHAIN block), the low side ramp-up signal having a non-zero signal slope upon reception of a leading edge of the low side control signal (figs 2 and 3 DLY_2 non-zero slope during transition; col 6 lines 29-35).
Regarding claim 14, Wu discloses the gate driver of claim 13, wherein the low voltage control logic further comprises: a low side support function activation signal circuit (fig 2, circuit including blocks 212, 214, and 224) configured to generate the low side support function activation signal (fig 2, second gate control signal LS_ON), wherein the low side support function activation signal circuit comprises: a low side leading edge triggered ramp-up circuit configured to provide the low side ramp-up signal responsive to the leading edge of the low side control signal (fig 2, circuit 212 receiving RISE and FALL signals to output PP2 signal); and a low side ramp-up signal comparator configured to compare the low side ramp-up signal with the timing control signal (fig 2, 214) and to output the low side support function activation signal based on the comparison (fig 2, DLY_CNT_2 signal from lower block of 214).
Regarding claim 15, Wu discloses the gate driver claim 12, wherein the high side support function circuit is configured as a high side protection function circuit, and wherein the low side support function circuit is configured as a low side protection function circuit, and the timing control signal is configured as a common protection function blanking control signal (fig 2, low side circuit including blocks 212, 214, and 224 and high side circuit including blocks 211, 214, and 216 operates as a high/low-side protection loop containing a dead-time measurement circuit, which dynamically adjusts blanking times to avoid shoot-through on the high/low-side power transistor Q1/Q2; timing control signal IN with adaptive signals DLY_1, DLY_2, PP1, PP2 all collectively provide a common protection function blanking control signal, preventing false overcurrent or shoot-through triggers during switching transitions as mapped out in the timing diagram Fig. 3).
Regarding claim 16, Wu discloses the gate driver claim 1,wherein the gate driver is monolithically integrated in a single chip (fig 13, gate driver circuit 1310 implemented on the single integrated circuit chip 1300; see col 12 line 62 – col 13 line 12 “implemented on the single integrated circuit chip 1300”).
Regarding claim 17, Wu discloses a system (fig 2, blocks 200 and 290), comprising: a half-bridge arrangement comprising a high side switch and a low side switch and a gate driver configured to drive the half-bridge arrangement (fig 2, switching half-bridge circuit 290, high-side transistor 291/Q1, low-side transistor 292/Q2, gate driver 200), the gate driver comprising: a low voltage control logic (fig 2, dead-time control circuit 210) configured to: receive a high side control signal (fig 2, VTH_HS), a low side control signal (fig 2, VTH_LS) and a timing control signal (fig 2, IN/201 programmable delay chains); generate an internal pulsed high side control signal based on the high side control signal and the timing control signal (fig 2, signal HS_ON from first pulse signal PP1 and first delay count DLY_1); and generate a low side support function activation signal based on the low side control signal and the timing control signal (fig 2, 214; col 5 lines 59-65 signal LS_On based on the input switching signal IN and the first and second delay counts, DLY_1 and DLY_2 compared in the DLY_CHAIN block); a high side switch control circuit coupled to the low voltage control logic and coupled to a control terminal of the high side switch (fig 2, high-side driver HS_Driver 221 see connection in 210 and control terminal of Q1), wherein the high side switch control circuit is configured to control the high side switch based on the internal pulsed high side control signal (fig 2, signals HS_ON / HS_G control Q1), and wherein the high side switch control circuit comprises a high side support function circuit (fig 2, circuit including 211, 214, and 216) configured to be enabled based on a first pulse of the internal pulsed high side control signal and to be activated based on a second pulse of the internal high side pulsed control signal (figs 2 and 9, first pulse of the internal pulsed high-side control signal PP1, further detailed in the logic schematic of Fig. 9, the signal PP1 is fed into the clock input of the high-side register 911 PP1_REG. The first pulse clocks a high state '1' into the register, shifting its state and enabling the multiplexer 913. The second pulse of PP1 (in combination with the main clock signal CLK) pulse/clock activates the N-bit digital counter 914 DLY_CTR1 to execute a count-up +1 or count-down -1 operation to update the digital delay command DLY1<N-1:0>, which adjusts the delay chain 214 for the next cycle); and a low side switch control circuit (fig 2, LS_driver 222 and fixed delay 224) coupled to the low voltage control logic and coupled to a control terminal of the low side switch (fig 2, see connection to 210 and control terminal of Q2), wherein the low side switch control circuit is configured to control the low side switch based on the low side control signal (fig 2, LS_G signal input to Q2), wherein the low side switch control circuit comprises a low side support function circuit (col 6 lines 10-11 “supporting circuitry”; fig 2, fixed delay circuit 224) configured to be activated based on the low side support function activation signal (fig 2, second gate control signal LS_ON).
Regarding claims 19-20, they are the method version of claims 1 and 4 above and are rejected for the reasons above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 10637348 B1) as applied to claim 1 above, and further in view of Lee (US 20110080205 A1).
Regarding claim 6, Wu discloses the gate driver of claim 5.
Wu discloses in fig 9, flip flops 911 and 921 however, no reset RST pin or line is illustrated for these two components therefore, Wu fails to disclose wherein the low voltage control logic is further configured to generate a high side switch control circuit reset signal configured to reset the high side switch control circuit.
Lee discloses a switch driving circuit that can prevent element damage and malfunction. Lee discloses low voltage control logic (fig 2, logic in blocks 120 and 150) is further configured to generate a high side switch control circuit reset signal configured to reset the high side switch control circuit (fig 2, switching control signals SC1 and SC2 input to flip flop 158, reset terminal R of the flip-flop 158).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu and incorporate the use of reset flip flop signal as taught by Lee. The advantage of this design is that proactive reset signal from the low-voltage side enforces dead-time compliance. Enforcing a reset path from this low-voltage timing logic to the high-side driver is the foundational method used to guarantee that the high-side state accurately tracks the calculated dead-times shown in the timing diagram.
Regarding claim 7, Wu and Lee disclose the gate driver claim 6, wherein the first high side edge triggered pulse generator is further configured to generate the high side switch control circuit reset signal based on a trailing edge of the high side control signal (Lee fig 2, when the high-side input control signal HIN transitions from low to high, the Edge detection unit 122 detects the leading edge and generates a pulse signal PS1. This pulse drives the switch SW1 to pull down the SC1 line, which goes through receiver 152 to trigger the Set S input of the latch 156, turning on the high-side gate driver. When HIN transitions from high to low, the Edge detection unit 122 detects the trailing/falling edge and generates a pulse signal PS2. This pulse turns on switch SW2, pulling down the SC2 line, which passes through receiver 154 to activate the Reset R1 input of the latch 156, turning off the high-side power switch Q1.).
Regarding claim 8, Wu and Lee disclose gate driver claim 6, wherein the high side switch control circuit (Lee fig 2, gate signal generator 150) is further configured to: turn-on the high side switch (Lee fig 2, switch Q1) and enable the high side support function circuit (Lee fig 2, 140) based on latching the first pulse of the internal pulsed high side control signal and activate the high side support function circuit based on latching the second pulse of the internal pulsed high side control signal (Lee fig 2, pulses P1, P2, and P3 from edge detection unit 122 are inputs to blocks 130, 140, and 150; flip flop 158 and MOSFETs M1/M2 latches the incoming pulses to maintain the state of the high-side gate output HO).
Regarding claim 9, Wu and Lee disclose the gate driver claim 8, wherein the high side switch control circuit is further configured to: turn-off the high side switch and disable the high side support function circuit based on unlatching the first pulse of the internal pulsed high side control signal and the second pulse of the internal pulsed high side control signal to the high side switch control circuit reset signal (Lee fig 2 and pars [0050-0052] protection unit 140 transmits a high-level protection pulse signal PS3 when the sense voltage Vrs is higher than the reference voltage Vref to the edge detection unit 122 for generation of the OFF-pulse signal PS2, safeguarding the circuit from latch-up or damage).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 10637348 B1) as applied to claim 1 above, and further in view of Mondzik et al. (US 20180026517 A1), hereinafter Mondzik.
Regarding claim 11, Wu discloses the gate driver of claim 1. Wu fails to disclose wherein: the high side support function circuit is configured to detect a desaturation of the high side switch and to turn off the high side switch based on the detected desaturation. DESAT protection is a standard safety feature integrated into high-voltage gate drivers and is well known in power electronics to protect power switches from catastrophic damage during short-circuits or extreme overcurrent events.
Mondzik discloses desaturation monitoring in its disclosure of a driver module. Mondzik disclose a high side support function circuit is configured to detect a desaturation of the high side switch and to turn off the high side switch based on the detected desaturation (par [0005] “Very common are, for example, driver modules with an overvoltage monitoring input for the so-called “desaturation monitoring” (DESAT), whereby the power semiconductor switch is opened via a corresponding control by the driver module in the case of an excessively high voltage between a controlled terminal and a reference potential terminal of the closed power semiconductor switch.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu and incorporate the use of DESAT protection/detection as taught by Mondzik. The advantage of this design is that the driver circuit would include the standard safety feature to open the power semiconductor switch in the case of high voltage.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, Wu and Lee disclose the gate driver claim 8, wherein the high side switch control circuit further comprises: a high side switch control flip-flop having a set input and a reset input (Lee fig 2, flip flop 158 set S and reset R) and configured to receive the internal pulsed high side control signal at the set input (Lee fig 2, SC1 from 152 S terminal of 158) and to receive the high side switch control circuit reset signal at the reset input (Lee fig 2, SC2 from 154 at R terminal of 158).
Wu, Lee, and Sakai et al. (US 20180337666 A1) have been found to be the closest prior art however, none of the prior art, taken singly or in combination, teach “a high side support function flip-flop-having a set input, a reset input, and an enable input, and configured to receive the internal pulsed high side control signal-at the set input, the high side switch control circuit reset signal at the reset input and an output of the high side switch control flip-flop at the enable input”.
Conclusion
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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