CTNF 18/735,396 CTNF 100074 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement submitted on 6 Jun 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant's election with traverse of Group I: claims 1-16 in the reply filed on 4 May 2026 is acknowledged. The traversal is on the grounds that newly amended claims 17-20 are no longer drawn to a distinct invention. This has been fully considered and is persuasive. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections 07-29-01 AIA Claim 10 objected to because of the following informalities: Claim 10 : the limitation “second terminal of the second capacitor” should be changed to “ the second terminal of the second capacitor” because “a second capacitor having first and second terminals” has already been claimed in line 7 . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems") . Regarding Claim 1 , Jang teaches a multiphase power converter (Fig 2) , comprising: a first phase circuit (102, Fig 2) having a first input (input to 202, Fig 2) , a first output (cathode of 232, Fig 2) , and a first terminal (emitter of 212, Fig 2) , the first output coupled to a positive voltage terminal (cathode of 232 coupled to top rail of 30, Fig 2) , and the first terminal coupled to a first negative voltage terminal (emitter of 212 coupled to bottom rail of 30, Fig 2) ; a second phase circuit (104, Fig 2) having a second input (input to 204, Fig 2) , a second output (cathode of 234, Fig 2) , and a second terminal (emitter of 214, Fig 2) , the second input coupled to the first input (input to 204 coupled to the input of 202, Fig 2) , the second output coupled to the positive voltage terminal (cathode of 234 coupled to top rail of 30, Fig 2) , and the second terminal coupled to the first negative voltage terminal (emitter of 214 coupled to bottom rail of 30, Fig 2) ; and a current sense circuit (110, Fig 2) . Jang does not teach a current sense circuit having first and second current sense terminals, the first current sense terminal coupled to the first negative voltage terminal and the second current sense terminal coupled to a second negative voltage terminal. Dusmez teaches a conventional current sensing circuit for use in a multiphase power converter including a current sense circuit (Rshunt, Fig 3) having first and second current sense terminals (left and right terminals of Rshunt, Fig 3) , the first current sense terminal coupled to the first negative voltage terminal (left terminal of Rshunt connected to the diode bridge rectifier at the input, Fig 3) and the second current sense terminal coupled to a second negative voltage terminal (right terminal of Rshunt connected to the output, Fig 3) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current sensing circuit in Jang, as taught by Dusmez, as it provides the advantage of fewer sensors and lower cost (p5116 Col 2 last paragraph-p5117 Col 1 first paragraph) . Regarding Claim 7 , the combination of Jang and Dusmez discloses all of the limitations of Claim 1 above, and further discloses wherein the current sense circuit includes a resistor having a first resistor terminal coupled to the first current sense terminal and a second resistor terminal coupled to the second current sense terminal (left and right terminals of current sense resistor Rshunt, Fig 3 of Dusmez) . 07-21-aia AIA Claim s 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems"), and further in view of Imamura (US 20240396455 A1) . Regarding Claim 2 , the combination of Jang and Dusmez discloses all of the limitations of Claim 1 above. The combination of Jang and Dusmez does not teach a first capacitor having first and second capacitor terminals, the first capacitor terminal coupled to the positive voltage terminal, and the second capacitor terminal coupled to the first current sense terminal; and a second capacitor having third and fourth capacitor terminals, the third capacitor terminal coupled to the positive voltage terminal, and the fourth capacitor terminal coupled to the second current sense terminal. Imamura teaches a conventional current detection circuit for use in a power converter (Rs, Co1, Co2, Fig 3) including a first capacitor having first and second terminals, the first capacitor terminal coupled to the positive voltage terminal, and the second capacitor terminal coupled to the first current sense terminal (Co1 connected to Vout and top terminal of Rs, Fig 3) ; and a second capacitor having third and fourth capacitor terminals, the third capacitor terminal coupled to the positive voltage terminal, and the fourth capacitor terminal coupled to the second current sense terminal (Co2 connected to Vout and bottom terminal of Rs, Fig 3) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current detection circuit in Jang, as taught by Imamura , as it provides the advantage of reducing the effects of EMI and improving the efficiency ([0048] of Imamura) . Regarding Claim 3 , the combination of Jang, Dusmez, and Imamura discloses all of the limitations of Claim 2 above, and further teaches a damping circuit having first and second damping circuit terminals, the first damping circuit terminal coupled to the positive voltage terminal (the snubber circuit formed by Rsnb2 and Csnb2 is connected to positive output line 104 via the right side of Csnb2, Fig 6 of Imamura) . Regarding Claim 4 , the combination of Jang, Dusmez, and Imamura discloses all of the limitations of Claim 3 above, and further teaches wherein the damping circuit includes a resistor coupled in series with a third capacitor (Rsnb2 and Csnb2 are connected in series to C1, Fig 6 of Imamura) . Regarding Claim 5 , the combination of Jang, Dusmez, and Imamura discloses all of the limitations of Claim 3 above, and further teaches wherein the second damping circuit terminal is coupled to the second current sense terminal (the left side of Rsnb2 is connected to the top of Rs via M1, Fig 6 of Imamura) . Regarding Claim 6 , the combination of Jang, Dusmez, and Imamura discloses all of the limitations of Claim 3 above, and further teaches wherein the second damping circuit terminal is coupled to the first current sense terminal (the right side of Csnb2 is connected to the bottom of Rs via C1, Fig 6 of Imamura) . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems"), and further in view of Schock (US 20160336892 A1) . Regarding Claim 8 , the combination of Jang and Dusmez teaches all of the limitations of Claim 1 above. The combination of Jang and Dusmez does not teach a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal has fallen below a threshold, and convert an analog signal from the current sense circuit to a digital signal. Schock teaches a conventional controller for use in a power converter (see Fig 2) including a controller configured to generate a carrier signal (18 controls the PWM by generating carrier 40, which is the output of an up/down counter, Figs 2 & 4, [0032]) , determine that a magnitude of the carrier signal has fallen below a threshold (" the center point represents zero, with progressively larger counts left and right from that center point.", Fig 4, [0032]) , and convert an analog signal from the current sense circuit to a digital signal ("Reference numerals 48 and 50 illustrate analog/digital (a/d) sample times, which are defined herein as points during the duty cycle when the current is sampled from the single shunt or current sensor 38.", Fig 4, [0032]) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the digital signal controller in Jang, as taught by Schock, as it provides the advantage of minimizes power draw and increases converter efficiency by selectively triggering the ADC . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems"), and further in view of Imamura (US 20240396455 A1) and Microchip ("Transition to Digital ADC") . Regarding Claim 9 , the combination of Jang and Dusmez discloses all of the limitations of Claim 1 above, and further teaches wherein the current sense circuit has an output (110's output is connected to 140, Fig 2) , the multiphase power converter further comprises a controller (140, Fig 2) . The combination of Jang and Dusmez does not teach an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the current sense circuit;a comparator having a first input, a second input, and an output, the first input of the comparator configured to receive a threshold value, and the output of the comparator coupled to the control input of the ADC; anda counter having an output coupled to the second input of the comparator. Microchip teaches a conventional digital signal controller for use in a power converter including an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the current sense circuit ("the ADC is used for the measurement of feedback signals. This means that a trigger signal is required by the ADC peripheral to start the conversion operation.", pg3) ; a comparator having a first input, a second input, and an output, and the output of the comparator coupled to the control input of the ADC ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter, which is counting up or down. When the two values match, the trigger signal is generated and the ADC starts the sampling operation.", pg4) ; and a counter having an output coupled to the second input of the comparator ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter", pg4) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the digital signal controller in Jang, as taught by Microchip, as it provides the advantage of minimizing power draw and increasing converter efficiency by selectively triggering the ADC . 07-21-aia AIA Claim s 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Imamura (US 20240396455 A1) . Regarding Claim 10 , Jang teaches multiphase power converter (Fig 2) , comprising: a first phase circuit (102, Fig 2) having an input (input to 202, Fig 2) and an output (cathode of 232, Fig 2) ; a second phase circuit (104, Fig 2) having an input coupled to the input of the first phase circuit (input to 204 coupled to the input of 202, Fig 2) and having an output coupled to the output of the first phase circuit (cathode of 234 coupled to the cathode of 232, Fig 2) ; a first capacitor having first and second terminals (20, Fig 2) , the first terminal coupled to the outputs of the first and second phase circuits (20 coupled to the cathodes of 232 and 234, Fig 2) . Jang does not teach a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the outputs of the first and second phase circuits; and a resistor having first and second terminals, the first terminal of the resistor coupled to the second terminal of the first capacitor and the second terminal of the resistor coupled to [the] second terminal of the second capacitor. Imamura teaches a conventional current detection circuit for use in a power converter (Rs, Co1, Co2, Fig 3) including a first capacitor having first and second terminals (Co1, Fig 3) , a second capacitor having first and second terminals (Co2, Fig 3) , the first terminal of the second capacitor coupled to the outputs of the first and second phase circuits (Co1 & Co2 connected in parallel between 104 and 106, Fig 3) ; and a resistor having first and second terminals (Rs, Fig 3) , the first terminal of the resistor coupled to the second terminal of the first capacitor and the second terminal of the resistor coupled to second terminal of the second capacitor (Rs connected between the bottom terminals of Co1 & Co2, Fig 2) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current detection circuit in Jang, as taught by Imamura, as it provides the advantage of reducing the effects of EMI and improving the efficiency ([0048] of Imamura) . Regarding Claim 11 , the combination of Jang and Imamura teaches all of the limitations of Claim 10 above, and further teaches a damping circuit having first and second terminals, the first terminal of the damping circuit coupled to the first terminals of the first and second capacitors (the snubber circuit formed by Rsnb1 and Csnb1 and Rsnb1 is connected to the top terminals of Co1 and Co2 via Rsnb2/Csnb2 and via D1, Fig 8 of Imamura) . Regarding Claim 12 , the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the resistor is a first resistor, and wherein the damping circuit includes a second resistor coupled in series with a third capacitor (Rsnb1 and Csnb1 are connected in series, Fig 8 of Imamura) . Regarding Claim 13 , the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the second terminal of the damping circuit is coupled to the second terminal of the first capacitor (the bottom of Csnb1 is connected to the bottom of Co1 via Rs, Fig 8 of Imamura) . Regarding Claim 14 , the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the second terminal of the damping circuit is coupled to the second terminal of the second capacitor (the bottom of Csnb1 is connected to the bottom of Co2 via Rs, Fig 8 of Imamura) . 07-21-aia AIA Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Imamura (US 20240396455 A1), and further in view of Aoki (UUS 20240088815 A1) and Texas Instruments ("TMS320x2802x, 2803x Piccolo Enhanced PulseWidth Modulator (ePWM) Module") . Regarding Claim 15 , the combination of Jang and Imamura discloses all of the limitations of Claim 10 above. The combination of Jang and Imamura does not teach an amplifier coupled to the resistor and having an output; and a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the output of the amplifier to a digital signal. Aoki teaches a conventional measurement circuit for use in a power converter (Fig 1) including an amplifier coupled to the resistor and having an output (3 and 4, Fig 1). Aoki does not teach a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the output of the amplifier to a digital signal. Aoki does not teach Texas Instruments teaches a conventional ePWM module for use in a controller for a power converter (see Figs 5 & 12) including a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the output of the amplifier to a digital signal (the time base counter TBCTR counts up and down in "up-down-count mode" to generate a triangular waveform, Figs 5 & 12) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Aoki, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ePWM module in Jang, as taught by Texas Instruments, as it provides the advantage of converting analog current measurement into a digital value for high-precision digital control . 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Imamura (US 20240396455 A1), and further in view of Aoki (UUS 20240088815 A1) and Microchip ("Transition to Digital ADC") . Regarding Claim 16 , the combination of Jang and Imamura discloses all of the limitations of Claim 10 above. The combination of Jang and Imamura does not disclose an amplifier coupled to the resistor and having an output, the multiphase power converter further comprises a controller including:an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the amplifier;a comparator having a first input, a second input, and an output, the first input of the comparator configured to receive a threshold voltage, and the output of the comparator coupled to the control input of the ADC; anda counter having an output coupled to the second input of the comparator. Aoki teaches a conventional measurement circuit for use in a power converter (Fig 1) including an amplifier coupled to the resistor and having an output (3 and 4, Fig 1). Aoki does not teach a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the output of the amplifier to a digital signal. Microchip teaches a conventional digital signal controller for use in a power converter (see Fig 2) including a controller including (Fig 2) : an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the amplifier ("the ADC is used for the measurement of feedback signals. This means that a trigger signal is required by the ADC peripheral to start the conversion operation." The trigger is the control input and the feedback signals are the analog input from the amplifier of Aoki, pg3) ; a comparator having a first input, a second input, and an output, the first input of the comparator configured to receive a threshold voltage, and the output of the comparator coupled to the control input of the ADC ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter, which is counting up or down. When the two values match, the trigger signal is generated and the ADC starts the sampling operation." The register value corresponds to a voltage level in an analog carrier implementation, pg4) ; and a counter having an output coupled to the second input of the comparator ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter", pg4) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Aoki, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Microchip, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity . 07-21-aia AIA Claim s 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Schock (US 20160336892 A1), and further in view of Texas Instruments ("TMS320x2802x, 2803x Piccolo Enhanced PulseWidth Modulator (ePWM) Module") . Regarding Claim 17 , Jang teaches system, comprising: a first phase circuit having an input and an output (102, Fig 2) ; a second phase circuit having an input coupled to the input of the first phase circuit and an output coupled to the output of the first phase circuit (104 inputs/outputs connected to 102 inputs/outputs, Fig 2) ; a current sense circuit coupled to the first and second phase circuits and having an output (110 connected to 102 and 104, Fig 2) . Jang does not teach an analog-to-digital converter (ADC) having an analog input coupled to the output of the current sense circuit and a control input; a first comparator having first and second inputs and an output, the output coupled to the control input; a second comparator having third and fourth inputs and an output; and a first counter having an input and an output, the output coupled to the first and third inputs. Schock teaches a conventional ADC for use in a power converter (see Fig 2) including an analog-to-digital converter (ADC) having an analog input coupled to the output of the current sense circuit and a control input (processor 18's A/D samples current sensor 38 at PWM synchronized times, Figs 2-3, [0030-2]) ; Schock does not teach a first comparator having first and second inputs and an output, the output coupled to the control input; a second comparator having third and fourth inputs and an output; and a first counter having an input and an output, the output coupled to the first and third inputs. Texas Instruments teaches a conventional counter-compare module for use in a power converter (see Figs 3 & 15) including an analog-to-digital converter (ADC) having an analog input coupled to the output of the current sense circuit and a control input (ADC has control inputs/SOC triggers, Figs 41-42) ; a first comparator having first and second inputs and an output, the output coupled to the control input (Digital comparator A has inputs from TBCTR and counter-compare A register CMPA and an event output CTR=CMPA, Fig 15) ; a second comparator having third and fourth inputs and an output (Digital comparator B has inputs from TBCTR and counter-compare B register CMPB and an event output CTR=CMPB, Fig 15) ; and a first counter having an input and an output, the output coupled to the first and third inputs (Counter UP/DOWN inside of the Time-Base Submodule contains the TBCTR register that provides inputs to the Digital comparator A and Digital comparator B, Figs 5 & 15) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ADC in Jang, as taught by Schock, as it provides the advantage of minimizes power draw and increases converter efficiency by selectively triggering the ADC. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the counter-compare module in Jang, as taught by Texas Instruments, as it provides the Regarding Claim 18 , the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 17 above, and further teaches a third comparator having fifth and sixth inputs and an output, the output of the third comparator coupled to the control input (when a second ePWM module for a second phase is added, the second ePWM module will have its own Digital comparator A has inputs from TBCTR and counter-compare A register CMPA and an event output CTR=CMPA, Fig 64 & 15 of Texas Instruments) ; a fourth comparator having seventh and eighth inputs and an output (when a second ePWM module for a second phase is added, the second ePWM module will have its own Digital comparator B has inputs from TBCTR and counter-compare B register CMPB and an event output CTR=CMPB, Fig 64 & 15 of Texas Instruments) ; and a second counter having an input and an output, the output of the second counter coupled to the fifth and sixth inputs (when a second ePWM module for a second phase is added, the second ePWM module will have its own Counter UP/DOWN inside of the Time- Base Submodule contains the TBCTR register that provides inputs to the Digital comparator A and Digital comparator B, Figs 64, 5 & 15 of Texas Instruments) . Regarding Claim 19 , the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 18 above, and further teaches wherein the inputs of the first and second counters are configured to receive a clock signal (TBCLK is an input to the counters in each ePWM module, Fig 5, Table 4 of Texas Instruments) . Regarding Claim 20 , the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 18 above, and further teaches wherein the ADC has a digital output and is configured to generate a digital output signal at the digital output in response to a signal at its control input (the current sample is converted into a digital value for calculations in the processor, [0033] of Schock) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Ekbote (US 20140265895 A1) discloses a converter with a damping resonance circuit that includes a resistor and capacitor in series. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.C.C./Examiner, Art Unit 2838 /GARY L LAXTON/Primary Examiner, Art Unit 2838 5/28/2026 Application/Control Number: 18/735,396 Page 2 Art Unit: 2838 Application/Control Number: 18/735,396 Page 3 Art Unit: 2838 Application/Control Number: 18/735,396 Page 4 Art Unit: 2838 Application/Control Number: 18/735,396 Page 5 Art Unit: 2838 Application/Control Number: 18/735,396 Page 6 Art Unit: 2838 Application/Control Number: 18/735,396 Page 7 Art Unit: 2838 Application/Control Number: 18/735,396 Page 8 Art Unit: 2838 Application/Control Number: 18/735,396 Page 9 Art Unit: 2838 Application/Control Number: 18/735,396 Page 10 Art Unit: 2838 Application/Control Number: 18/735,396 Page 11 Art Unit: 2838 Application/Control Number: 18/735,396 Page 12 Art Unit: 2838 Application/Control Number: 18/735,396 Page 13 Art Unit: 2838 Application/Control Number: 18/735,396 Page 14 Art Unit: 2838 Application/Control Number: 18/735,396 Page 15 Art Unit: 2838 Application/Control Number: 18/735,396 Page 16 Art Unit: 2838 Application/Control Number: 18/735,396 Page 17 Art Unit: 2838 Application/Control Number: 18/735,396 Page 18 Art Unit: 2838
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