DETAILED ACTION
Response to Arguments
Applicant’s arguments, see pg 11 section “CLAIM OBJECTION” filed 2 Sep 2026, with respect to claim 10 have been fully considered and are persuasive. The objection of claim 10 has been withdrawn.
Applicant’s arguments with respect to the rejection of claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 9, 21-24 are objected to because of the following informalities:
Claim 9, line 7: the limitation “third input of the comparator” should be changed to --“fourth input of the comparator”--.
Claims 21-24: are objected to on the basis of their dependency on Claim 9.
Claim 21, lines 5-6: the limitation “of second phase terminal” should be changed to --“of the second phase terminal”--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2) and further in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems").
Regarding claim 1, Jang discloses a multiphase power converter (Fig 2), comprising: a first phase circuit (102, Fig 2) having a first input (input to 202, Fig 2), a first output (cathode of 232, Fig 2), a first terminal (anode of 232/collector of 212, Fig 2), and a second terminal (emitter of 212, Fig 2), the first input coupled to the first terminal (input to 202 coupled through the phase inductor to the switching node at the anode of 232/collector of 212, Fig 2), the first output coupled to a positive voltage terminal (cathode of 232 coupled to top rail of 30, Fig 2), the second terminal coupled to a first negative voltage terminal (emitter of 212 coupled to bottom rail of 30, Fig 2), and the first phase circuit comprising: a second transistor having a third current terminal, a fourth current terminal, and a second control terminal (212 has a collector, emitter, and base, Fig 2), the third current terminal coupled to the first terminal of the first phase circuit (the collector of 212 is connected to the switching node/anode of 232, Fig 2), and the fourth current terminal coupled to the second terminal of the first phase circuit (the emitter of 212 is connected to the bottom rail of 30, Fig 2); a second phase circuit (104, Fig 2) having a second input (input to 204, Fig 2), a second output (cathode of 234, Fig 2), and a third terminal (emitter of 214, Fig 2), the second input coupled to the first input (input to 204 coupled to the input of 202, Fig 2), the second output coupled to the positive voltage terminal (cathode of 234 coupled to top rail of 30, Fig 2), and the third terminal coupled to the first negative voltage terminal (emitter of 214 coupled to bottom rail of 30, Fig 2).
Jang does not disclose a first transistor having a first current terminal, a second current terminal, and a first control terminal, the first current terminal coupled to the first output of the first phase circuit, and the second current terminal coupled to the first terminal of the first phase circuit; a current sense circuit having first and second current sense terminals, the first current sense terminal coupled to the first negative voltage terminal and the second current sense terminal coupled to a second negative voltage terminal.
Canfield teaches a conventional transistor for use in a boost converter (see Fig 2) including a first transistor having a first current terminal, a second current terminal, and a first control terminal (SW2 with source, drain, and gate, where SW2 can be a transistor, Fig 2, Col 5[21-3]), the first current terminal coupled to the first output of the first phase circuit (SW2's source coupled to Vout, Fig 2), and the second current terminal coupled to the first terminal of the first phase circuit (SW2's drain connected to P1, which would occupy the position of Jang's diode 232, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the transistor in place of Jang’s diode, as taught by Canfield, as it provides the advantage of reduced conduction loss and higher efficiency.
Canfield does not teach a current sense circuit having first and second current sense terminals, the first current sense terminal coupled to the first negative voltage terminal and the second current sense terminal coupled to a second negative voltage terminal.
Dusmez teaches a conventional current sensing circuit for use in a multiphase power converter including a current sense circuit (Rshunt, Fig 3) having first and second current sense terminals (left and right terminals of Rshunt, Fig 3), the first current sense terminal coupled to the first negative voltage terminal (left terminal of Rshunt connected to the diode bridge rectifier at the input, Fig 3) and the second current sense terminal coupled to a second negative voltage terminal (right terminal of Rshunt connected to the output, Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current sensing circuit in Jang, as taught by Dusmez, as it provides the advantage of fewer sensors and lower cost (p5116 Col 2 last paragraph-p5117 Col 1 first paragraph of Dusmez).
Regarding Claim 7, the combination of Jang, Canfield, and Dusmez discloses all of the limitations of Claim 1 above, and further discloses wherein the current sense circuit includes a resistor having a first resistor terminal coupled to the first current sense terminal and a second resistor terminal coupled to the second current sense terminal (left and right terminals of current sense resistor Rshunt, Fig 3 of Dusmez).
Regarding claim 21, the combination of Jang, Canfield, and Dusmez discloses all of the limitations of Claim 1 above, and further discloses wherein the second phase circuit comprises: a fourth terminal (junction of 204, 214, and 234, Fig 2 of Jang) coupled to the second input of the second phase circuit (junction of 204, 214, and 234 coupled to input of 204, Fig 2 of Jang); a third transistor (SW2, Fig 2 of Canfield) having a fifth current terminal, a sixth current terminal, and a third control terminal (source, drain, and gate as SW2 can be a transistor, Fig 2 of Canfield), the fifth current terminal coupled to the second output of second phase terminal (source of SW2 coupled to P1, [which corresponds to junction of 204, 214, and 234 of Jang], Fig 2 of Canfield), and the sixth current terminal coupled to the fourth terminal of the second phase circuit (drain of SW2 coupled to P2, [which corresponds to cathode of 234 to top rail of 30 of Jang], Fig 2 of Canfield); and a fourth transistor (214, Fig 2 of Jang) having a seventh current terminal, an eighth current terminal, and a fourth control terminal (collector, emitter, and gate of 214 coupled to the junction of 204, 214, and 234, Fig 2 of Jang), the seventh current terminal coupled to the fourth terminal of the second phase circuit (collector of 214 coupled to the junction of 204, 214, and 234, Fig 2 of Jang), and the eighth current terminal coupled to the third terminal of the second phase circuit (emitter of 214 coupled to bottom rail of 30, Fig 2 of Jang).
Regarding claim 22, the combination of Jang, Canfield, and Dusmez discloses all of the limitations of Claim 21 above, and further discloses wherein the current sense circuit has a third output (112, Fig 2 of Jang), the third output of the current sense circuit configured to provide an analog signal (summed current info signal 112 sensed by current sensor 110, Fig 2 of Jang), wherein the multiphase power converter further comprises:
a plurality of transistor control terminals comprising the first control terminal (control terminal of SW2 first phase instance, Fig 2 of Canfield), the second control terminal (control terminal of SW2 second phase instance, Fig 2 of Canfield), the third control terminal, and the fourth control terminal of the first transistor, the second transistor, the third transistor (212 base, Fig 2 of Jang), and the fourth transistor (214 base, Fig 2 of Jang), respectively; and a controller having a third input and a plurality of output terminals (140, Fig 2 of Jang), the third input of the controller coupled to the third output of the current sense circuit (140 coupled to receive summed current info signal 112 from current sensor 110, Fig 2 of Jang), and the plurality of output terminals of the controller coupled to the plurality of transistor control terminals (140 controls 212, 214, and 216 with drive signals 222, 224, and 226 [and 3 more drive signals would be added to drive the transistors of Canfield], Fig 2 of Jang), wherein the controller, when operating in a first state, is configured to provide a plurality of first control signals to the plurality of transistor control terminals, the plurality of first control signals causing the first transistor and the fourth transistor to enter an ON state, and the plurality of first control signals causing the second transistor and the third transistor to enter an OFF state (timing of phases 102, 104 shown at 222, 224, where one phase’s active switch is ON while the other phase’s active switch is OFF at a given sampling instant of Fig 4 of Jang).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2) and further in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems") and Imamura (US 20240396455 A1).
Regarding Claim 2, the combination of Jang, Canfield, and Dusmez discloses all of the limitations of Claim 1 above.
The combination of Jang, Canfield, and Dusmez does not disclose a first capacitor having first and second capacitor terminals, the first capacitor terminal coupled to the positive voltage terminal, and the second capacitor terminal coupled to the first current sense terminal; and a second capacitor having third and fourth capacitor terminals, the third capacitor terminal coupled to the positive voltage terminal, and the fourth capacitor terminal coupled to the second current sense terminal.
Imamura teaches a conventional current detection circuit for use in a power converter (Rs, Co1, Co2, Fig 3) including a first capacitor having first and second terminals, the first capacitor terminal coupled to the positive voltage terminal, and the second capacitor terminal coupled to the first current sense terminal (Co1 connected to Vout and top terminal of Rs, Fig 3); and a second capacitor having third and fourth capacitor terminals, the third capacitor terminal coupled to the positive voltage terminal, and the fourth capacitor terminal coupled to the second current sense terminal (Co2 connected to Vout and bottom terminal of Rs, Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current detection circuit in Jang, as taught by Imamura, as it provides the advantage of reducing the effects of EMI and improving the efficiency ([0048] of Imamura).
Claims 8 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2) and further in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems") and Schock (US 20160336892 A1).
Regarding Claim 8, the combination of Jang, Canfield and Dusmez teaches all of the limitations of Claim 1 above.
The combination of Jang, Canfield and Dusmez does not teach a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal has fallen below a threshold, and convert an analog signal from the current sense circuit to a digital signal.
Schock teaches a conventional controller for use in a power converter (see Fig 2) including a controller configured to generate a carrier signal (18 controls the PWM by generating carrier 40, which is the output of an up/down counter, Figs 2 & 4, [0032]), determine that a magnitude of the carrier signal has fallen below a threshold (" the center point represents zero, with progressively larger counts left and right from that center point.", Fig 4, [0032]), and convert an analog signal from the current sense circuit to a digital signal ("Reference numerals 48 and 50 illustrate analog/digital (a/d) sample times, which are defined herein as points during the duty cycle when the current is sampled from the single shunt or current sensor 38.", Fig 4, [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the digital signal controller in Jang, as taught by Schock, as it provides the advantage of minimizing power draw and increasing converter efficiency by selectively triggering the ADC.
Regarding claim 23, the combination of Jang, Canfield, and Dusmez discloses all of the limitations of Claim 22 above.
The combination of Jang, Canfield, and Dusmez does not disclose wherein the controller, when operating in the first state, is further configured to convert the analog signal provided by the third output of the current sense circuit to a digital signal.
Schock teaches a conventional controller for a switching power converter (see Fig 4-6) wherein the controller, when operating in the first state, is further configured to convert the analog signal provided by the third output of the current sense circuit to a digital signal (processor 18, a digital signal processor, samples the analog output of current sensor 38 at a/d sample times, 48, 50, Fig 4-6, [0022, 0030, 0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the digital signal controller in Jang, as taught by Schock, as it provides the advantage of enabling digital signal processing and comparison of the sensed current value by the controller.
Regarding claim 24, the combination of Jang, Canfield, Dusmez, and Schock discloses all of the limitations of Claim 23 above, and further discloses wherein the controller, when operating in the first state, is configured to: determine a sensing current flowing across the first negative voltage terminal and the second negative voltage terminal based on the digital signal (current controller 120/phase current calculating block 150 determines phase current info I1CALC, I2CALC, I3CALC for phases 102, 104, 106 from the summed current info signal 112 sensed across the negative rails of DC link 17, Fig 2-3 of Jang); in response to determining the sensing current, modify the plurality of first control signals (“the current controller utilizes…the current balancing signals to modify the pulse width modulated (PWM) duty cycle of the gate drive signals”, Fig 2-3, [0031] 3 of Jang); and in response to modifying the plurality of first control signals, adjust a first current and a second current, the first current flowing between the first input and the first terminal of the first phase circuit, and the second current flowing between the second input and the fourth terminal of the second phase circuit (“the controller 120 stabilizes and balances the currents of the phases 102, 104, 106 to provide regulated, stable current”, Fig 2-3, [0033] 3 of Jang).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2) and further in view of Dusmez ("A Modified Dual-Output Interleaved PFC Converter Using Single Negative Rail Current Sense for Server Power Systems") and Microchip ("Transition to Digital ADC").
Regarding Claim 9, the combination of Jang, Canfield and Dusmez teaches all of the limitations of Claim 1 above, and further teaches wherein the current sense circuit has a third output (110's output is connected to 140, Fig 2), and the multiphase power converter further comprises a controller (140, Fig 2).
The combination of Jang, Canfield and Dusmez does not teach a an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the current sense circuit; a comparator having a first input, a second input, and an output, the first input of the comparator configured to receive a threshold value, and the output of the comparator coupled to the control input of the ADC; and a counter having an output coupled to the second input of the comparator.
Microchip teaches a conventional digital signal controller for use in a power converter including an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the third output of the current sense circuit ("the ADC is used for the measurement of feedback signals. This means that a trigger signal is required by the ADC peripheral to start the conversion operation.", pg3); a comparator having a third input, a fourth input, and a fourth output, the third input of the comparator configured to receive a threshold value, and the fourth output of the comparator coupled to the control input of the ADC ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter, which is counting up or down. When the two values match, the trigger signal is generated and the ADC starts the sampling operation.", pg4); and a counter having a fifth output coupled to the fourth input of the comparator ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter", pg4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the digital signal controller in Jang, as taught by Microchip, as it provides the advantage of minimizing power draw and increasing converter efficiency by selectively triggering the ADC.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2), and further in view of Imamura (US 20240396455 A1).
Regarding Claim 10, Jang discloses a multiphase power converter (Fig 2), comprising: a first phase circuit (102, Fig 2) having a first input (input to 202, Fig 2) and a first output (cathode of 232, Fig 2), the first phase circuit comprising: a second transistor having a third current terminal and a fourth current terminal (212 has collector and emitter, Fig 2), the third current terminal coupled to the second current terminal of the first transistor (212’s collector coupled to the switching node shared with the [drain of SW2 of Canfield], Fig 2); a second phase circuit (104, Fig 2) having a second input (input to 204, Fig 2) and a second output (cathode of 234, Fig 2), the second input coupled to the first input of the first phase circuit (input to 204 coupled to the input of 202, Fig 2), and the second output coupled to the first output of the first phase circuit (cathode of 234 coupled to the cathode of 232, Fig 2); a first capacitor having first and second capacitor terminals (20, Fig 2), the first capacitor terminal coupled to the first output of the first phase circuit and the second output of the second phase circuit (20 coupled to the cathodes of 232 and 234, Fig 2), and the first and second capacitor terminals of the first capacitor coupled to the first current terminal of the first transistor and the fourth current terminal of the second transistor, respectively (top of 20 coupled to the [SW2 of Canfield]/cathode of 232, and bottom of 20 coupled to emitter of 212, Fig 2).
Jang does not disclose a first transistor having a first current terminal and a second current terminal, the first current terminal coupled to the first output of the first phase circuit, and the second current terminal coupled to the first input of the first phase circuit; a second capacitor having third and fourth capacitor terminals, the third capacitor terminal of the second capacitor coupled to the first output of the first phase circuit and the second output of the second phase circuit; and a resistor having first and second resistor terminals, the first resistor terminal of the resistor coupled to the second capacitor terminal of the first capacitor, and the second resistor terminal of the resistor coupled to the fourth capacitor terminal of the second capacitor.
Canfield teaches a conventional transistor for use in a boost converter (see Fig 2) including a first transistor having a first current terminal and a second current terminal (SW2 with source and drain, where SW2 can be a transistor, Fig 2, Col 5[21-3]), the first current terminal coupled to the first output of the first phase circuit (SW2's source coupled to Vout, Fig 2), and the second current terminal coupled to the first input of the first phase circuit (SW2's drain connected to P1, which would occupy the position of Jang's diode 232, Fig 2).
Canfield does not teach a second capacitor having third and fourth capacitor terminals, the third capacitor terminal of the second capacitor coupled to the first output of the first phase circuit and the second output of the second phase circuit; and a resistor having first and second resistor terminals, the first resistor terminal of the resistor coupled to the second capacitor terminal of the first capacitor, and the second resistor terminal of the resistor coupled to the fourth capacitor terminal of the second capacitor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current sensing circuit in Jang, as taught by Canfield, as it provides the advantage of reduced conduction loss and higher efficiency.
Imamura teaches a conventional current detection circuit for use in a multiphase power converter (see Fig 3) including a first capacitor having first and second capacitor terminals (Co1, Fig 3), a second capacitor having third and fourth capacitor terminals (Co2, Fig 3), the third capacitor terminal of the second capacitor coupled to the first output of the first phase circuit and the second output of the second phase circuit (Co1 & Co2 connected in parallel between 104 and 106, Fig 3); and a resistor having first and second resistor terminals (Rs, Fig 3), the first resistor terminal of the resistor coupled to the second capacitor terminal of the first capacitor and the second resistor terminal of the resistor coupled to the fourth capacitor terminal of the second capacitor (Rs connected between the bottom terminals of Co1 & Co2, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current detection circuit in Jang, as taught by Imamura, as it provides the advantage of reducing the effects of EMI and improving the efficiency ([0048] of Imamura).
Regarding Claim 11, the combination of Jang and Imamura teaches all of the limitations of Claim 10 above, and further teaches a damping circuit having first and second damping terminals, the first damping terminal of the damping circuit coupled to the first capacitor terminal of the first capacitor and the third capacitor terminal of the second capacitor (the snubber circuit formed by Rsnb1 and Csnb1 and Rsnb1 is connected to the top terminals of Co1 and Co2 via Rsnb2/Csnb2 and via D1, Fig 8 of Imamura).
Regarding Claim 12, the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the resistor is a first resistor, and wherein the damping circuit includes a second resistor coupled in series with a third capacitor (Rsnb1 and Csnb1 are connected in series, Fig 8 of Imamura).
Regarding Claim 13, the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the second damping terminal of the damping circuit is coupled to the second capacitor terminal of the first capacitor (the bottom of Csnb1 is connected to the bottom of Co1 via Rs, Fig 8 of Imamura).
Regarding Claim 14, the combination of Jang and Imamura teaches all of the limitations of Claim 11 above, and further teaches wherein the second damping terminal of the damping circuit is coupled to the fourth capacitor terminal of the second capacitor (the bottom of Csnb1 is connected to the bottom of Co2 via Rs, Fig 8 of Imamura).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2), and further in view of Imamura (US 20240396455 A1), Aoki (US 20240088815 A1) and Texas Instruments ("TMS320x2802x, 2803x Piccolo Enhanced PulseWidth Modulator (ePWM) Module").
Regarding Claim 15, the combination of Jang, Canfield, and Imamura discloses all of the limitations of Claim 10 above.
The combination of Jang, Canfield, and Imamura does not teach an amplifier coupled to the resistor and having a third output; and a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the third output of the amplifier to a digital signal.
Aoki teaches a conventional measurement circuit for use in a power converter (Fig 1) including an amplifier coupled to the resistor and having a third output (3 and 4, Fig 1).
Aoki does not teach a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the output of the amplifier to a digital signal. Aoki does not teach
Texas Instruments teaches a conventional ePWM module for use in a controller for a power converter (see Figs 5 & 12) including a controller configured to generate a carrier signal, determine that a magnitude of the carrier signal equals or is below a threshold, and convert an analog signal from the third output of the amplifier to a digital signal (the time base counter TBCTR counts up and down in "up-down-count mode" to generate a triangular waveform, Figs 5 & 12).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Aoki, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ePWM module in Jang, as taught by Texas Instruments, as it provides the advantage of converting analog current measurement into a digital value for high-precision digital control.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Canfield (US 8063615 B2), and further in view of Imamura (US 20240396455 A1), Aoki (US 20240088815 A1) and Microchip ("Transition to Digital ADC").
Regarding Claim 16, the combination of Jang, Canfield, and Imamura discloses all of the limitations of Claim 10 above.
The combination of Jang, Canfield, and Imamura does not disclose an amplifier coupled to the resistor and having a third output, the multiphase power converter further comprises a controller including: an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the third output of the amplifier; a comparator having a third input, a fourth input, and a fourth output, the third input of the comparator configured to receive a threshold voltage, and the fourth output of the comparator coupled to the control input of the ADC; and a counter having a fifth output coupled to the third input of the comparator.
Aoki teaches a conventional measurement circuit for use in a power converter (Fig 1) including an amplifier coupled to the resistor and having a third output (3 and 4, Fig 1).
Aoki does not teach the multiphase power converter further comprises a controller including: an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the output of the amplifier; a comparator having a third input, a fourth input, and a fourth output, the third input of the comparator configured to receive a threshold voltage, and the fourth output of the comparator coupled to the control input of the ADC; and a counter having a fifth output coupled to the third input of the comparator.
Microchip teaches a conventional digital signal controller for use in a power converter (see Fig 2) including the multiphase power converter further comprises a controller including: an analog-to-digital converter (ADC) having an analog input and a control input, the analog input coupled to the third output of the amplifier ("the ADC is used for the measurement of feedback signals. This means that a trigger signal is required by the ADC peripheral to start the conversion operation." The trigger is the control input and the feedback signals are the analog input from the amplifier of Aoki, pg3); a comparator having a third input, a fourth input, and a fourth output, the third input of the comparator configured to receive a threshold voltage, and the output of the comparator coupled to the control input of the ADC ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter, which is counting up or down. When the two values match, the trigger signal is generated and the ADC starts the sampling operation." The register value corresponds to a voltage level in an analog carrier implementation, pg4); and a counter having a fifth output coupled to the third input of the comparator ("The comparator continuously compares the value of the ADC Trigger register with the value of the counter", pg4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Aoki, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the amplifier in Jang, as taught by Microchip, as it provides the advantage of amplifying the value read over the resistor to improve the measurement resolution and improve the converter's noise immunity.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20100019702 A1) in view of Schock (US 20160336892 A1), and further in view of Texas Instruments ("TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module").
Regarding Claim 17, Jang teaches system, comprising: a first phase circuit having a first input and a first output (102, Fig 2); a second phase circuit having a second input coupled to the first input of the first phase circuit and a second output coupled to the first output of the first phase circuit (104 inputs/outputs connected to 102 inputs/outputs, Fig 2); a current sense circuit having a third output, wherein the current sense circuit is coupled to the first and second phase circuits (110 connected to 102 and 104, Fig 2).
Jang does not teach an analog-to-digital converter (ADC) having an analog input and a control input, wherein the analog input is coupled to the third output of the current sense circuit; a controller, the controller comprising: a first comparator having a third input, and a fourth input and a fourth output, wherein the output is coupled to the control input of the ADC; a second comparator having a fifth input, and a sixth input, and a fifth output, wherein the fifth output is coupled to the control input of the ADC; a first counter having a seventh input and a sixth output, wherein the sixth output is coupled to the third input of the first comparator, and wherein the first counter is configured to provide a first carrier signal to the first comparator; and a second counter having an eighth input and a seventh output, wherein the seventh output is coupled to the fifth input of the second comparator, wherein the second counter is configured to provide a second carrier signal to the second comparator, wherein the first carrier signal and the second carrier signal have a non-zero phase offset, wherein the first comparator and the second comparator are configured to cause the ADC to convert an analog signal from the analog input to a digital output signal at a plurality of first times and a plurality of second times, wherein the plurality of first times correspond to the first carrier signal reaching a first threshold value, and wherein the plurality of second times correspond to the second carrier signal reaching a second threshold value.
Schock teaches a conventional ADC for use in a power converter (see Fig 2) including an analog-to-digital converter (ADC) having an analog input coupled to the third output of the current sense circuit (processor 18's A/D samples current sensor 38 at PWM synchronized times, Figs 2-3, [0030-2]);
Schock does not teach a control input of the ADC; a controller, the controller comprising: a first comparator having a third input, and a fourth input and a fourth output, wherein the output is coupled to the control input of the ADC; a second comparator having a fifth input, and a sixth input, and a fifth output, wherein the fifth output is coupled to the control input of the ADC; a first counter having a seventh input and a sixth output, wherein the sixth output is coupled to the third input of the first comparator, and wherein the first counter is configured to provide a first carrier signal to the first comparator; and a second counter having an eighth input and a seventh output, wherein the seventh output is coupled to the fifth input of the second comparator, wherein the second counter is configured to provide a second carrier signal to the second comparator, wherein the first carrier signal and the second carrier signal have a non-zero phase offset, wherein the first comparator and the second comparator are configured to cause the ADC to convert an analog signal from the analog input to a digital output signal at a plurality of first times and a plurality of second times, wherein the plurality of first times correspond to the first carrier signal reaching a first threshold value, and wherein the plurality of second times correspond to the second carrier signal reaching a second threshold value.
Texas Instruments teaches a conventional counter compare module for use in a power converter (see Figs 3 & 15) including an analog-to-digital converter (ADC) having an analog input and a control input, wherein the analog input is coupled to the third output of the current sense circuit (ADC has control inputs/SOC triggers, Figs 41-42); and a controller, the controller comprising: a first comparator having a third input, a fourth input, and a fourth output, wherein the fourth output is coupled to the control input of the ADC (Digital comparator A has inputs from TBCTR and counter-compare A register CMPA and an event output CTR=CMPA, Fig 15); a second comparator having a fifth input, a sixth input and a fifth output, wherein the fifth output is coupled to the control input of the ADC (Digital comparator B has inputs from TBCTR and counter-compare B register CMPB and an event output CTR=CMPB, Fig 15); and a first counter having a seventh input and a sixth output, wherein the sixth output is coupled to the third input of the first comparator, and wherein the first counter is configured to provide a first carrier signal to the first comparator (Counter UP/DOWN inside of the Time-Base Submodule contains the TBCTR register that provides inputs to the Digital comparator A and Digital comparator B, Figs 5 & 15); and a second counter having an eighth input and a seventh output, wherein the seventh output is coupled to the fifth input of the second comparator, wherein the second counter is configured to provide a second carrier signal to the second comparator (when a second ePWM module for a second phase is added, the second ePWM module will have its own Counter UP/DOWN inside of the Time-Base Submodule containing a TBCTR register that provides an input to that module’s own Digital comparator A and Digital Comparator B, Figs 64, 5, and 15), wherein the first carrier signal and the second carrier signal have a non-zero phase offset (each ePWM module’s time-base counter (TBCTR) may be automatically loaded with that module’s own Time-Base Phase Register (TBPHS) value upon a sync event (TBCTL[PHSEN]/EPWMxSYNCI) and “[l]ead or lag phase control can be added to the waveforms generated by different ePWM modules to synchronize them”, establishing a non-zero phase offset between the carrier signal of a first ePWM module and the carrier signal of a second, phase-shifted ePWM module, p28-30), wherein the first comparator and the second comparator are configured to cause the ADC to convert an analog signal from the analog input to a digital output signal at a plurality of first times and a plurality of second times, wherein the plurality of first times correspond to the first carrier signal reaching a first threshold value, and wherein the plurality of second times correspond to the second carrier signal reaching a second threshold value (Digital Comparator A generates event output CTR=CMPA when the first ePWM modules’ TBCTR reaches counter-compare register CMPA, and the second, phase-offset ePWM modules own TBCTR reaches its own counter-compare register CMPA, each event output providing a control-input/SOC trigger causing the ADC to convert at that carrier-threshold-crossing time, Figs 15, 41-42).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ADC in Jang, as taught by Schock, as it provides the advantage of minimizes power draw and increases converter efficiency by selectively triggering the ADC.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the counter compare module in Jang, as taught by Texas Instruments, as it provides the advantage of interleaving each phase’s current sampling window relative to the other phase’s carrier signal.
Regarding Claim 18, the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 17 above, and further teaches wherein the controller further comprises: a third comparator having a ninth input, a tenth input and an eighth output, the ninth input of the third comparator coupled to the sixth output of the first counter, and the eighth output of the third comparator coupled to a second control input of the first phase circuit (when a second ePWM module for a second phase is added, the second ePWM module will have its own Digital comparator A has inputs from TBCTR and counter-compare A register CMPA and an event output CTR=CMPA, Fig 64 & 15 of Texas Instruments); and a fourth comparator having an eleventh input, and a twelfth input and a ninth output, the eleventh input of the fourth comparator coupled to the seventh output of the second counter, and the ninth output of the fourth comparator coupled to a third control input of the second phase circuit (when a second ePWM module for a second phase is added, the second ePWM module will have its own Digital comparator B has inputs from TBCTR and counter-compare B register CMPB and an event output CTR=CMPB, Fig 64 & 15 of Texas Instruments);
and a second counter having an input and an output, the output of the second counter coupled to the fifth and sixth inputs (when a second ePWM module for a second phase is added, the second ePWM module will have its own Counter UP/DOWN inside of the Time-Base Submodule contains the TBCTR register that provides inputs to the Digital comparator A and Digital comparator B, Figs 64, 5 & 15 of Texas Instruments).
Regarding Claim 19, the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 18 above, and further teaches wherein the inputs of the first and second counters are configured to receive a clock signal (TBCLK is an input to the counters in each ePWM module, Fig 5, Table 4 of Texas Instruments).
Regarding Claim 20, the combination of Jang, Schock, and Texas Instruments discloses all of the limitations of Claim 18 above, and further teaches wherein the ADC has a digital output and is configured to generate a digital output signal at the digital output in response to a signal at its control input (the current sample is converted into a digital value for calculations in the processor, [0033] of Schock).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 9/18/2026
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