Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1 – 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 13 of U.S. Patent No. 11,640,265.
US Application Number 18/735,412
US Patent Number 11,640,265
(Claim 1)
An apparatus for processing received data, the apparatus comprising: a decompression circuit configured to decompress a compressed code to decode a N-bit string, wherein N represents an integer greater than 1, and K represents an integer from 1 to N, a bit value of a K-th bit of the N-bit string is determined based on the compressed code and bit values for each bit up to (K−1), and the decompression circuit is configured to calculate a plurality of candidate bit values for each bit of the N-bit string.
(Claim 1)
An apparatus for processing received data, the apparatus comprising: a circuit configured to receive an input code compressed based on a range code; and a plurality of decompression circuits configured to decompress a part or all of the input code to decode a bit string, wherein a bit value of a bit of the input code is decoded based on a bit history of a bit before the bit, and wherein the plurality of decompression circuits are configured to: calculate a plurality of candidate bit values for each bit of the bit string based on a plurality of possible bit histories of the bit before the bit, and repeatedly select a correct bit value of the bit from the plurality of candidate bit values based on a correct bit history of the bit before the bit to decode the bit string.
(Claim 2)
The apparatus according to claim 1, wherein the decompression circuit is configured to select a bit value of K-th bit from the candidate bit values based on the compressed code and bit values determined up to (K−1)-th bit.
(Claim 4)
The apparatus according to claim 1, wherein the plurality of decompression circuits are configured to store probability values of a bit value appearing in accordance with the bit history, and select and update a probability value corresponding to a bit history based on correct bits constituting the decoded bit string from the stored probability values.
(Claim 3)
The apparatus according to claim 2, wherein the decompression circuit is configured to repeatedly select the bit value of the K-th bit.
(claim 1)
An apparatus for processing received data, the apparatus comprising: a circuit configured to receive an input code compressed based on a range code; and a plurality of decompression circuits configured to decompress a part or all of the input code to decode a bit string, wherein a bit value of a bit of the input code is decoded based on a bit history of a bit before the bit, and wherein the plurality of decompression circuits are configured to: calculate a plurality of candidate bit values for each bit of the bit string based on a plurality of possible bit histories of the bit before the bit, and repeatedly select a correct bit value of the bit from the plurality of candidate bit values based on a correct bit history of the bit before the bit to decode the bit string.
(Claim 4)
The apparatus according to claim 1, wherein the decompression circuit is configured to calculate the plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit values for each bit up to (K−1) in parallel for a plurality of bits.
(Claim 3)
The apparatus according to claim 1, wherein the plurality of decompression circuits are configured to calculate the plurality of candidate bit values in parallel for a plurality of bits.
(Claim 5)
The apparatus according to claim 4, wherein, in calculating the plurality of candidate bit values in parallel for the plurality of bits, a number of the candidate bit values for a (K+1)-th bit is twice a number of the K-th bit.
(Claim 3)
The apparatus according to claim 1, wherein the plurality of decompression circuits are configured to calculate the plurality of candidate bit values in parallel for a plurality of bits.
(Claim 6)
The apparatus according to claim 1, wherein the decompression circuit is configured to store probability values of a bit value appearing in accordance with the bit values for each bit up to (K−1), and select and update a probability value corresponding to bit values for each bit up to (K−1) based on correct bits constituting the decoded N-bit string from the stored probability values.
(Claim 4)
The apparatus according to claim 1, wherein the plurality of decompression circuits are configured to store probability values of a bit value appearing in accordance with the bit history, and select and update a probability value corresponding to a bit history based on correct bits constituting the decoded bit string from the stored probability values.
(Claim 7)
The apparatus according to claim 1, wherein in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit values for each bit up to (K−1) is performed to divide the division target range into two sections, and each of 2{circumflex over ( )}(K−1) candidate bit values is determined from a section specified by a sub-code among the two sections of the K-th bit in the compressed code.
(Claim 5)
The apparatus according to claim 1, wherein the bit string is an N-bit string, the bit is a K-th bit, N represents an integer greater than 1, and K represents an integer from 1 to N, and wherein, in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit histories is performed to divide the division target range into two sections, and each of 2{circumflex over ( )}(K−1) candidate bit values is determined from a section specified by a sub-code among the two sections of the K-th bit in the input code.
(Claim 8)
The apparatus according to claim 1, wherein when the number of bits to be decoded from the entire compressed code is larger than a preset maximum value, the decompression circuit performs decoding of a bit string based on a part of the compressed code for a plurality of cycles.
(Claim 6)
The apparatus according to claim 1, wherein, when the number of bits to be decoded from the entire input code is larger than a preset maximum value, the plurality of decompression circuits perform decoding of a bit string based on a part of the input code for a plurality of cycles.
(Claim 9)
The apparatus according to claim 8, wherein in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the K-th bit is a section corresponding to a correct bit value of the K-th bit in an immediately preceding cycle.
(Claim 7)
The apparatus according to claim 6, wherein, in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the bit is a section corresponding to a correct bit value of the bit in an immediately preceding cycle.
(Claim 10)
A storage system, comprising: an interface configured to receive a request from a host; and a controller configured to execute writing of data to a storage drive and reading of data from the storage drive in accordance with a command from the host, wherein the controller includes the decompression circuit according to claim 1, the controller is configured such that, in accordance with a read command from the host, the compressed code transferred from the storage drive is decoded by the decompression circuit to generate read data, and the read data is replied to the host via the interface.
(Claim 8)
A storage system, comprising: an interface configured to receive a request from a host; and a controller configured to execute writing of data to a storage drive and reading of data from the storage drive in accordance with a command from the host, wherein the controller includes the plurality of decompression circuits according to claim 1, wherein the controller is configured such that, in accordance with a read command from the host, the input code transferred from the storage drive is decoded by the plurality of decompression circuits to generate read data, and wherein the read data is replied to the host via the interface.
(Claim 11)
The storage system according to claim 10, wherein the decompression circuit is configured to store probability values of a bit value appearing in accordance with the bit values for each bit up to (K−1), and select and update a probability value of each of correct bit values constituting the decoded N-bit string from the stored probability values.
(Claim 9)
The storage system according to claim 8, wherein the plurality of decompression circuits are configured to store probability values of a bit value appearing in accordance with the bit history, and select and update a probability value of each of correct bit values constituting the decoded N-bit string from the stored probability values.
(Claim 12)
The storage system according to claim 10, wherein in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit values for each bit up to (K−1) is performed to divide the division target range into two sections, and a candidate bit value is determined from each of 2{circumflex over ( )}(K−1) sections for a sub-code of the K-th bit in the compressed code.
(Claim 10)
The storage system according to claim 8, wherein the bit string is an N-bit string, the bit is a K-th bit, N represents an integer greater than 1, and K represents an integer from 1 to N, and wherein, in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit histories is performed to divide the division target range into two sections, and a candidate bit value is determined from each of 2{circumflex over ( )}(K−1) sections for a sub-code of the K-th bit in the input code.
(Claim 13)
The storage system according to claim 10, wherein when the number of bits to be decoded from the entire compressed code is larger than a preset maximum value, the decompression circuit performs decoding of a bit string based on a part of the compressed code for a plurality of cycles.
(Claim 11)
The storage system according to claim 8, wherein, when the number of bits to be decoded from the entire input code is larger than a preset maximum value, the plurality of decompression circuits perform decoding of a bit string based on a part of the input code for a plurality of cycles.
(Claim 14)
The storage system according to claim 13, wherein in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the K-th bit is a section corresponding to a correct bit value of the K-th bit in an immediately preceding cycle.
(Claim 12)
The storage system according to claim 11, wherein, in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the bit is a section corresponding to a correct bit value of the bit in an immediately preceding cycle.
(Claim 15)
A method for processing received data in an apparatus including a decompression circuit, the method comprising: decompressing a part or all of a compressed code to decode a N-bit string by the decompression circuit, wherein N represents an integer greater than 1, and K represents an integer from 1 to N, wherein a bit value of a K-th bit of the N-bit string is determined based on the compressed code and bit values for each bit up to (K−1), and wherein the decompressing includes calculating a plurality of candidate bit values for each bit of the N-bit string, and selecting a bit value of K-th bit from the candidate bit values based on the compressed code and bit values determined up to (K−1)-th bit.
(Claim 13)
A method for processing received data in an apparatus including a plurality of decompression circuits, the method comprising: receiving an input code compressed based on a range code; and decompressing a part or all of the input code to decode a bit string by the plurality of decompression circuits, wherein a bit value of a bit of the input code is decoded based on a bit history of a bit before the bit, and wherein the decompressing includes calculating a plurality of candidate bit values for each bit of the bit string based on a plurality of possible bit histories of the bit before the bit, and repeatedly select a correct bit value of the bit from the plurality of candidate bit values based on a correct bit history of the bit before the bit to decode the bit string.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patents make obvious the claims of the pending application in that the limitations claimed in the pending application are found in the issued patents even though they are not necessarily presented in the same order as those in the issued patents. “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845