DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In reference to claim 6, the claim requires “further comprising a third interface
disposed on the first one of the plurality of side surfaces” The structure of the first one is unclear, as a result it is unclear what it means disposed on the first one of a plurality of surfaces, rendering the meaning of claim 6 indefinite.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is that the second substrate contains dielectric material in contact with the front surface (113) of the substrate 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 5909055 A – hereinafter Yamashita) in view of Chen (US 9107290 B1) and Geissler at al. (US 20180331080 A1 – hereinafter Geissler).
Regarding independent claim 1, Yamashita teaches:
A packaged device ([4:6-8] – “FIG. 8 shows by a side view a second
example of the chip package device of FIGS. 4 to 6 mounted on a printed circuit hoard” – hereinafter ‘PD’), comprising:
a chip module (31 – Fig. 6 – [4:58-59] – “IC chip 31 is brought onto the package substrate 33”);
a package body (51 – Fig. 6 – [5:56-58] – “a mass of resin 51 is formed to cover the IC chip 31 and a marginal or peripheral area of the package substrate 33” – this is interpreted as a package body) configured to package the chip module (31) and comprising:
a bottom surface (Fig. 7 annotated, see below – hereinafter ‘Bottom’) configured to face a circuit board (39 – Fig. 7 – [6:3] – “printed circuit board 39”); and
a plurality of side surfaces;
a first interface (35 – Fig. 7 – [5:67] – “electrodes 35” – this is an interface) configured to connect to the circuit board (39), wherein the first interface (35) is disposed on the bottom surface (Bottom) or on a part that is of at least a first one of the plurality of side surfaces and that is proximate to the bottom surface (Bottom – Fig. 7 shows this); and
a second interface configured to connect to a surface-mount device,
wherein the second interface is disposed on at least a second one of the plurality of side surfaces, and
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface.
Yamashita does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Chen teaches
a second interface (Fig. 1A annotated, see below – [18 = 6:27] – “conducting terminal 110” – Fig. 1A shows element on the top and bottom faces, hereinafter 110-2) configured to connect to a surface-mount device (Fig. 1A annotated, see below – this is interpreted as a stacked package, hereinafter ‘SMD’),
wherein the second interface (110) is disposed on at least a second one of the plurality of side surfaces.
PNG
media_image1.png
578
1098
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second interface structure as taught by Chen into Yamashita.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results [2:40-42] – “a package structure for packaging electronic components in high density integration by using a surface mount technology (SMT).”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Yamashita and Chen do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Geissler teaches
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface ([0077] – “tall components 120 (second electrical device components B) are placed with adhesive tapes 720 on the bottom side” – Fig. 7d shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the side structure as taught by Geissler into Yamashita and Chen.
An ordinary artisan would have been motivated to use the known technique of Geissler in the manner set forth above to produce the predictable results [0002] – “For example, System in Package (SiP) integration is a trend in the semiconductor packaging industry to reduce the system form factor, costs and increase performance. Some approaches are side by side (SbS) die arrangements, 3D die stacking (3D), package on package (PoP) stacking and integration of passive components (integrated passive devices IPDs and surface mounted devices SMDs) into packages.
[0003] For example, the low z-height requirements for PoP (e.g. 1.0 mm) can limit the possibilities for integration of standard components like SMDs or MEMs (micro-electro-mechanical systems). Only flat components especially designed for system integration may be usable but that reduces flexibility and increases costs.”
Regarding claim 3, Yamashita as modified by Chen and Geissler, teaches claim 1 from which claim 3 depends. Yamashita further teaches
the packaged device (PD).
Yamashita and Geissler do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Chen teaches
wherein the second interface (110) is further configured to transmit a
second type signal, and wherein the second type signal comprises at least one of a voltage signal transmitted between the packaged device and the surface-mount device (SMD) or a current signal transmitted ([11:52-61] – “the first conducting terminals 110 of the first electronic component 11 and the second conductive layer 13 are isolated from the heat dissipation device 31. In addition, after the heat is transferred to the second conductive layer 13, the heat may be further transferred to the heat dissipation device 31 through the insulating and heat-dissipating layer 30. More especially, since the package structure 3 can withstand a high voltage, the possibility of causing current leakage and high-voltage spark will be minimized” – this describes a voltage or current signal transmitted via 110) between the packaged device and the surface-mount device (SMD).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second interface and signal structure as taught by Chen into Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 4, Yamashita as modified by Chen and Geissler, teaches claim 1 from which claim 4 depends. Yamashita and Geissler do not expressly disclose the limitations of claim 4.
However, in an analogous art, Chen teaches
further comprising a third interface (40 – Fig. 4 – [12:17-20] – “The package
structure 4 can be fixed and connected with a system circuit board by inserting the pin 40 into the system circuit board and welding the pin 40 on the system circuit board”)
disposed on at least a third one of the plurality of side surfaces (Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third interface structure as taught by Chen into Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 5, Yamashita as modified by Chen and Geissler, teaches claim 4 from which claim 5 depends. Yamashita and Geissler do not expressly disclose the limitations of claim 5.
However, in an analogous art, Chen teaches
wherein the third interface (40) is configured to:
connect to the circuit board (40 – Fig. 4 – [12:17-20] – “The package structure 4 can be fixed and connected with a system circuit board by inserting the pin 40 into the system circuit board and welding the pin 40 on the system circuit board”); and
provide a parallel line to the first interface or the second interface (110).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third interface structure as taught by Chen into Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 6, Yamashita as modified by Chen and Geissler, teaches claim 1 from which claim 6 depends. Yamashita and Geissler do not expressly disclose the limitations of claim 6.
However, in an analogous art, Chen teaches
further comprising a third interface (40) disposed on the first one of the
plurality of side surfaces (Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third interface structure as taught by Chen into Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Chen, Geissler, and Hossain et al. (US 20190115293 A1 – hereinafter Hossain).
Regarding claim 2, Yamashita as modified by Chen and Geissler, teaches claim 1 from which claim 2 depends. Yamashita further teaches
wherein the first interface (35) is further configured to transmit a first
type signal, and wherein the first type signal comprises at least one of a power signal ([1:28-34] – “an IC package having a predetermined number of pins including a power supply pin and a grounding pin and furthermore having a greater number of internal terminals which are connected to an IC chip and to the pins and includes at least one additional power supply terminal and at least one additional grounding terminal” – this describes a power signal transmitted between the device and circuit board by means of the electrodes) transmitted between the packaged device (PD) and the circuit board (39), a ground signal ([1:28-34] – “an IC package having a predetermined number of pins including a power supply pin and a grounding pin and furthermore having a greater number of internal terminals which are connected to an IC chip and to the pins and includes at least one additional power supply terminal and at least one additional grounding terminal” – this describes a ground signal transmitted between the device and circuit board by means of the electrodes) transmitted between the packaged device (PD) and the circuit board (39), or a control signal transmitted between the packaged device (PD) and the circuit board (39).
Yamashita, Chen, and Geissler do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Hossain teaches
a control signal ([0014] – “the integrated circuit dies may communicate with other components that are disposed on the same package as the respective integrated circuit dies or with components that are disposed on a PCB or other circuit device that is not on the same package of the respective integrated circuit dies (e.g., off-package). By way of example, one or more integrated circuit dies on a package may communicate with memory devices, such as memory chips, that are disposed off of the package. The memory chips may be categorized based on their types and applications. For example, double data rate synchronous dynamic random access memory (DDR SDRAM) offer higher data transfer rates by a strict control of timing of electrical data” – this describes a control signal transmitted between the circuit board and the package device) transmitted.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the control signal as taught by Hossain into Yamashita, Chen, and Geissler.
An ordinary artisan would have been motivated to use the known technique of Hossain in the manner set forth above to produce the predictable results of [0003] – “Multiple integrated circuit dies and components may be packaged on a substrate, forming an integrated circuit package. The package may include electrical connections that connect the die and other components to the printed circuit board (PCB) and pins or leads that may be utilized for the electrical connections to circuits, power, and ground external to the integrated circuit. Thus, the package may serve as the interface between the dies and the PCB” Which would require a common control signal.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nootens et al. (US 20220278021 A1 – hereinafter Nootens) in view of Yamashita and Geissler.
Regarding independent claim 7, Nootens teaches:
A power module ([0036] – “electronic package having an interposer
electrically connecting at least one high power integrated circuit die” – hereinafter ‘PM’), comprising:
at least one of a heat sink (142 – Fig. 10 – [0085] – “heat sink 142”) or a surface-mount device (124 – Fig. 10 – [0085] – “the mount 124”); and
a packaged device (0036] – “electronic package having an interposer electrically connecting at least one high power integrated circuit die” – hereinafter ‘Pack’) comprising:
a chip module ([0067] – “The depth of the cavity 55 … provide for flatness across the exposed surfaces of die and interposer” – this describes a chip module, hereinafter ‘CM’);
a package body (die – Fig. – [0067] – “The depth of the cavity 55 can be selected so that the upper surface 56 of the die 57” – this describes a package body, hereinafter ‘PB’) configured to package the chip module (CM) and comprising:
a bottom surface configured to face a circuit board; and
a plurality of side surfaces;
a first interface configured to connect to the circuit board, wherein the first interface is disposed on the bottom surface or on a part that is of at least a first one of the plurality of side surfaces and that is proximate to the bottom surface; and
a second interface (134 – Fig. 10 – [0084] – “mounting pads 134”) configured to connect to a surface-mount device (124),
wherein the second interface (134) is disposed on at least a second one of the plurality of side surfaces, and
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface,
wherein when the power module (PM) comprises the heat sink (142), the heat sink (142) is disposed on at least one of the plurality of side surfaces (Fig. 10 shows this), and
wherein when the power module (PM) comprises the surface-mount device (124), the surface-mount device (124) is connected to the second interface (134) of the packaged device (Pack).
Nootens does not expressly disclose the other limitations of claim 7.
However, in an analogous art, Yamashita teaches
a bottom surface (Fig. 7 annotated, see below – hereinafter ‘Bottom’)
configured to face a circuit board (39 – Fig. 7 – [6:3] – “printed circuit board 39”); and
a plurality of side surfaces;
a first interface (35 – Fig. 7 – [5:67] – “electrodes 35” – this is an interface) configured to connect to the circuit board (39), wherein the first interface (35) is disposed on the bottom surface (Bottom) or on a part that is of at least a first one of the plurality of side surfaces and that is proximate to the bottom surface (Bottom – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bottom surface structure as taught by Yamashita into Nootens.
An ordinary artisan would have been motivated to use the known technique of Yamashita in the manner set forth above to produce the predictable results [1:12-15] – “a chip package device or unit and to a multi-chip module which comprises a plurality of chip package devices on a printed circuit board used as a mother board.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Nootens and Yamashita do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Geissler teaches
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface ([0077] – “tall components 120 (second electrical device components B) are placed with adhesive tapes 720 on the bottom side” – Fig. 7d shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the side structure as taught by Geissler into Nootens and Yamashita.
An ordinary artisan would have been motivated to use the known technique of Geissler in the manner set forth above to produce the predictable results as stated above in claim 1.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nootens in view of Yamashita, Geissler, and Otremba et al. (US 20170098598 A1 – hereinafter Otremba).
Regarding claim 8, Nootens as modified by Yamashita and Geissler, teaches claim 7 from which claim 8 depends. Nootens, Yamashita and Geissler do not expressly disclose the limitations of claim 8.
However, in an analogous art, Otremba teaches
wherein the heat sink (100 – Fig. 4 – [0067] – “the electronic component 100 to
heat dissipation body 112 (which is here configured as a heat sink with cooling fins)” – hereinafter ‘HS’) comprises a heat-dissipation body (112 – Fig. 2 – [0066] – “heat dissipation body 112”), and wherein the heat-dissipation body (112) is connected to the surface-mount device (108 – Fig. 2 – [0067] – “interface structure 108” – this is interpreted as a surface-mount device) or the at least one of the plurality of side surfaces (Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results of [0005] – “A conventional electronic chip mounted on a chip carrier such as a leadframe, electrically connected by a bond wire extending from the chip to the chip carrier, and molded within a package may suffer from its thermal insulation within the package” therefor a method of removing this heat is required.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 9, Nootens as modified by Yamashita, Geissler, and Otremba, teaches claim 8 from which claim 9 depends. Nootens, Yamashita and Geissler do not expressly disclose the limitations of claim 9.
However, in an analogous art, Otremba teaches
wherein the heat sink (100) comprises a support body (116 – Fig. 4 – [0067] – “fastening element 116” – this is interpreted as a support body), wherein a first end of the support body (116) is connected to the heat-dissipation body (112), the surface-mount device (108), or the at least one of the plurality of side surfaces, and wherein a second end of the support body (112) is connected to the circuit board (132 – Fig. 6 – [0079] – “arrangement 130 comprises a mounting structure 132, here embodied as a printed circuit board (PCB)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Regarding claim 10, Nootens as modified by Yamashita, Geissler, and Otremba, teaches claim 9 from which claim 10 depends. Nootens, Yamashita and Geissler do not expressly disclose the limitations of claim 10.
However, in an analogous art, Otremba teaches
wherein the surface-mount device (108) or the second interface (134 – Fig. 6
– [0079] – “arrangement 130 comprises a mounting structure 132, here embodied as a printed circuit board (PCB), which comprises electric contacts 134”) is electrically connected to the circuit board (132) by using the heat sink (100 – Fig. 6 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Regarding claim 11, Nootens as modified by Yamashita, Geissler, and Otremba, teaches claim 9 from which claim 11 depends. Nootens further teaches
the packaged device (Pack).
Nootens, Yamashita and Geissler do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Otremba teaches
wherein the packaged device comprises a third interface (114 – [0077] –
“electronic component 100 again comprises a clip 118 (rather than a fastening element 116 in cooperation with a through hole 114) configured for connecting the electronic component 100 to a heat dissipation body 112 by clamping”), and wherein the third interface (114) is electrically connected to the circuit board (132) by using the heat sink (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Regarding claim 12, Nootens as modified by Yamashita and Geissler, teaches claim 7 from which claim 12 depends. Nootens, Yamashita and Geissler do not expressly disclose the limitations of claim 12.
However, in an analogous art, Otremba teaches
wherein the heat sink (100) is disposed on a third one of the plurality of
side surfaces, and wherein the surface-mount device (108) and the second interface (102 – Fig. 6 – [0079] – “the mounting structure 132 so that the electronic chip 104 is electrically connected to the electric contact 134 via the chip carrier 102”) are disposed on the second one of the plurality of side surfaces.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Claims 13 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nootens in view of Yamashita, Geissler, Otremba and Chen.
Regarding independent claim 13, Nootens teaches:
An electronic apparatus ([0053] – “electronic device interposer” –
hereinafter ‘EA’), comprising:
a circuit board (76 – Fig. 8 – [0074] – “printed circuit board 76”) comprising a first connection interface (75 – Fig. 8 – [0074] – “mounting pads 75 on the circuit board”); and
a power module disposed on the circuit board and comprising:
at least one of a heat sink or a surface-mount device; and
a packaged device ([0036] – “electronic package having an interposer electrically connecting at least one high power integrated circuit die” – hereinafter ‘Pack’) disposed sideways on the circuit board and comprising:
a chip module;
a package body configured to package the chip module and comprising:
a bottom surface configured to face the circuit board; and
a plurality of side surfaces;
a first interface configured to connect to the first connection interface (75 – Fig. 8 – [0074] – “mounting pads 75 on the circuit board”), wherein the first interface is disposed on the bottom surface or on a part that is of at least a first one of the plurality of side surfaces and that is proximate to the bottom surface; and
a second interface (134 – Fig. 10 – [0084] – “mounting pads 134”) configured to connect to the surface-mount device (124 – Fig. 10 – [0085] – “the mount 124”),
wherein the second interface (134) is disposed on at least a second one of the plurality of side surfaces,
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface,
wherein when the power module (PM) comprises the heat sink (142), the heat sink (142) is disposed on at least one of the plurality of side surfaces (Fig. 10 shows this), and
wherein when the power module (PM) comprises the surface-mount device (124), the surface-mount device (124) is connected to the second interface (134) of the packaged device (Pack).
Nootens does not expressly disclose the other limitations of claim 13.
However, in an analogous art, Yamashita teaches
the circuit board (39 – Fig. 7 – [6:3] – “printed circuit board 39”) and comprising:
a chip module (31 – Fig. 6 – [4:58-59] – “IC chip 31 is brought onto the package substrate 33”);
a package body (51 – Fig. 6 – [5:56-58] – “a mass of resin 51 is formed to cover the IC chip 31 and a marginal or peripheral area of the package substrate 33” – this is interpreted as a package body) configured to package the chip module (31) and comprising:
a bottom surface configured to face the circuit board (39); and
a plurality of side surfaces;
a first interface (35 – Fig. 7 – [5:67] – “electrodes 35” – this is an interface) configured to connect to the first connection interface, wherein the first interface (35) is disposed on the bottom surface (Bottom) or on a part that is of at least a first one of the plurality of side surfaces and that is proximate to the bottom surface (Bottom – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the circuit board structure as taught by Yamashita into Nootens.
An ordinary artisan would have been motivated to use the known technique of Yamashita in the manner set forth above to produce the predictable results as stated above in claim 7.
Nootens and Yamashita do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Geissler teaches
disposed sideways ([0077] – “tall components 120 (second electrical device components B) are placed with adhesive tapes 720 on the bottom side” – Fig. 7d shows this) on the circuit board,
wherein a first area of at least one of the plurality of side surfaces is greater than a second area of the bottom surface ([0077] – “tall components 120 (second electrical device components B) are placed with adhesive tapes 720 on the bottom side” – Fig. 7d shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the side structure as taught by Geissler into Nootens and Yamashita.
An ordinary artisan would have been motivated to use the known technique of Geissler in the manner set forth above to produce the predictable results as stated above in claim 1.
Nootens, Yamashita and Geissler do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Otremba teaches
at least one of a heat sink (100 – Fig. 4 – [0067] – “the electronic component 100 to heat dissipation body 112 (which is here configured as a heat sink with cooling fins)” – hereinafter ‘HS’) or a surface-mount device (108 – Fig. 2 – [0067] – “interface structure 108” – this is interpreted as a surface-mount device).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Nootens, Yamashita, Geissler, and Otremba do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Chen teaches
a power module (8 – Fig. 8 – [13:28] – “stacked package module 8” – this can be a power module) disposed on the circuit board ([13:38-40] – “package structure 8 can be fixed and connected with a system circuit board by inserting the pin 80 into the system circuit board and welding the pin 80 on the system circuit board” – this can be disposed on a circuit board) and comprising:
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power module structure as taught by Chen into Nootens, Yamashita, Geissler, and Otremba.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 19, Nootens as modified by Yamashita, Geissler, Otremba, and Chen, teaches claim 13 from which claim 19 depends. Nootens, Geissler, and Otremba do not expressly disclose the limitations of claim 19.
However, in an analogous art, Yamashita teaches
the packaged device (PD).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the package device structure as taught by Yamashita into Nootens, Geissler, and Otremba.
An ordinary artisan would have been motivated to use the known technique of Yamashita in the manner set forth above to produce the predictable results as stated above in claim 7.
Nootens, Geissler, Otremba, and Yamashita do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Chen teaches
wherein the second interface (110) is further configured to transmit a
second type signal, and wherein the second type signal comprises at least one of a voltage signal transmitted between the packaged device and the surface-mount device (SMD) or a current signal transmitted ([11:52-61] – “the first conducting terminals 110 of the first electronic component 11 and the second conductive layer 13 are isolated from the heat dissipation device 31. In addition, after the heat is transferred to the second conductive layer 13, the heat may be further transferred to the heat dissipation device 31 through the insulating and heat-dissipating layer 30. More especially, since the package structure 3 can withstand a high voltage, the possibility of causing current leakage and high-voltage spark will be minimized” – this describes a voltage or current signal transmitted via 110) between the packaged device and the surface-mount device (SMD).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the interface and signal structure as taught by Chen into Nootens, Yamashita, Geissler, and Otremba.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 20, Nootens as modified by Yamashita, Geissler, Otremba, and Chen, teaches claim 13 from which claim 20 depends. Nootens, Geissler, Otremba, and Yamashita do not expressly disclose the limitations of claim 20.
However, in an analogous art, Chen teaches
wherein the packaged device comprises a third interface (40 – Fig. 4 –
[12:17-20] – “The package structure 4 can be fixed and connected with a system circuit board by inserting the pin 40 into the system circuit board and welding the pin 40 on the system circuit board”), and wherein the third interface is disposed on at least a third one of the plurality of side surfaces (Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third interface structure as taught by Chen into Nootens, Yamashita, Geissler, and Otremba.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nootens in view of Yamashita, Geissler, Otremba, Chen, and Mische (US 10785864 B2).
Regarding claim 14, Nootens as modified by Yamashita, Geissler, Otremba, and Chen, teaches claim 13 from which claim 14 depends. Nootens further teaches
the circuit board (76 – Fig. 8 – [0074] – “printed circuit board 76”).
Nootens, Yamashita, and Geissler do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Otremba teaches
comprises the heat sink (100 – Fig. 4 – [0067] – “the electronic component 100 to heat dissipation body 112 (which is here configured as a heat sink with cooling fins)” – hereinafter ‘HS’),
a support body (116 – Fig. 4 – [0067] – “fastening element 116” – this is interpreted as a support body) of the heat sink (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat sink structure as taught by Otremba into Nootens, Yamashita and Geissler.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results as stated above in claim 8.
Nootens, Yamashita, Geissler, and Otremba do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Chen teaches
the power module (8).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power module structure as taught by Chen into Nootens, Yamashita, Geissler, and Otremba.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 1.
Nootens, Yamashita, Geissler, Otremba, and Chen do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Mische teaches
a second connection interface (500 – Fig. 5A – [8:24-27] – “connector 500 coupled directly to a PCB 502 (shown as a cutout of a larger PCB for illustration purposes). The connector 500 may couple to a heat sink 501 or another component”}, {[2:35-39] – “a connector (also referred to as an “interface” or a “coupler”}) may be coupled to the PCB aperture, possibly via the aforementioned PCB features. The connector may include connector features that are configured to couple to other components, such as a heat sink”) or a third connection interface, and the second connection interface (500).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection interface structure as taught by Mische into Nootens, Yamashita, Geissler, Otremba, and Chen.
An ordinary artisan would have been motivated to use the known technique of Mische in the manner set forth above to produce the predictable results of electrically connecting components together.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nootens in view of Yamashita, Geissler, Otremba, Chen, Mische, and Kim et al. (US 9530753 B2 – hereinafter Kim).
Regarding claim 15, Nootens as modified by Yamashita, Geissler, Otremba, Chen, and Mische teaches claim 14 from which claim 15 depends. Nootens, Yamashita, Geissler, Otremba, Chen, and Mische do not expressly disclose the limitations of claim 15.
However, in an analogous art, Kim teaches
wherein the packaged device (108 – Fig. 1 – [5:47] – “vertical chip 108” – this
is a device) further comprises a third interface (137 – Fig. 1 – “[5:47-51] – “The arch interconnect 140 can electrically couple the bond pad 137 to the substrate component contact 105 of the first substrate 102. The arch interconnect 140 can electrically couple the bond pad 137 to the second substrate contact 135 of the second substrate 110” – this corresponds to an interface on the package device), and wherein the second connection interface (105 – Fig. 1 – [5:47-51] – “The arch interconnect 140 can electrically couple the bond pad 137 to the substrate component contact 105 of the first substrate 102. The arch interconnect 140 can electrically couple the bond pad 137 to the second substrate contact 135 of the second substrate 110” – this corresponds to a connection interface on the circuit board) is electrically connected to the third interface (137) by using the heat sink ([4:9-13] – “the integrated circuit structure 106 can be two or more stacked integrated circuit dies, an integrated circuit die stacked with a heat sink, an integrated circuit die stacked with an integrated circuit package, or a combination thereof”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection interface structure as taught by Kim into Nootens, Yamashita, Geissler, Otremba, Chen, and Mische.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results [1:51-53] – “to reduce costs, improve efficiencies and performance, and meet competitive pressures.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 16, Nootens as modified by Yamashita, Geissler, Otremba, Chen, and Mische teaches claim 14 from which claim 16 depends. Nootens, Yamashita, Geissler, Otremba, Chen, and Mische do not expressly disclose the limitations of claim 16.
However, in an analogous art, Kim teaches
wherein when the power module further comprises the surface-mount
device (128 – Fig. 1 - [4:32-39] – “integrated circuit structure 106 can include a stack device 128, which is defined as a component, an integrated circuit die, integrated circuit package, or a combination thereof for stacking over other dies, components, and packages. The stack device 128 can include a flip chip die, a wire bonded die, or an integrated circuit package. The stack device 128 can be mounted over the base integrated circuit 120” – this is interpreted that the one of the stacked packages can be a power moduel that is a surface mount device), the third connection (133 – Fig. 1 – [4:50-51] – “interconnect 133 directly attached to the interconnect side 130 of the stack device 128”) interface is electrically connected to the surface-mount device by using the heat sink ([4:9-13] – “the integrated circuit structure 106 can be two or more stacked integrated circuit dies, an integrated circuit die stacked with a heat sink, an integrated circuit die stacked with an integrated circuit package, or a combination thereof”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power module structure as taught by Kim into Nootens, Yamashita, Geissler, Otremba, Chen, and Mische.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 15.
Regarding claim 17, Nootens as modified by Yamashita, Geissler, Otremba, Chen, and Mische teaches claim 14 from which claim 17 depends. Nootens, Yamashita, Geissler, Otremba, Chen, and Mische do not expressly disclose the limitations of claim 17.
However, in an analogous art, Kim teaches
wherein the third connection interface (137) is electrically connected to the
second interface (135 – Fig. 1 – [5:18-22] – “second substrate contact 135 can provide an electrical connection to the second substrate 110”) by using the heat sink ([4:9-13] – “the integrated circuit structure 106 can be two or more stacked integrated circuit dies, an integrated circuit die stacked with a heat sink, an integrated circuit die stacked with an integrated circuit package, or a combination thereof”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection structure as taught by Kim into Nootens, Yamashita, Geissler, Otremba, Chen, and Mische.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 15.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nootens in view of Yamashita, Geissler, Otremba, Chen, and Hossain.
Regarding claim 18, Nootens as modified by Yamashita, Geissler, Otremba, and Chen, teaches claim 13 from which claim 18 depends. Nootens, Geissler, Otremba, and Chen do not expressly disclose the limitations of claim 18.
However, in an analogous art, Yamashita teaches
wherein the first interface (35) is further configured to transmit a first type signal, and wherein the first type signal comprises at least one of a power signal ([1:28-34] – “an IC package having a predetermined number of pins including a power supply pin and a grounding pin and furthermore having a greater number of internal terminals which are connected to an IC chip and to the pins and includes at least one additional power supply terminal and at least one additional grounding terminal” – this describes a power signal transmitted between the device and circuit board by means of the electrodes) transmitted between the packaged device (PD) and the circuit board (39), a ground signal ([1:28-34] – “an IC package having a predetermined number of pins including a power supply pin and a grounding pin and furthermore having a greater number of internal terminals which are connected to an IC chip and to the pins and includes at least one additional power supply terminal and at least one additional grounding terminal” – this describes a ground signal transmitted between the device and circuit board by means of the electrodes) transmitted between the packaged device (PD) and the circuit board (39), or a control signal transmitted between the packaged device (PD) and the circuit board (39).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the package device structure as taught by Yamashita into Nootens, Geissler, Otremba, and Chen.
An ordinary artisan would have been motivated to use the known technique of Yamashita in the manner set forth above to produce the predictable results as stated above in claim 7.
Nootens, Geissler, Otremba, Chen, and Yamashita do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Hossain teaches
a control signal ([0014] – “the integrated circuit dies may communicate with other components that are disposed on the same package as the respective integrated circuit dies or with components that are disposed on a PCB or other circuit device that is not on the same package of the respective integrated circuit dies (e.g., off-package). By way of example, one or more integrated circuit dies on a package may communicate with memory devices, such as memory chips, that are disposed off of the package. The memory chips may be categorized based on their types and applications. For example, double data rate synchronous dynamic random access memory (DDR SDRAM) offer higher data transfer rates by a strict control of timing of electrical data” – this describes a control signal transmitted between the circuit board and the package device) transmitted.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the control signal as taught by Hossain into Yamashita, Chen, and Geissler.
An ordinary artisan would have been motivated to use the known technique of Hossain in the manner set forth above to produce the predictable results as stated above in claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights