Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 12-15, 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 20220131013 A1) hereafter referred to as Tang in view of Kikkawa et al. (US 20090065787 A1) hereafter referred to as Kikkawa. Park et al. (US 20130082276 A1) hereafter referred to as Park is provided as evidence.
In regard to claim 1 Tang teaches [“FIGS. 2A-2C illustrate cross-sectional views of an example semiconductor device 200 having a source and a drain”] a semiconductor structure, comprising:
a substrate [“substrate 102 may be composed of gallium arsenide (GaAs), silicon (Si), indium phosphide (InP), or any other suitable material, such as any suitable Group III-V semiconductor material”];
a channel structure [“channel regions 110”] on the substrate, wherein the channel structure comprises a first intermediate layer [see each channel has a “barrier layers 112” below and above it], a channel layer [“each of the channel regions 110 may extend from the doped semiconductor region 204 to the doped semiconductor region 208”], and a second intermediate layer [see each channel has a “barrier layers 112” below and above it] that are stacked on [see FIGS. 2A-2C] the substrate, and the channel structure comprises a gate region [“the gate region 116 may surround the barrier layer 112E, the channel region 110C, and the barrier layer 112F, as shown”], and a source region [“the semiconductor device 200 may include doped semiconductor regions 204, 208 disposed above the buffer layer 104 and adjacent to the channel regions 110, the barrier layers 112, and the sacrificial layers 114” “the semiconductor device 200 may include S/D contacts 202, 206 disposed above the doped semiconductor regions 204, 208, respectively”] and a drain region at both sides of the gate region;
a gate electrode within the gate region [“the gate region 116 is implemented in a gate-all-around fashion, meaning that the gate region 116 surrounds the lateral surface(s) of each of the channel regions 110”], wherein the gate electrode covers sidewalls of the channel structure,
but does not teach a first N-type heavily doped layer and a second N-type heavily doped layer, wherein the first N-type heavily doped layer is between the substrate and the channel structure, and the second N-type heavily doped layer is on a side of the channel structure far from the substrate, and projection of the first N-type heavily doped layer on the channel structure and projection of the second N-type heavily doped layer on the channel structure are located within the gate region; and wherein the gate electrode covers sidewalls of the first N-type heavily doped layer and the second N-type heavily doped layer.
The Examiner notes that Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang.
See Kikkawa teaches see Fig. 1A see the “GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports” see the higher bandgap “non-doped AlGaN layer 105” “n-type AlGaN layer 106 serves as an electron supply layer to supply electron carriers to the active layer 104” see “an n-type GaN layer 107 as a protective layer is grown on the n-type AlGaN layer 106. A doping amount of Si is, for example, about 5.times.10.sup.18 cm.sup.-3. The n-type AlGaN layer 106 is therefore covered with the n-type GaN layer 107 having a lower resistivity”, see the gate “SiN film 108 in a gate contact region is etched, and for example, an Ni layer of 20 nm thick and an Au layer of 400 nm thick are formed and patterned to form a gate electrode. This electrode can be formed, for example, also by lift-off method. The gate electrode forms a Schottky contact” see also a different metal give ohmic contact to 107 in Fig. 1A see “For example, a Ta layer of 10 nm thick is formed, an Al layer of 300 nm thick is formed on the Ta layer, and they are patterned to form a source electrode S and a drain electrode D. These electrodes can be patterned, for example, by lift-off method. Annealing is performed at 600.degree. C. to form ohmic contacts”, thus the choice of the metal used gives a choice of either ohmic or Schottky contact.
Park is provided as evidence that it is common in the art to make metal choice for the gate, see paragraph 0020 “In another example of the present invention, the gate electrode may be in ohmic contact with the n-type nitride layer. At this time, in an example, the source, drain, and gate electrodes may be made of the same metal material”.
Applying the teaching of Kikkawa to Tang Fig. 2B, it would be obvious to place a heavily doped n -type layer of lower bandgap than the Barrier 112 between the Barrier 112 and the gate region 116 i.e. it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include a first N-type heavily doped layer and a second N-type heavily doped layer, wherein the first N-type heavily doped layer is between the substrate and the channel structure, and the second N-type heavily doped layer is on a side of the channel structure far from the substrate, and projection of the first N-type heavily doped layer on the channel structure and projection of the second N-type heavily doped layer on the channel structure are located within the gate region; and wherein the gate electrode covers sidewalls of the first N-type heavily doped layer and the second N-type heavily doped layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to lower resistance of the device.
In regard to claim 2 Tang and Kikkawa as combined teaches wherein the gate electrode is in ohmic contact [see this is based on the metal choice, see Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang] with the first N-type heavily doped layer and the second N-type heavily doped layer.
In regard to claim 3 Tang and Kikkawa as combined teaches wherein the semiconductor structure comprises: a plurality of the channel structures that are stacked [see Tang FIGS. 2A-2C, see combination] on the substrate; and a third N-type heavily doped layer [see Tang FIGS. 2A-2C, see combination] between adjacent channel structures of the plurality of channel structures, and projection of the third N-type heavily doped layer on the channel structure is located [see Tang FIGS. 2A-2C, see combination] within the gate region.
In regard to claim 4 Tang and Kikkawa as combined teaches wherein the plurality of channel structures share [see Tang FIGS. 2A-2C, see combination] the gate electrode, the gate electrode covers sidewalls of the third N-type heavily doped layer, and the gate electrode is in ohmic contact [see this is based on the metal choice, see Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang] with the third N-type heavily doped layer.
In regard to claim 5 Tang and Kikkawa as combined does not teach in Fig. 2A further comprising: a dielectric layer on the gate region, wherein the dielectric layer covers the sidewalls of the channel layer, and the dielectric layer is between the gate electrode and the channel layer.
However see embodiment of Fig. 7A, Fig. 7B see “Continuing from the etching of the middle portion of each of the sacrificial layers 114 in FIGS. 5D and 5E, a dielectric layer 702 (e.g., also referred to as a “gate dielectric”) may be formed adjacent to a top or bottom portion of each of the barrier layers 112, as well as adjacent to each of the channel regions 110, as shown in FIGS. 7A and 7B. FIG. 7B is a cross-section of the semiconductor device 500 through the line B-B′ of FIG. 7A”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include further comprising: a dielectric layer on the gate region, wherein the dielectric layer covers the sidewalls of the channel layer, and the dielectric layer is between the gate electrode and the channel layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use the field effect to control the channel to obtain an FET i.e. field effect transistor with insulated gate.
In regard to claim 6 Tang and Kikkawa as combined teaches wherein the channel layer is [see Tang FIGS. 2A-2C] a nanowire structure or a nanosheet structure.
In regard to claim 7 Tang and Kikkawa as combined teaches wherein a material of the channel structure [“In certain aspects, the channel regions 110 are composed of Group III-V materials, such as indium gallium arsenide (InGaAs), or any other suitable material”] comprises a group-III nitride material.
In regard to claim 8 Tang and Kikkawa as combined teaches [“The barrier layers 112 may be composed of AlGaAs, indium gallium phosphide (InGaP), indium aluminum arsenide (InAlAs), or any other suitable material that is at least partially- or delta-doped by impurities to form two-dimensional electron gas in the channel regions 110. The material of the barrier layers 112 may have a bandgap larger than a bandgap of the channel regions 110” “In certain aspects, the channel regions 110 are composed of Group III-V materials, such as indium gallium arsenide (InGaAs), or any other suitable material” “The sacrificial layers 114 may be composed of aluminum arsenide (AlAs), indium phosphide (InP), or any other suitable material”] thus Tang does not state wherein materials of the first intermediate layer and the second intermediate layer comprises AlN; and a material of the channel layer comprises GaN, AlGaN, InGaN, or AlInGaN.
However in addition to the P and As, the nitride N is also part of the Group III-V materials, see combination Kikkawa, see “GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports” see the higher bandgap “non-doped AlGaN layer 105” “n-type AlGaN layer 106 serves as an electron supply layer to supply electron carriers to the active layer 104” see “an n-type GaN layer 107 as a protective layer is grown on the n-type AlGaN layer 106”.
See that between barrier layers and channel regions it the bandgap and formation of 2DEG that determines choice and for sacrificial layers it selective etching.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include wherein materials of the first intermediate layer and the second intermediate layer comprises AlN; and a material of the channel layer comprises GaN, AlGaN, InGaN, or AlInGaN.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the nitride N is also part of the Group III-V materials and is known to give excellent results in semiconductor devices.
In regard to claim 9 Tang and Kikkawa as combined teaches further comprising: a source electrode [see Tang “the semiconductor device 200 may include S/D contacts 202, 206 disposed above the doped semiconductor regions 204, 208, respectively”] and a drain electrode respectively at the source region and the drain region, but in Figs. 2A-2C does not state wherein the source electrode and the drain electrode both wrap around the channel layer.
However see embodiment of Fig. 3C, see “as illustrated in FIG. 3C, which is a cross-sectional view of the semiconductor device 300 along the line Y-Y′ of FIG. 3A, S/D terminal 302 may be formed such that the channel regions 110, barrier layers 112, and the sacrificial layers 114 are disposed between portions of the S/D terminal 302. That is, multiple sides of each of the channel regions 110, barrier layers 112, and the sacrificial layers 114 may be adjacent to the S/D terminal 302. Further, the S/D terminal 302 may cover lateral and top surfaces of an end (e.g., the barrier layer 112F) of a stack comprising the channel regions 110, the barrier layers 112, and the sacrificial layers 114. Furthermore, S/D terminal 304 may be formed in a similar manner to the S/D terminal 302”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include wherein the source electrode and the drain electrode both wrap around the channel layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is better electrical contact to source and drain.
In regard to claim 10 Tang and Kikkawa as combined teaches [see Tang “In certain aspects, the channel regions 110 may be n-type delta doped (e.g., the dopant may be highly concentrated in a thin layer)”] but does not state wherein the channel layer is an N-type lightly doped layer, and doping concentration of N-type ions for the channel layer is less than 1E18.
The Examiner notes that the limitation of “less than 1E18” is broad because it includes any non-zero dopant level.
See that in regions of the channel regions 110 that is adjacent the delta doped, the concentration is much lower and there will be a decay in concentration from delta doped to non-delta-doped, see that some diffusion of dopant will also occur in non-zero heat processing steps, see also Kikkawa “GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include wherein the channel layer is an N-type lightly doped layer, and doping concentration of N-type ions for the channel layer is less than 1E18.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Tang does not state intentionally doping the non-delta-doped part of the channel, thus the concentration of n-type dopant will be very low indeed, but not necessarily zero because the delta-doping will have a decay in concentration from delta doped to non-delta-doped.
Claim(s) 11, 16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 20220131013 A1) hereafter referred to as Tang in view of Kikkawa et al. (US 20090065787 A1) hereafter referred to as Kikkawa. Park et al. (US 20130082276 A1) hereafter referred to as Park is provided as evidence.
In regard to claim 11 Tang teaches [“FIGS. 2A-2C illustrate cross-sectional views of an example semiconductor device 200 having a source and a drain”] a manufacturing method for a semiconductor structure, comprising:
providing a substrate [“substrate 102 may be composed of gallium arsenide (GaAs), silicon (Si), indium phosphide (InP), or any other suitable material, such as any suitable Group III-V semiconductor material”];
sequentially manufacturing a channel structure [“In certain aspects, during fabrication, the channel regions 110, the barrier layers 112, and the sacrificial layers 114 may be formed first, and may be partially etched (e.g., wet etched) to facilitate formation (e.g., growth) of the doped semiconductor regions 204, 208”] on the substrate,
wherein manufacturing the channel structure comprises:
manufacturing a first intermediate layer [see each channel has a “barrier layers 112” below and above it], a channel layer [“channel regions 110”], and a second intermediate layer [see each channel has a “barrier layers 112” below and above it] that are stacked on the first N-type heavily doped layer, wherein the channel structure comprises a gate region [i.e. the central region “the gate region 116 may surround the barrier layer 112E, the channel region 110C, and the barrier layer 112F, as shown”], and a source region [“the semiconductor device 200 may include doped semiconductor regions 204, 208 disposed above the buffer layer 104 and adjacent to the channel regions 110, the barrier layers 112, and the sacrificial layers 114” “the semiconductor device 200 may include S/D contacts 202, 206 disposed above the doped semiconductor regions 204, 208, respectively”] and a drain region at both sides of the gate region;
removing parts of the layers [“In certain aspects, during fabrication, the channel regions 110, the barrier layers 112, and the sacrificial layers 114 may be formed first, and may be partially etched (e.g., wet etched) to facilitate formation (e.g., growth) of the doped semiconductor regions 204, 208”, see all the layers above 104 in Fig. 2A are partially etched] whose projection on the channel structure is within the source region and the drain region; and
manufacturing a gate electrode [“As shown in FIG. 5D, a middle portion of each of the sacrificial layers 114 may be etched (e.g., wet etched) or otherwise selectively removed to form gaps 504A, 504B, 504C (collectively referred to as “gaps 504”)” “As shown in FIG. 5F, the middle portion 503 of the sacrificial layer 502 and gaps 504 may be filled with gate metal for the gate region 116”] within the gate region,
and wherein the gate electrode covers sidewalls [“the gate region 116 is implemented in a gate-all-around fashion, meaning that the gate region 116 surrounds the lateral surface(s) of each of the channel regions 110”] of the channel structure,
but does not teach that the sequentially manufacturing is a first N-type heavily doped layer, the channel structure, and a second N-type heavily doped layer on the substrate, that the removing parts includes of the first N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region, and parts of the second N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region; and wherein the gate electrode covers sidewalls of the first N-type heavily doped layer and the second N-type heavily doped layer.
The Examiner notes that Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang.
See Kikkawa teaches see Fig. 1A see the “GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports” see the higher bandgap “non-doped AlGaN layer 105” “n-type AlGaN layer 106 serves as an electron supply layer to supply electron carriers to the active layer 104” see “an n-type GaN layer 107 as a protective layer is grown on the n-type AlGaN layer 106. A doping amount of Si is, for example, about 5.times.10.sup.18 cm.sup.-3. The n-type AlGaN layer 106 is therefore covered with the n-type GaN layer 107 having a lower resistivity”, see the gate “SiN film 108 in a gate contact region is etched, and for example, an Ni layer of 20 nm thick and an Au layer of 400 nm thick are formed and patterned to form a gate electrode. This electrode can be formed, for example, also by lift-off method. The gate electrode forms a Schottky contact” see also a different metal give ohmic contact to 107 in Fig. 1A see “For example, a Ta layer of 10 nm thick is formed, an Al layer of 300 nm thick is formed on the Ta layer, and they are patterned to form a source electrode S and a drain electrode D. These electrodes can be patterned, for example, by lift-off method. Annealing is performed at 600.degree. C. to form ohmic contacts”, thus the choice of the metal used gives a choice of either ohmic or Schottky contact.
Park is provided as evidence that it is common in the art to make metal choice for the gate, see paragraph 0020 “In another example of the present invention, the gate electrode may be in ohmic contact with the n-type nitride layer. At this time, in an example, the source, drain, and gate electrodes may be made of the same metal material”.
Applying the teaching of Kikkawa to Tang Fig. 2B, it would be obvious to place a heavily doped n -type layer of lower bandgap than the Barrier 112 between the Barrier 112 and the gate region 116 i.e. it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include that the sequentially manufacturing is a first N-type heavily doped layer, the channel structure, and a second N-type heavily doped layer on the substrate, that the removing parts includes of the first N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region, and parts of the second N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region; and wherein the gate electrode covers sidewalls of the first N-type heavily doped layer and the second N-type heavily doped layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to lower resistance of the device.
In regard to claim 16 Tang and Kikkawa as combined teaches wherein the gate electrode is in ohmic contact [see this is based on the metal choice, see Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang] with the first N-type heavily doped layer and the second N-type heavily doped layer.
In regard to claim 18 Tang and Kikkawa as combined teaches wherein manufacturing the channel structure comprises: manufacturing a plurality of the channel structures that are stacked [see Tang FIGS. 2A-2C, see combination] on the substrate; and the method further comprises: manufacturing a third N-type heavily doped layer [see Tang FIGS. 2A-2C, see combination] between adjacent channel structures in the plurality of channel structures, wherein the gate electrode is connected to [see Tang FIGS. 2A-2C, see combination] the third N-type heavily doped layer, and the gate electrode is in ohmic contact [see this is based on the metal choice, see Tang teaches “gate metal for the gate region 116” but does not state that the gate 116 is a Schottky contact, thus it could be said that either ohmic or Schottky is envisaged by Tang] with the third N-type heavily doped layer.
In regard to claim 19 Tang and Kikkawa as combined teaches wherein [“In certain aspects, during fabrication, the channel regions 110, the barrier layers 112, and the sacrificial layers 114 may be formed first, and may be partially etched (e.g., wet etched) to facilitate formation (e.g., growth) of the doped semiconductor regions 204, 208”, see combination, see all the layers above 104 in Fig. 2A are partially etched] removing the parts of the first N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region, and the parts of the second N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region comprises: removing the parts of the first N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region, the parts of the second N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region, and parts of the third N-type heavily doped layer whose projection on the channel structure is within the source region and the drain region.
In regard to claim 20 Tang and Kikkawa as combined teaches further comprising: performing N-type doping [see Tang “In certain aspects, the channel regions 110 may be n-type delta doped (e.g., the dopant may be highly concentrated in a thin layer)”] on the channel layer, but does not state wherein doping concentration of N-type ions is less than 1E18.
The Examiner notes that the limitation of “less than 1E18” is broad because it includes any non-zero dopant level.
See that in regions of the channel regions 110 that is adjacent the delta doped, the concentration is much lower and there will be a decay in concentration from delta doped to non-delta-doped, see that some diffusion of dopant will also occur in non-zero heat processing steps, see also Kikkawa “GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tang to include wherein doping concentration of N-type ions is less than 1E18.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Tang does not state intentionally doping the non-delta-doped part of the channel, thus the concentration of n-type dopant will be very low indeed, but not necessarily zero because the delta-doping will have a decay in concentration from delta doped to non-delta-doped.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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