DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 6, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings were received on June 6, 2024. These drawings are acceptable.
Claim Objections
Claim(s) 1 and 6 are objected to because of the following informalities (note that the markings show the examiner’s suggested amendments):
Claim 1, line 13, “electrostatic electrode and not to be exposed to an inner”, should be change to - - built-in electrostatic electrode and not to be exposed to an inner - -.
Claim 1, line 15, “electrically coupled to the electrostatic electrode; and”, should be change to - - electrically coupled to the built-in electrostatic electrode; and - -.
Claim 1, line 17, “from the electrostatic electrode at a height equal to or”, should be change to - - from the built-in electrostatic electrode at a height equal to or - -.
Claim 6, line 6, “shape as the electrostatic electrode and having a through-”, should be change to - - shape as the built-in electrostatic electrode and having a through- - -.
Appropriate correction is required.
Examiner’s Note: Applicant is required to carefully review all pending claims for the presence of any similar informalities and to correct them accordingly.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With regard to claim 2, recite the limitation “wherein the base plate also serves as the bias electrode” which renders the claim vague and indefinite. It is unclear because independent claim 1 requires “a base plate” and “a bias electrode” as separate components; claim 1 also requires that “the bias electrode is located at a height equal to or lower than a height of a lowermost inner electrode of the plurality of inner electrodes” (see applicant’s Fig. 5, Fig. 6) wherein the bias electrode (35 – Fig. 5; 135 – Fig. 6) is located at a height equal to or lower than a height of a lowermost inner electrode (33 – Fig. 5; Fig. 6) of the plurality of inner electrodes (31, 32, 33 – Fig. 5; Fig. 6). This limitation recites a contradictory configuration of independent claim 1. Clarification is required.
Allowable Subject Matter
Claim(s) 1 and 3-8 are allowed.
Claim(s) 2 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The claimed combination found within independent claim 1 is considered novel and unobvious in view of the prior art of record. The closest prior art is considered to be Ito (WO 2023/095707 A1) and Ishikawa (US 2023/0090650 A1).
Ito teaches a member for semiconductor manufacturing apparatus (Abstract, lines 1-4), comprising: a ceramic plate (1111 – Fig. 3) having a wafer placement surface (111a1 – Fig. 3) on its upper surface and a built-in electrostatic electrode (1113a – Fig. 3); a base plate (1110 – Fig. 3) provided on a lower surface of the ceramic plate (1111 – Fig. 3), and configured to include a built-in refrigerant flow path (116 – Fig. 3); a passage (115 – Fig. 3) provided from a lower surface of the base plate (1110 – Fig. 3) to the wafer placement surface (111a1 – Fig. 3) of the ceramic plate (1111 – Fig. 3); and a bias electrode (1113b – Fig. 3) (page 4, line 34; Machine Translation) provided electrically independently from the built-in electrostatic electrode (1113a – Fig. 3), the bias electrode (1113b – Fig. 3) being configured so that a bias voltage (31 – Fig. 2) is applied when generating a plasma over the wafer placement surface (111a1 – Fig. 3) (page 4, line 47; page 5,lines 1-6; Machine Translation).
Ishikawa teaches a member for semiconductor manufacturing apparatus (1 – Fig. 2), comprising:
a ceramic plate (114 – Fig. 2) having a wafer placement surface (11 – Fig. 2) on its upper surface and a built-in electrostatic electrode (115 – Fig. 2; Fig. 3); a base plate (113 – Fig. 2) provided on a lower surface of the ceramic plate (114 – Fig. 2), and configured to include a built-in refrigerant flow path (113a – Fig. 2); an inner electrode (117 – Fig. 2); and a bias electrode (116 – Fig. 3) provided electrically independently from the built-in electrostatic electrode (115 – Fig. 2; Fig. 3), the bias electrode (116 – Fig. 3) being configured so that a bias voltage is applied when generating a plasma over the wafer placement surface (11 – Fig. 2) ([0055] lines 1-8).
The following is an examiner’s statement of reasons for allowance:
With regard to claim 1, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a plurality of inner electrodes provided in multiple steps in an up-down direction inside the ceramic plate so as to be located in a periphery of the passage under the built-in electrostatic electrode and not to be exposed to an inner wall of the passage, the plurality of inner electrodes being electrically coupled to the built-in electrostatic electrode; and a bias electrode provided electrically independently from the built-in electrostatic electrode at a height equal to or lower than a height of a lowermost inner electrode of the plurality of inner electrodes.”
Claim(s) 3-8 are allowed by dependence on claim 1.
Claims 2 would be allowed by dependency on claim 1 when the rejection under 35 U.S.C. 112(b) would be overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Nakamura (US 2017/0170047 A1) teaches a wafer transfer tray 42 in a support section 41 of a plasma treatment apparatus 40, it has a base 43 formed of an insulating body, a first conductive layer 44 for electrostatic attraction embedded at a position closer to one surface (a first surface) 43a than the other surface 43b of the base 43, and a conductor 45 disposed to be exposed at the other surface (a second surface) 43b of the base 43. The base 43 is constituted by a ceramic plate or the like. The first conductive layer 44 and the conductor 45 are formed of a metal, for example, aluminum, tungsten or titanium, or an alloy including these metals. The gas supply unit 25 configured to supply a cooling gas and serving as a cooling unit configured to cool the wafer transfer tray 42 is connected to the support section 41. The cooling gas supplied from the gas supply unit 25 flows along a gas flow path (not shown) formed at one surface (a first surface) 42a side of the wafer transfer tray 42 to cool the wafer transfer tray 42.
Takebayashi (US 2023/0290622 A1) teaches a member for a semiconductor manufacturing apparatus, comprising: a conductive base substrate that has a wafer-placement-table support including a circular wafer-placement-table support surface, and that has a focus-ring-placement-table support at an outer periphery of the wafer-placement-table support, the focus-ring-placement-table support including a ring-shaped focus-ring-placement-table support surface at a height that is lower than a height of the wafer-placement-table support surface; an insulating focus-ring placement table that has, at an upper surface thereof, a ring-shaped focus-ring placement surface, and that is joined to the focus-ring-placement-table support surface; an insulating wafer placement table that has, at an upper surface thereof, a circular wafer placement surface, that is separate from the focus-ring placement table, that overlaps an inner peripheral portion of the focus-ring placement surface in plan view, and that is joined to the inner peripheral portion of the focus-ring placement surface and to the wafer-placement-table support surface; a ring-shaped internal space that is surrounded by a lower surface of the wafer placement table, an outer peripheral surface of the wafer-placement-table support of the base substrate, an inner peripheral surface of the focus-ring placement table, and the focus-ring-placement-table support surface of the base substrate; and a communication path that is provided at the base substrate and that causes the internal space and an outside of the base substrate to communicate with each other.
Morioka (US 2023/0317430 A1) teaches a wafer placement table comprising: a ceramic plate including a plate annular portion that includes a focus ring placement surface which has an annular shape and which is disposed outside a plate central portion including a wafer placement surface having a circular shape; and a conductive substrate that is provided on a lower surface of the ceramic plate and that is used as a radio-frequency source electrode, wherein at a same height from the focus ring placement surface in the plate annular portion, a focus ring attraction electrode and a focus-ring-side radio-frequency bias electrode to which a bias radio frequency is supplied are embedded.
Takebayashi (US 2025/0149310 A1) teaches a member for semiconductor manufacturing apparatus includes a ceramic plate having a wafer placement surface on its upper surface and a built-in electrostatic electrode; a base plate provided on a lower surface of the ceramic plate; a passage provided from a lower surface of the base plate to the wafer placement surface of the ceramic plate; an internal electrode provided inside the ceramic plate so as to be located in a periphery of the passage under the electrostatic electrode; a switcher coupled to the internal electrode, and configured to switch between whether the internal electrode is electrically coupled to the electrostatic electrode; and a bias electrode provided at a height lower than or equal to a height of the internal electrode electrically independently from the electrostatic electrode, and configured to receive application of a bias voltage when plasma is generated over the wafer placement surface.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838