Performing a Multi-qubit Stabilizer Measurement

§101 §103

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on November 22, 2024, two files from August 14, 2024, February 20, 2025; and November 12, 2025, have been considered by the examiner. The submissions are compliant with the provisions of 37 CFR 1.97. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation includes: “means for applying a multi-qubit quantum logic gate on the stabilizer check qubit device…” in claim 24. Because this claim limitation(s) is not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof. Corresponding structure is found in paragraph [0021] noting “ the example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109, or otherwise),” of the written description specification. If applicant intends to have this limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation does not recite sufficient structure, materials, or acts to perform the claimed function. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefore, subject to the conditions and requirements of this title. Claims 1-9, 13-22, and 24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea (mental process or math ) without significantly more. Claim 1: Regarding claim 1, the claim recites “1. A method for operating a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices operably coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices, the method comprising: applying a multi-qubit quantum logic gate on the stabilizer check qubit device and the two or more data qubit devices of the superconducting quantum processing unit, the multi-qubit quantum logic gate encoding information from the two or more data qubit devices onto the stabilizer check qubit device, the encoded information usable by a quantum error correction scheme, wherein applying the multi-qubit quantum logic gate comprises evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian, the interaction Hamiltonian comprising a plurality of terms, each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices, each of the terms comprising a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices,” and in step 1 of the 101-analysis set forth in MPEP 2106, and a method is one of the four statutory categories of invention. In step 2A prong 1 of the 101-analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a math operation but for recitation of generic computer components: Regarding the limitation i. applying a multi-qubit quantum logic gate on the stabilizer check qubit device and the two or more data qubit devices of the superconducting quantum processing unit, the multi-qubit quantum logic gate encoding information from the two or more data qubit devices onto the stabilizer check qubit device, (This recites a mathematical relationship, mathematical formula or equation, or mathematical calculation, see specification paragraphs [0045] note “In some implementations, a quantum error correction code based on multi-qubit stabilizer measurements is implemented on the superconducting quantum processing unit 102A. In some implementations, applying a multi-qubit stabilizer measurement includes applying a multi-qubit quantum logic gate on qubits implemented by superconducting qubit devices. and [0073] note PNG media_image1.png 450 1025 media_image1.png Greyscale PNG media_image2.png 6 691 media_image2.png Greyscale PNG media_image2.png 6 691 media_image2.png Greyscale recites math equations when applying quantum logic gates, see MPEP 2106.04(a)(2)), Regarding the limitation ii. the encoded information usable by a quantum error correction scheme, wherein applying the multi-qubit quantum logic gate comprises evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian, the interaction Hamiltonian comprising a plurality of terms, each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices, each of the terms comprising a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices, (This recites a mathematical relationship, mathematical formula or equation, or mathematical calculation, see specification paragraph [0077] shows math operations when using an interaction Hamiltonian and Pauli operator, PNG media_image3.png 7 676 media_image3.png Greyscale PNG media_image3.png 7 676 media_image3.png Greyscale see MPEP 2106.04(a)(2)), If claim limitations, under their broadest reasonable interpretation, cover performance of the limitations as a math concept but for the recitation of generic computer components, then it falls within the math concept generic computer components, then it falls within the math concept grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: Regarding the limitation iii. A method for operating a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices operably coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices, the method comprising: … (This recites mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional element iii recites mere instructions to apply the judicial exception using generic computer components, which is not indicative of significantly more. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Claim 2: Regarding claim 2, it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 2 recites the following abstract idea: i. PNG media_image4.png 2 272 media_image4.png Greyscale (This recites a mathematical relationship, formula or equation, or calculation, see specification paragraph [0073] note PNG media_image2.png 6 691 media_image2.png Greyscale PNG media_image2.png 6 691 media_image2.png Greyscale , see MPEP 2106.04(a)(2)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 3: Regarding claim 3, it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis applied to claim 2. Further, claim 3 recites the following abstract idea: PNG media_image4.png 2 272 media_image4.png Greyscale (This recites a mathematical relationship, mathematical formula or equation, or mathematical calculation, see specification paragraph [0077] shows math operations when using an interaction Hamiltonian and Pauli operator, PNG media_image3.png 7 676 media_image3.png Greyscale PNG media_image3.png 7 676 media_image3.png Greyscale see MPEP 2106.04(a)(2)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 4: Regarding claim 4, it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 4 recites the following additional element: i. The method of claim 1, wherein each of the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler device is a tunable-frequency transmon qubit device, (In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), (In step 2B, this is also considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 5: Regarding claim 5, it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 5 recites the following additional element: i. 5. The method of claim 1, wherein the quantum error correction scheme is based on a surface error correction code., (In step 2A, prong 2, this recites an indication to a field of use or technological environment – see MPEP 2106.05(h)), (In step 2B, this also recites a field of use or technological environment – see MPEP 2106.05(h)), Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 6: Regarding claim 6, it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 6 recites the following additional elements: i. The method of claim 1, comprising: prior to applying the multi-qubit quantum logic gate, obtaining device parameters for the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler devices of the superconducting quantum processing unit; (In step 2A, prong 2, this recites mere data receiving, which is considered insignificant extra-solution activity – see MPEP 2106.05(g),). In step 2B, this insignificant extra-solution activity is well understood routine and conventional activity which includes storing and retrieving information in memory data from court case Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; – see MPEP 2106.05(d) (II)(iv)), and regarding limitation ii. and determining control parameters for applying the multi-qubit quantum logic gate to the stabilizer check qubit device and the two or more data qubit devices according to the qubit device parameters., (This recites a mental process, determining of control parameters is a process that can be performed via mind, see MPEP 2106.04(a)(2)(III)). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 7: Regarding claim 7, it is dependent upon claim 6, and thereby incorporates the limitations of, and corresponding analysis applied to claim 6. Further, claim 7 recites the following additional elements: i. 7. The method of claim 6, wherein determining the control parameters comprises: determining parking values of respective coupler flux biases for flux bias signals to deactivate the respective tunable-frequency coupler devices. ((This recites a mental process, determining of control parameters and parking values is a process that can be performed via mind, see MPEP 2106.04(a)(2)(III))). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 8: Regarding claim 8, it is dependent upon claim 7, and thereby incorporates the limitations of, and corresponding analysis applied to claim 7. Further, claim 8 recites the following additional elements: i. The method of claim 7, comprising: after applying the multi-qubit quantum logic gate, performing a qubit readout measurement on the stabilizer check qubit device; (In step 2A, prong 2, this recites mere data receiving, from obtaining readout measurements, which is considered insignificant extra-solution activity – see MPEP 2106.05(g),). (In step 2B, this insignificant extra-solution activity is well understood routine and conventional activity which includes storing and retrieving information in memory data from court case Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; – see MPEP 2106.05(d) (II)(iv)), Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 9: Regarding claim 9, it is dependent upon claim 8, and thereby incorporates the limitations of, and corresponding analysis applied to claim 8. Further, claim 9 recites the following additional elements: i. The method of claim 8, comprising: prior to performing the qubit readout measurement, applying the coupler flux biases at the parking values to the respective tunable-frequency coupler devices in parallel to deactivate the respective tunable-frequency coupler devices in parallel to deactivate the respective tunable-frequency coupler devices in parallel during a time step such that the stabilizer check qubit device is decoupled to the two or more data qubit devices during the time step, (In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), (In step 2B, this is also considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), see specification in [0120] for details, Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 13: Regarding claim 13, the claim recites “13. … A quantum computing system comprising: a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices; and a control system communicably coupled to the superconducting quantum processing unit and operable to perform operations comprising: …,” and in step 1 of the 101-analysis set forth in MPEP 2106, and a system or machine is one of the four statutory categories of invention. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: Regarding the limitation A quantum computing system comprising: a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices; and a control system communicably coupled to the superconducting quantum processing unit and operable to perform operations: … (This recites mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional element recites mere instructions to apply the judicial exception using generic computer components, which is not indicative of significantly more. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Since claim 13 recites similar limitations as corresponding independent claim 1 listed above, it is rejected for similar reasons under 35 U.S.C. 101. Claims 14-21: Since claims 14-21 recite similar limitations as corresponding claims 2-9 listed above, they are rejected for similar reasons under 35 U.S.C. 101. Claim 22: Regarding claim 22, it is dependent upon claim 18, and thereby incorporates the limitations of, and corresponding analysis applied to claim 18. Further, claim 22 recites the following additional elements: i. The system of claim 18, wherein determining the control parameters comprises: determining gate-activating values of respective coupler flux biases for flux bias signals to activate the respective tunable-frequency coupler devices, (In step 2A, prong 2, this is considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), (In step 2B, this is also considered mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), see specification in [0120] for details, Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Claim 24: Regarding claim 24, the claim recites “24. A quantum computing system comprising: a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices; and means for applying a multi-qubit quantum logic gate on the stabilizer check qubit device: …,” and in step 1 of the 101-analysis set forth in MPEP 2106, and a system or machine is one of the four statutory categories of invention. In step 2A prong 2 of the 101-analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application: Regarding the limitation i A quantum computing system comprising: a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices … (This recites mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), and limitation ii and means for applying a multi-qubit quantum logic gate on the stabilizer check qubit device: … (This recites mere instructions to apply an exception using generic computer – see MPEP 2106.05(f)), Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea. In step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, additional element i and ii recite mere instructions to apply the judicial exception using generic computer components, which are not indicative of significantly more. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible. Since claim 24 recites similar limitations as corresponding independent claim 1 listed above, it is rejected for similar reasons under 35 U.S.C. 101. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 13, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor M. et al., in “Demonstration of universal parametric entangling gates on a multi-qubit lattice,” published on February 2, 2018, available at: https://www.science.org/doi/10.1126/sciadv.aao3603, (hereafter, Reagor), in view of Andersen C. et al., in "Entanglement stabilization using ancilla-based parity detection and real-time feedback in superconducting circuits,” published on August 15, 2019, available at https://www.nature.com/articles/s41534-019-0185-4 , (hereafter, Andersen), and further in view of Terhal, B. et al., published on July 9, 2020, in “Towards scalable bosonic quantum error correction. Quantum Science & Technology,” available at: https://iopscience.iop.org/article/10.1088/2058-9565/ab98a5/pdf , (hereafter, Terhal). Claim 1: Regarding claim 1, Reagor teaches "1. A method for operating a superconducting quantum processing unit comprising a stabilizer check qubit device and two or more data qubit devices operably coupled to the stabilizer check qubit device through respective tunable-frequency coupler device…, the method comprising:" See Reagor 2018 in page 1, paragraph 3, Introduction note “here, we implement universal entangling gates via parametric control on a superconducting processor with eight qubits.” Here, Reagor shows running a superconducting processor with eight qubits (relates to running two or more data qubit devices) . Also, see Reagor in page 1, Introduction, paragraph 3 note “Further, we directly quantify the effect of the remaining six qubits of the processor on the operation of a single two-qubit CZ gate. To do so, we prepare each of the 64 classical states of the ancilla qubit register and, for each preparation, conduct two-qubit QPT. Tracing out the measurement outcomes of the ancillae results in an average estimated fidelity of ℱ = 91.6 ± 2.6% to the ideal process of CZ.” Here, the ancilla qubit register corresponds to being a stabilizer check qubit device. See last paragraph of page 2, where Reagor notes “Specifically, we characterize the behavior of each gate by reconstructing the evolution of a sufficiently large and diverse set of inputs, which corresponds to wrapping the gate by a set of pre-and post-rotations.” Here, Reagor shows a respective device or gate that operate at various inputs. See Reagor in table 1 on page 4 note “Note that the anharmonicities of the flux tunable qubits are measured at their operating frequencies,” showing different frequencies at 8 qubit device. For more information on respective tunable frequency devices, see Reagor in page 2 for details. PNG media_image5.png 583 546 media_image5.png Greyscale Further, Reagor teaches “applying a multi-qubit quantum logic gate on the stabilizer check qubit device and … of the superconducting quantum processing unit,” See Reagor 2018 in page 2, paragraph after equation 3 mention “Parametric modulation of the tunable transmon’s frequency is achieved by modulating the flux through the SQUID loop. ω depends on the flux modulation amplitude and the dc flux bias point (23). Therefore, the resonance conditions for each of the terms in Eq. 3 involve both the modulation amplitude and the frequency. The first term in Eq. 3 can be used to implement an iSWAP gate (5, 24, 31) of duration π/2gn, whereas either of the latter two terms can be used to implement a CZ gate (9, 10, 24, 32) of duration π/2gn.” Note a multi-qubit quantum logic gate is construed to mean a CNOT, swap gate, or similar synonymous terms. Here, Reagor also mentions a tunable frequency modulated by the SQUID loop flux. Further, see Reagor in pages 1-2, note in section Results “Figure 1A shows an optical image of the transmon qubit (30) quantum processor used in our experiment. The multi-qubit lattice consists of alternating tunable and fixed-frequency transmons, each capacitively coupled to its two nearest neighbors to form a ring topology (see Materials and Methods). The Hamiltonian for a coupled tunable and fixed-frequency transmon pair is well approximated by …” PNG media_image6.png 616 575 media_image6.png Greyscale Here, from equations 1-3, Reagor shows that the multi-qubit lattice has alternating tunable and fixed frequency transmons, which corresponds to a tunable-frequency coupler device. Reagor also teaches the processor used for running the quantum processing operations in figure 1. PNG media_image7.png 729 567 media_image7.png Greyscale However, Reagor did not teach “applying a multi-qubit quantum logic gate on ... and the two or more data qubit devices of the superconducting quantum processing unit” or “the multi-qubit quantum logic gate encoding information from the two or more data qubit devices onto the stabilizer check qubit device, the encoded information usable by a quantum error correction scheme,…” or “wherein applying the multi-qubit quantum logic gate comprises evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian, the interaction Hamiltonian comprising a plurality of terms, each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices”, or “each of the terms comprising a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices,” In an analogous art, Andersen teaches “the multi-qubit quantum logic gate encoding information from the two or more data qubit devices onto the stabilizer check qubit device, the encoded information usable by a quantum error correction scheme,” See Andersen mention in page 5, Discussion "Our results constitute an important step toward the real-time stabilization of entangled multi-qubit states beyond Bell states using higher-weight parity detection 33,34 as required, for example, in quantum error correction codes, such as the Bacon-Shor code60 and the surface code." Here, Andersen shows information is used by a quantum error correction scheme by a surface code or Bacon-Shor code, which is defined by paragraph [0044] in the specification written description describe " Error detection or correction mechanisms associated with a logical qubit may be based on quantum error correction schemes such as the surface code, color code, Bacon-Shor codes, low-density parity check codes (LDPC), some combination of these, or others." Therefore, quantum error correction scheme include surface code, Bacon-Shor codes, or other similar codes, which is considered encoded information. Further, Andersen teaches “… each of the terms comprising a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices,” See Andersen note in page 2, “we characterize the coherent part of the parity detection algorithm by performing quantum-state tomography of all three qubits prior to the first readout of A. Accounting for finite readout fidelity, we average this data to obtain the expectation values for all multi-qubit Pauli operators ^ P (Fig. 3a). The overall three-qubit state fidelity F=〈ψ|ρ|ψ〉≈94%, estimated based on the most likely density matrix ρ reconstructed from the measured Pauli sets,” Here, Andersen shows using the Pauli operators for the qubit device, and the operators are applied to the respective one of the qubit device, part of a system of devices. See figure 4 on page 4 for details. PNG media_image8.png 773 1342 media_image8.png Greyscale Also, see Andersen mention in page 4, paragraph 2, note ""As the ancilla is reset in every stabilization round, the Pauli frame update is only conditioned on the last two (one) parity measurements when stabilizing both ZZ and XX (only ZZ) as these two (one) measurements completely determine the corresponding Pauli frame. Thus, if the last ZZ (XX) outcome is −1,we apply a Rπ x (Rπ z) rotation to the Pauli operators of the state tomography of D2 before averaging the data and reconstructing the most likely density matrix." Here, Andersen notes the Pauli operator is applied to an ancilla (which is viewed as a stabilizer check qubit device), and Pauli operator is applied to all multi-qubit systems from page 2. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Reagor and incorporate into the teachings of Andersen because both references teach applying a multi-qubit quantum operations using stabilizer check qubit device, for quantum error correction. One of ordinary skill in the art would be motivated to do so because “ the latter approach —also known as Pauli frame updating 21—has the advantage of avoiding errors introduced by imperfect feedback and additional decoherence due to feedback latency,” (see Andersen in page 1, second paragraph of Introduction). However, Reagor in view of Andersen did not teach “applying a multi-qubit quantum logic gate on ... and the two or more data qubit devices of the superconducting quantum processing unit” or “wherein applying the multi-qubit quantum logic gate comprises evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian, the interaction Hamiltonian comprising a plurality of terms, each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices.” In an analogous art, Terhal teaches “applying a multi-qubit quantum logic gate on ... and the two or more data qubit devices of the superconducting quantum processing unit” See Terhal in page 2, first sentence, from Introduction section, note "The repetition or surface codes are the simplest examples of such further encoding steps, using then multiple oscillators...variants on who is playing the role of data and ancilla qubit and what additional error correction on these qubits takes place, are important in actually getting the very demanding engineering it, to pan out. If we have learned anything over the past 20 years of Hamiltonian engineering it is that partially-coherent dynamics can be implemented in many quantum systems," Here, Terhal mentions using multiple oscillators, which relate to using multiple devices of two or more data qubit devices of the quantum system. Also, see page 1, from Introduction, where Terhal notes “to be concrete, we concentrate on superconducting devices as physical realizations, due to the excellent control and engineerability of strong non-linearities, as described by the formalism of circuit quantum electrodynamics (circuit-QED).” Here, Terhal shows using a superconducting quantum system. Further, see page 1, abstract, where Terhal talks about "We present some new results on decoding repeated GKP error correction using finitely-squeezed GKP ancilla qubits, exhibiting differences with previously studied stochastic error models.. We discuss circuit-QED ways to realize CZ gates between GKP qubits and we discuss different scenarios for using GKP and regular qubits as building blocks in a scalable superconducting surface code architecture". Here, Terhal mentions using CZ gates between GKP qubits , which shows using multiple qubits. Further, Terhal mentions the realizing CZ gates between GKO qubits corresponds to the method of applying a multi-qubit quantum logic gate. Further, Terhal teaches “wherein applying the multi-qubit quantum logic gate comprises evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian, the interaction Hamiltonian comprising a plurality of terms, each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices, ” See Terhal in page 24 from section 4. Prospects for a GKP-surface code architecture note “ PNG media_image9.png 467 1147 media_image9.png Greyscale ” Here, Terhal shows applying an interaction Hamiltonian on all data oscillators (i.e. two or more data qubit devices) from equation 40 as well as on the ancilla device (i.e. viewed as a stabilizer check qubit device), and each of the terms from equation 40 correspond to an interaction between the ancilla device and each of the data oscillators. See figure 15, where Terhal illustrates the encoding of the ancilla qubits on a device. PNG media_image10.png 329 1028 media_image10.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor and Andersen, and incorporate with the teachings of Terhal by using the teachings of Reagor and Andersen, with Terhal' s teaching of applying an interaction Hamiltonian for the stabilizer check qubit device and respective data qubit devices. One of ordinary skill in the art would be motivated to do so because by integrating Terhal' s framework into the methods of Reagor and Andersen, one with ordinary skill in the art would achieve the goal of providing “to be concrete, we concentrate on superconducting devices as physical realizations, due to the excellent control and engineerability of strong non-linearities, as described by the formalism of circuit quantum electrodynamics (circuit-QED),” (see page 1, Introduction section in Terhal). Claim 13: Referring to claim 13, regarding “A quantum computing system comprising: … and a control system communicably coupled to the superconducting quantum processing unit and operable to perform operations…,” Further, Andersen teaches “A quantum computing system comprising: … and a control system communicably coupled to the superconducting quantum processing unit and operable to perform operations…,” See Andersen in page 4 mention "Here, we keep track of the parity measurements in software, and apply Pauli frame updating to stabilize the target subspaces. The gate sequence is then equivalent to Fig. 1, but feedback is only used for resetting the ancilla qubit after each parity measurement." Here, Andersen mentions using software, which inherently contains a processor with memory. Also, see Andersen in page 6, from Contributions describe "C.K.A. designed the device and A.R., S.K., J.-C.B. and M.G. fabricated the device. C.K.A., A.R., S.L., S.K. and J.H. set up the experiment and wrote the experimental control software." Here, Andersen mentions using control software as a form of control system. Further, claim 13 comprises of similar additional limitations as independent claim 1, and is rejected under the same rationale under 35 U.S.C. 103. Claim 24: Further, claim 24 comprises of similar additional limitations as independent claim 1, and is rejected under the same rationale under 35 U.S.C. 103. Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, and further in view of Mezzacapo, A. et al., in “Many-body interactions with tunable-coupling transmon qubits,” published on July 30, 2014, available at: https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.113.050501 , (hereafter, Mezzacapo). Claim 2: Regarding claim 2, Reagor in view of Andersen, further in view of Terhal, teach the limitations of claim 1. However, Reagor in view of Andersen, further in view of Terhal, did not teach PNG media_image4.png 2 272 media_image4.png Greyscale In an analogous art, Mezzacapo teaches PNG media_image4.png 2 272 media_image4.png Greyscale See Mezzacapo in page 1 note PNG media_image11.png 579 1366 media_image11.png Greyscale Also, see from equation 1, where Mezzacapo show using the Pauli matrix σ i α (which also relate to being a Pauli operator) that correspond to the different energy levels of the TCQ device. The Pauli matrix is the matrix representation of a Pauli operator and they are synonymous terms in this case. Also, see Mezzacapo in page 1, second paragraph note “Sequences of collective gates together with local qubit rotations can implement stabilizer operators [22,23] that can allow for the implementation of topological codes.” Here, Mezzacapo shows that the effective Hamiltonian interaction can be implemented on stabilizer operators, which are synonymous with stabilizer check devices. Further, see Mezzacapo in page 3 note PNG media_image12.png 47 240 media_image12.png Greyscale Here, Mezzacapo shows that equation 1 PNG media_image12.png 47 240 media_image12.png Greyscale has a general format similar to PNG media_image4.png 2 272 media_image4.png Greyscale . Also, see Mezzacapo in page 5 note from Conclusion that “we have shown that a setup made out of several superconducting three-island devices provided with tunable coupling to a coplanar waveguide resonator may realize collective gates and many-body interactions among superconducting qubits.” Here, Mezzacapo shows that this method is applied to various devices, and shows more than one device and can be viewed as k = 1 ,… n data qubit devices. Data qubit devices is construed to be any system that can run quantum operations. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, and Terhal and incorporate with the teachings of Mezzacapo by using the teachings of Reagor, Andersen, and Terhal, with Mezzacapo’s teaching of the interaction Hamiltonian equation. One of ordinary skill in the art would be motivated to do so because by integrating Mezzacapo’s framework into the methods of Reagor, Andersen, and Terhal, one with ordinary skill in the art would achieve “the fidelity improves as the qubit-resonator detuning increases,” (see page 4, figure 4, from Mezzacapo). Claim 14: Claim 14 comprises of similar additional limitations as corresponding claim 2, and is rejected under the same rationale under 35 U.S.C. 103. Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Mezzacapo, and further in view of Arisoy, O., et al., in "Few-qubit quantum refrigerator for cooling a multi-qubit system," published on June 21, 2021, available at https://www.nature.com/articles/s41598-021-92258-0#citeas , (hereafter, Arisoy). Claim 3: Regarding claim 3, Reagor in view of Andersen, further in view of Terhal, and further in view of Mezzacapo, teach the limitations of claim 2. Further, However, Reagor in view of Andersen, further in view of Terhal, and further in view of Mezzacapo, did not teach PNG media_image4.png 2 272 media_image4.png Greyscale In an analogous art, Arisoy teaches PNG media_image4.png 2 272 media_image4.png Greyscale See Arisoy mention from page 3, in section Thermal state for the spin-star model and effective temperature of the refrigerant qubit note “the eigenstates of the Hamiltonian in Eq. (1) are not entangled. Off-diagonal elements of the total density matrix vanish in the tensor product of the z-basis of each effective spin. Accordingly, we can treat the Ising spin-star model as a classical discrete system (with up and down spin states labeled by z = +1 and z = -1 , respectively) and study the state probability distribution described by the diagonal elements of the total density matrix.” Here, Arisoy mentions a z-basis of each effective spin and relate to Z operators. Further, see Arisoy mention on page 2 in section Model system for the preparation of the refrigerant qubits note “We consider a so-called “spin-star” system consisting of a single qubit surrounded by N ancilla qubits, as illustrated in Fig. 1. For the sake of clarity in what the word “system” refers to in the rest of the text, we will denote the whole spin-star system as system A, its central spin as system B and the many-body system to be cooled as system C. Interactions between the central qubit and the surrounding qubits are assumed to be the same, characterized by the coupling coefficient g. The energy gap of the qubit is denoted by h. We represent each qubit as an effective spin-1/2 particle and further assume that the qubit-qubit interactions are only between the z-components of the effective spins. PNG media_image13.png 260 1041 media_image13.png Greyscale As the Pauli spin operators are only for the z-components, the model can be considered a longitudinal Ising model37, but with a spin-star configuration instead of a spin chain.” When Arisoy mentions the effective spins involving z-components and z-basis, this shows that it is part of the Pauli- Z operator since the z-components are involved in Pauli spin operations. This variable could also be incorporated into the Hamiltonian interaction equation as Arisoy indicated in equation 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal and Mezzacapo, and incorporate with the teachings of Arisoy by using the teachings of Reagor, Andersen, Terhal, and Mezzacapo, with Arisoy’s teaching of the interaction Hamiltonian equation including the Pauli- Z operator. One of ordinary skill in the art would be motivated to do so because by integrating Arisoy’s framework into the methods of Reagor, Andersen, and Terhal, and Mezzacapo, one in the ordinary of skill in the art would achieve a “ scheme is suitable for cooling a small many-body system with a finite set of discrete eigenfrequencies in practice while being flexible for the cooling arbitrary sized qubit systems as the number of available qubits in a quantum system and the maximum possible number of simultaneous couplings to a single qubit increase with future technological improvements,” (see Arisoy in page 7, from Cooling of a many-body system with spin-star quantum refrigerators). Claim 15: Claim 15 comprises of similar additional limitations as corresponding claim 3, and is rejected under the same rationale under 35 U.S.C. 103. Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Kjaergaard, M. et al., in “Superconducting Qubits: Current State of Play. Annual Review of Condensed Matter,” published on December 17, 2019, available at https://doi.org/10.1146/annurev-conmatphys-031119-050605 , (hereafter, Kjaergaard). Claim 4: Regarding claim 4, Reagor in view of Andersen, further in view of Terhal, teach the limitations of claim 1. However, Reagor in view of Andersen, further in view of Terhal, did not teach “The method of claim 1, wherein each of the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler device is a tunable-frequency transmon qubit device.” In an analogous art, Kjaergaard teaches “ The method of claim 1, wherein each of the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler device is a tunable-frequency transmon qubit device.” See Kjaergaard in pages 370-371, Introduction, paragraph 2, mention "In 2014, the first controlled qubit–qubit interaction with fidelities greater than 0.99 in multiqubit systems was demonstrated (3) with the transmon qubit (4) variant of superconducting qubits, and since then, multiple controlled two-qubit interactions have been demonstrated with similarly high fidelities (see, e.g., 5, 6)...Although the architectures based purely on the transmon qubit (see Section 2.1) have not yet demonstrated logical states with longer lifetimes than their constituent physical states, multiqubit systems with on the order of 10–20 qubits have been demonstrated (14–18)," Here, Kjaergaard mentions using various qubit systems, which correspond to two or more data qubit devices. Further, see Kjaergaard in page 375, section 2.2. Gate Operations in Superconducting Qubits, note "Although the implementation of single-qubit gates is now mostly uniform across the community, many different two-qubit gates have been demonstrated, and several of those have reached fidelities >0.99. The two-qubit gates can be roughly split into three categories. One class uses tunable transmon qubits whose frequencies can be modulated by applying magnetic flux through a dc-SQUID loop that tunes the effective critical current of the Josephson junction. Several high-fidelity, two-qubit gates can be implemented by tuning certain energy levels of the tunable transmon qubits close to resonance (3, 55, 72–74; see details in Table 1 )." Here, Kjaegaard describes using a tunable frequency transmon qubit system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, and Terhal and incorporate with the teachings of Kjaegaard by using the teachings of Reagor, Andersen, Terhal, with Kjaegaard’s teaching of using a tunable frequency transmon qubit device. One of ordinary skill in the art would be motivated to do so because by integrating Kjaegaard’s framework into the methods of Reagor, Andersen, and Terhal, one with ordinary skill in the art would achieve “these encodings are attractive because they take advantage of the long lifetimes of microwave cavities (98, 99) and may enable hardware-efficient quantum error correction,” (see page 377, section 2.4. Bosonic-Encoded Qubits in Kjaegaard). Claim 16: Claim 16 comprises of similar additional limitations as corresponding claim 4, and is rejected under the same rationale under 35 U.S.C. 103. Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Yoder, T. J. et al., in “The surface code with a twist,” published on March 22, 2017, available at: https://quantum-journal.org/papers/q-2017-04-25-2/pdf/ , (hereafter, Yoder). Claim 5: Regarding claim 5, Reagor in view of Andersen, further in view of Terhal, teach the limitations of claim 1. However, Reagor in view of Andersen, further in view of Terhal, did not teach “5. The method of claim 1, wherein the quantum error correction scheme is based on a surface error correction code.” In an analogous art, Yoder teaches “5. The method of claim 1, wherein the quantum error correction scheme is based on a surface error correction code,” See Yoder in page 1, Introduction, note "The surface code is one of the most successful approaches to topological quantum error correction. It boasts the smallest known syndrome extraction circuits and correspondingly largest thresholds." Here, Yoder shows using surface code provides a successful approach to quantum error correction. Also, see Yoder in page 9, note "These designs were chosen as they satisfy reasonable criteria for a near-term fault-tolerant qubit: all use less than 20 qubits including ancillas, the connectivity between qubits required is low, and no design uses posts election to create ancillas during syndrome extraction. The triangle code performs remarkably well in the comparison, saving two or four qubits over the surface code with a drop in pseudo threshold of only 3% or 14%, respectively." Here, Yoder shows using surface code helps save two or four qubits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, and Terhal and incorporate with the teachings of Yoder by using the teachings of Reagor, Andersen, and Terhal, with Yoder’s teaching of using a tunable frequency transmon qubit device. One of ordinary skill in the art would be motivated to do so because by integrating Yoder’s framework into the methods of Reagor, Andersen, and Terhal, one with ordinary skill in the art would achieve “Moreover, the syndrome information can be processed efficiently [2, 6–8], resulting in the highest known topo logical fault-tolerance threshold [9],” (see Yoder in page 1, Introduction). Claim 17: Claim 17 comprises of similar additional limitations as corresponding claim 5, and is rejected under the same rationale under 35 U.S.C. 103. Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, J. et al., in “Resonant coupling parameter estimation with superconducting qubits," published on November 30, 2021, view in https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.2.040343 , (hereafter, Béjanin), and further in view of Sete, E. et al., in PG Pub. WO-2018236922-A1, published on December 27, 2018, (hereafter Sete_18). Claim 6: Regarding claim 6, Reagor in view of Andersen, further in view of Terhal, teach the limitations of claim 1. However, Reagor in view of Andersen, further in view of Terhal, did not teach “6. The method of claim 1, comprising: prior to applying the multi-qubit quantum logic gate, obtaining device parameters for the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler devices of the superconducting quantum processing unit;” In an analogous art, Béjanin teaches “6. The method of claim 1, comprising: prior to applying the multi-qubit quantum logic gate, obtaining device parameters for the stabilizer check qubit device, the two or more data qubit devices, and the respective tunable-frequency coupler devices of the superconducting quantum processing unit;” See Béjanin in pages 2-3, Popular summary section note “Large quantum computers, those with many physical quantum bits (qubits), require extensive calibration before they can execute algorithms. In addition, because the physical parameters of the quantum computer change in time, the calibration must be repeated regularly... We explain and experimentally demonstrate two algorithms that give us the information needed to optimize two-qubit gates and avoid errors caused by defects in the quantum device. Together, these algorithms reduce the time needed by 1 order of magnitude...Detecting and estimating the parameters of these interactions, the resonance frequency and the coupling strength, let us tune each qubit. For example, knowing the parameters of the interaction between the two qubits is essential to two-qubit gates. Moreover, knowing if there are two-level systems lets us avoid them, reducing errors.” Here, Béjanin mentions this calibration applies to two qubit devices, as well as devices that use resonance frequency and coupling strength (i.e. relates to tunable-frequency coupler devices). Examiner construes a stabilizer check qubit device to mean a system designed to measure or run quantum error correction or related operations. Here, Béjanin notes 'knowing the parameters of the interaction between the two qubits is essential to two-qubit gates', and helps to reduce errors, which shows that this applies for a stabilizer check qubit system. A "stabilizer device" or hardware implementation of stabilizers refers to a quantum system engineered specifically to measure or enforce quantum error correction. Further, see Béjanin in page 27, appendix B Qubit flux pulse, note "To increase accuracy, it is important to properly calibrate the flux pulses before the experiment, ensuring that the qubit frequency is stable. This calibration can be done, again, with pulse spectroscopy, by mapping out the qubit frequency over the length of the pulse." Here, Béjanin mentions that properly calibrating flux pulses is construed to mean finding device parameters before performing any operations or running a logic gate. In quantum computing, specifically with superconducting qubits, calibrating the flux pulses means finding and setting the precise device parameters (such as pulse amplitude, duration, and shape) before running a logic gate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, and Terhal and incorporate with the teachings of Béjanin by using the teachings of Reagor, Andersen, and Terhal, with Béjanin’s teaching of obtaining device parameters. One of ordinary skill in the art would be motivated to do so because by integrating Béjanin’s framework into the methods of Reagor, Andersen, and Terhal, one with ordinary skill in the art would achieve “can use the online and offline algorithms to efficiently detect the location and estimate the parameters of any qubit dynamics akin to a chevron pattern,” (see page 22, in section VI. Discussion, by Béjanin). However, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, did not teach “determining control parameters for applying the multi-qubit quantum logic gate to the stabilizer check qubit device and the two or more data qubit devices according to the qubit device parameters.” In an analogous art, Sete_18 teaches “determining control parameters for applying the multi-qubit quantum logic gate to the stabilizer check qubit device and the two or more data qubit devices according to the qubit device parameters,” See Sete_18 in paragraph [0036] FIG. 28 is a flowchart showing an example process for determining gate parameters for a parametrically-activated quantum logic gate." Here, Sete_18 explicitly shows determining gate parameters (i.e. viewed as analogous to control parameters) to apply logic gate to the devices. Also, see Sete_18 in paragraph [0039] describe "For instance, the gate time for a parametrically activated gate may be controlled by external control parameters, and therefore the gate may be made faster by adjusting the modulation amplitude and frequency of a control signal. Moreover, control signals that include a modulation frequency (e.g., a microwave tone) can be more robust to, or even immune to, certain control imperfections (e.g., errors associated with fast dc pulses, etc.)." Further, see Sete_18 in [00222] note "In some cases, operation 2206 can be executed as a gate calibration process, e.g., performed by a control system in a quantum computing system. For instance, the gate calibration process may select parameters of control signals that are delivered to the tunable qubit device to activate two-qubit quantum logic gates. The gate calibration process may determine gate parameters for parametrically activated quantum logic gates, for example, control parameters that correspond to a flux modulation amplitude; a flux modulation frequency; a flux modulation time (a duration); and possibly other parameters." Here, Sete_18 explicitly mentions that the gate calibration process selects control signal parameters (i.e. viewed here as analogous to determining control parameters) to apply the quantum logic gate. Sete_18 also lists the control parameters as a flux modulation frequency, time, or amplitude. Further, see Sete_18 note in [0041] In some cases, a number of different types or classes of two-qubit quantum logic gates can be parametrically activated in the same quantum processor or applied to the same two qubits, which can allow a larger selection of gates and a larger number of control optimization parameters." Here, Sete_18 *mentions applying this to two qubit devices that can be '*parametrically activated in the same quantum processor' (i.e. relate to two or more data qubit devices according to device parameters). Also, see Sete_18 mention in [0046] "In some implementations, the quantum computing system 100 can operate using gate-based models for quantum computing. According to some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, topological quantum error correction schemes can operate on a lattice of nearest-neighbor-coupled qubits. In some instances, these and other types of quantum error correcting schemes can be adapted for a two- or three-dimensional lattice of nearest- neighbor-coupled qubits, for example, to achieve fault-tolerant quantum computation." Here, Sete_18 mentions a stabilizer qubit system, since stabilizer qubit devices perform error corrections, which is an operation Sete_18 describes here, and thus relate to using a stabilizer check qubit device. Further, see Sete_18 note in [0091] “For instance, a gate calibration module may execute a calibration process that obtains qubit device parameters of the qubit devices in the quantum processor 204. The qubit device parameters may be obtained by the gate calibration process, for example, based on measurements of the quantum processor 204, based on a circuit specification of the quantum processor 204, based on analytical or numerical calculations, or otherwise. The qubit device parameters may include, for example, qubit frequencies (e.g., a tunable range) and an anharmonicity for each tunable qubit device; a qubit frequency and anharmonicity for each respective fixed-frequency qubit devices; effective coupling strengths; dispersive shifts; etc. Based on the qubit device parameters, the calibration process may select gate parameters of a two-qubit quantum logic gate for application to pairs of qubits defined by pairs of devices”. Here, Sete_18 lists the elements of qubit device parameters, and based on the device parameters, this method then select gate parameters, (i.e. which are viewed as determining control parameters for applying the multi-qubit quantum logic gate). Also, see Sete_18, note in [0053] "In the example shown in FIG. 1, the signal delivery system 106 provides communication between the control system 110 and the quantum processor 102. For example, the signal delivery system 106 can receive control signals from the control system 110 and deliver the control signals to the quantum processor 102. In some instances, the signal delivery system 106 performs preprocessing, signal conditioning, or other operations to the control signals before delivering them to the quantum processor 102.” Here, Sete_18 mentions this step of preprocessing, which includes gathering device parameters, is performed before running quantum operations like logic gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal, and Béjanin, and incorporate with the teachings of Sete_18 by using the teachings of Reagor, Andersen, Terhal, and Béjanin, with Sete_18’s teaching of determining control parameters for applying the multi-qubit quantum logic gate to the stabilizer check qubit device and the two or more data qubit devices according to the qubit device parameters. One of ordinary skill in the art would be motivated to do so because by integrating Sete_18’s framework into the methods of Reagor, Andersen, Terhal, and Béjanin, one with ordinary skill in the art would achieve “The filter can improve operation of parametrically-activated quantum logic gates, for example, by increasing the dephasing time under modulation around the "sweet spot" by filtering out white flux noise,” (see Sete_18 in [0055]). Claim 18: Claim 18 comprises of similar additional limitations as corresponding claim 6, and is rejected under the same rationale under 35 U.S.C. 103. Claims 7, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, and further in view of Sete, Eyob A. et al. in PG Pub. No. WO2021178562A1 published on September 10, 2021, (hereafter, Sete_patent_21). Claim 7: Regarding claim 7, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, and further in view of Sete_18, teach the limitations of claim 6. However, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, and further in view of Sete_18, did not teach “7. The method of claim 6, wherein determining the control parameters comprises: determining parking values of respective coupler flux biases for flux bias signals to deactivate the respective tunable-frequency coupler devices.” In an analogous art, Sete_patent_21 teaches “7. The method of claim 6, wherein determining the control parameters comprises: determining parking values of respective coupler flux biases for flux bias signals to deactivate the respective tunable-frequency coupler devices,” See Sete_patent_21 in paragraph [00135] note “as shown in FIG. 5C, the total coupling strength crosses zero (e.g., g = 0) at a coupler flux bias value of 0.22 F0. At this coupler flux bias value (e.g., <Pec = ±0.22F0) , the coupling between the first and second tunable floating qubit devices 402, 404 is deactivated. As the magnitude of the coupler flux bias increases, the total coupling strength g increases, reaching a maximum absolute value at a coupler flux bias of <Pec = ±0.5F0. In some instances, when operating at a coupler flux bias of <Pec = 0, the value of the frequency of the tunable floating coupler device 406 is at its maximum value. In some instances, when operating at a coupler flux bias of <Pec = ±0.5F0, the value of the frequency of the tunable floating coupler device 406 is at its minimum value. In some instances, the <Pec = ±0.22F0 is the parking value of the coupler flux bias and the <Pec = ±0.5F0 is a gate-activating value of the coupler flux bias. By adjusting the value of the coupler flux bias from the parking value to the gate-activating value, the total coupling can be turned on when preparing the tunable floating qubit devices for quantum logic gates; and when the quantum logic gates are completed, the value of the coupler flux bias can be tuned back to the parking value to turn off the coupling between the two tunable floating qubit devices 402, 404, e.g., suppress cross-talk between the two tunable floating qubit devices 402, 404.” Here, Sete_patent_21 mentions that at the coupler flux bias value of <Pec = ±0.22F0, the coupling between first and second tunable qubit devices is deactivated or switched off, and Sete_patent_21 explicitly shows that by adjusting the value of the coupler flux bias from parking value to gate-activating value, the total coupling can be turned on or switched off between the two qubit devices, and shows a parking value for a flux bias signal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal, Béjanin, and Sete_18, and incorporate with the teachings of Sete_patent_21 by using the teachings of Reagor, Andersen, Terhal, Béjanin, and Sete_18, with Sete_patent_21’s teaching of determining parking values of respective coupler flux biases for flux bias signals to deactivate the respective tunable-frequency coupler devices. One of ordinary skill in the art would be motivated to do so because by integrating Sete_patent_21’s framework into the methods of Reagor, Andersen, Terhal, Béjanin, and Sete_18 one with ordinary skill in the art would achieve “The systems and techniques presented here can reduce sensitivity of the tunable floating qubit devices 402, 404 to flux noise thereby improving their coherence times,” (see Sete_patent_21 in [00121]). Claim 19: Regarding claim 19, it comprises of similar additional limitations as corresponding claim 7, and is rejected under the same rationale under 35 U.S.C. 103. Claim 22: Regarding claim 22, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, and further in view of Sete_18, teach the limitations of claim 18. However, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, and further in view of Sete_18, did not teach “22. The system of claim 18, wherein determining the control parameters comprises: determining gate-activating values of respective coupler flux biases for flux bias signals to activate the respective tunable-frequency coupler devices.” In an analogous art, Sete_patent_21 teaches “22. The system of claim 18, wherein determining the control parameters comprises: determining gate-activating values of respective coupler flux biases for flux bias signals to activate the respective tunable-frequency coupler devices,” See Sete_patent_21 in paragraph [00135] note “as shown in FIG. 5C, the total coupling strength crosses zero (e.g., g = 0) at a coupler flux bias value of 0.22 F0. At this coupler flux bias value (e.g., <Pec = ±0.22F0) , the coupling between the first and second tunable floating qubit devices 402, 404 is deactivated. As the magnitude of the coupler flux bias increases, the total coupling strength g increases, reaching a maximum absolute value at a coupler flux bias of <Pec = ±0.5F0. In some instances, when operating at a coupler flux bias of <Pec = 0, the value of the frequency of the tunable floating coupler device 406 is at its maximum value. In some instances, when operating at a coupler flux bias of <Pec = ±0.5F0, the value of the frequency of the tunable floating coupler device 406 is at its minimum value. In some instances, the <Pec = ±0.22F0 is the parking value of the coupler flux bias and the <Pec = ±0.5F0 is a gate-activating value of the coupler flux bias. By adjusting the value of the coupler flux bias from the parking value to the gate-activating value, the total coupling can be turned on when preparing the tunable floating qubit devices for quantum logic gates; and when the quantum logic gates are completed, the value of the coupler flux bias can be tuned back to the parking value to turn off the coupling between the two tunable floating qubit devices 402, 404, e.g., suppress cross-talk between the two tunable floating qubit devices 402, 404.” Here, Sete_patent_21 mentions that at the coupler flux bias value of <Pec = ±0.22F0, the coupling between first and second tunable qubit devices is deactivated or switched off, and Sete_patent_21 explicitly shows that by adjusting the value of the coupler flux bias from parking value to gate-activating value, the total coupling can be turned on or switched off between the two qubit devices, and shows a parking value for a flux bias signal. Here, Sete_patent_21 mentions getting a gate-activating value to prepare the qubit devices for quantum logic gates so the coupler flux bias can be tuned back (i.e. or activate the respective tunable-frequency coupler devices) for flux bias signals. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal, Béjanin, and Sete_18, and incorporate with the teachings of Sete_patent_21 by using the teachings of Reagor, Andersen, Terhal, Béjanin, and Sete_18, with Sete_patent_21’s teaching of determining parking values of respective coupler flux biases for flux bias signals to deactivate the respective tunable-frequency coupler devices. One of ordinary skill in the art would be motivated to do so because by integrating Sete_patent_21’s framework into the methods of Reagor, Andersen, Terhal, Béjanin, and Sete_18 one with ordinary skill in the art would achieve “The systems and techniques presented here can reduce sensitivity of the tunable floating qubit devices 402, 404 to flux noise thereby improving their coherence times,” (see Sete_patent_21 in [00121]). Claims 8 and 20 are rejected as being unpatentable under 35 U.S.C. 103 over Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, and further in view of Hilder, J. et al., in “Fault-tolerant parity readout on a shuttling-based trapped-ion quantum computer,” published on July 13, 2021, available at: https://arxiv.org/pdf/2107.06368 , (hereafter, Hilder). Claim 8: Regarding claim 8, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, teach the limitations of claim 7. However, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, did not teach “8. The method of claim 7, comprising: after applying the multi-qubit quantum logic gate, performing a qubit readout measurement on the stabilizer check qubit device.” In an analogous art, Hilder teaches “8. The method of claim 7, comprising: after applying the multi-qubit quantum logic gate, performing a qubit readout measurement on the stabilizer check qubit device,” See page 7, where Hilder mentions “Beyond their relevance in the context of FT QEC, our results demonstrate the capability of realizing multi-qubit quantum protocols with effective all-to-all connectivity on a shuttling-based quantum processor architecture.” Here, Hilder mentions applying this in the setting of multi qubit devices. Also, see Hilder on page 2, section Fault tolerant parity check measurement, note “Here, we focus on the experimental verification of a flag-based FT weight-4 parity check, gz = Z1Z2Z3Z4, according to the circuit shown in Fig. 1c. The gx parity check is equivalent, as it merely requires mapping the data qubits by local rotations to the X basis before syndrome readout.” Here, Hilder mentions the operation mapping data qubits by local rotations before readout (here readout is viewed as a measurement). Here, Hilder describes the method of applying the necessary quantum logic gates to encode the parity information, and then read out the stabilizer to check qubit measurements. See Hilder on page 2, section Shuttling-Based Trapped-Ion Platform, also note “A special feature of our protocol is that we establish the required effective all-to-all connectivity by reordering the register via physical rotation of two commonly confined ions. This operation is equivalent to a unit-fidelity SWAP logic gate [68] and contrasts with faulty radiation-driven SWAP gates.” Here, Hilder shows applying a logic gate as part of the method from page 2, section Fault tolerant parity check measurement. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal, Béjanin, Sete_18, and Sete_patent_21, and incorporate with the teachings of Hilder by using the teachings of Reagor, Andersen, Terhal, Béjanin, Sete_18, and Sete_patent_21, with Hilder’s teaching of after applying the multi-qubit quantum logic gate, performing a qubit readout measurement on the stabilizer check qubit device. One of ordinary skill in the art would be motivated to do so because by integrating Hilder’s framework into the methods of Reagor, Andersen, Terhal, Béjanin, Sete_18, and Sete_patent_21, one with ordinary skill in the art would achieve “results demonstrate the capability of realizing multi-qubit quantum protocols with effective all-to-all connectivity on a shuttling-based quantum processor architecture,” (see Hilder in page 7, first paragraph). Claim 20: Regarding claim 20, it comprises of similar additional limitations as corresponding claim 8, and is rejected under the same rationale under 35 U.S.C. 103. Claims 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, further in view of Hilder, and further in view of Versluis R. et al. US20210279134-A1, Method for executing a quantum error correction cycle in a quantum computer; published on September 9, 2021, (hereafter, Versluis). Claim 9: Regarding claim 9, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, further in view of Hilder, teach the limitations of claim 8. However, Reagor in view of Andersen, further in view of Terhal, further in view of Béjanin, further in view of Sete_18, further in view of Sete_patent_21, further in view of Hilder, did not teach “9. The method of claim 8, comprising: prior to performing the qubit readout measurement, applying the coupler flux biases at the parking values to the respective tunable-frequency coupler devices in parallel to deactivate the respective tunable-frequency coupler devices in parallel during a time step such that the stabilizer check qubit device is decoupled to the two or more data qubit devices during the time step” In an analogous art, Versluis teaches “9. The method of claim 8, comprising: prior to performing the qubit readout measurement, applying the coupler flux biases at the parking values to the respective tunable-frequency coupler devices in parallel to deactivate the respective tunable-frequency coupler devices in parallel during a time step such that the stabilizer check qubit device is decoupled to the two or more data qubit devices during the time step” See Versluis in paragraphs [0024-0025] note " Solutions are known to perform single-qubit gates (Hadamard gates) in the QEC cycle for a large number of qubits. The single-qubit gates can be executed in parallel for a large number of qubits, for example as described in US2009/0015317. The present invention includes a control system, known per se, to perform single-qubit gates, such as Hadamard gates, synchronized with the two-qubit gates. In some papers discussing the QEC cycle it is assumed that the entangling gates for the X-stabilizers and for the Z-stabilizers are done simultaneously. To be more specific, in these theoretical implementations, the first entangling gate for the X-stabilizers is done simultaneously with the first entangling gate for the Z-stabilizers, also for the second, third and fourth entangling gates. Then, measurement of the X-ancillary qubits and Z-ancillary qubits are also performed simultaneously. This parallelization is a logical approach because it minimizes the amount of consecutive gates that needs to be done, thereby minimizing the total duration of a QEC cycle." Here, Versluis shows the coupler devices work operations in parallel. Later, see Versluis in [0088] note "Within the plurality of physical qubits, logical qubits may be defined by performing stabilizer measurements according to the method described for example in [A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland—Surface codes: Towards practical large-scale quantum computation, phys. rev. A 86, 032324 (2012)]. These may be planar qubits or defect qubits. Operations on these logical qubits are generally performed by switching on and off (select or de-select) stabilizer measurements for specific ancillary qubits." Here, Versluis shows that the operations (that can be performed in parallel described from paragraphs [0024-25]) from the logic qubit stabilizer devices can be switched on or off. Here, switching off means deactivating. Further, see Versluis in [0033] note "Qubit measurements and qubit gates can be pipelined to minimize the overall cycle time of a quantum error correction cycle. In an embodiment a conditional phase gate is provided as an entangling gate in the QEC cycle." Here, Versluis describes a time cycle for performing quantum error correction, which includes total duration to run the quantum error correction operations. Further, see Versluis in [0020] describe " FIG. 15 bottom shows the spectrum of single excitations for a two-qubit system. The horizontal axis is a measure for the flux control signal responsible for the detuning of the qubit frequency....by pulse-tuning one of the two-qubits close to this avoided crossing (indicated by the Roman numeral II on the horizontal axis), keeping the detuned qubit at the interaction frequency for a specific amount of time and tuning the qubit away from this interaction frequency, the ZZ interaction generates the required CZ gate. FIG. 15 further shows an example of a typical pulse profile for generating the CZ gate. Generally a calibration is required to determine the optimum pulse shape. A typical duration of the flux pulse may, for example, be between 2 and 100 ns." Here, Versluis describes a time step duration may be between 2 and 100 ns. Versluis also mentions this applies to a two-qubit system (i.e. two or more data qubit devices). From paragraphs [0024-25], Versluis mentions this applies to the measurement of the X-ancillary qubits and Z-ancillary qubits are also performed simultaneously. See figure 15 where Versluis illustrates that a qubit device is decoupled over time. PNG media_image14.png 449 673 media_image14.png Greyscale Also, see Versluis mention in paragraph [0090] "The isolation value of the switches must be good enough to decouple the current/voltage source input signal from the Josephson-junctions in the qubit, typical values may be between 50 and 120 dB. The switches must be fast enough and accurately timed between the pulses by the control system. Rise and fall time may typically be between 10 ps and 10 ns, depending on the duration of the CZ gates and timing accuracy may also typically be between 10 ps and 10 ns, depending on the dead-time between consecutive CZ pulses." Here, Versluis also mention the process is applied to decoupling. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references of Reagor, Andersen, Terhal, Béjanin, Sete_18, Sete_patent_21, and Hilder, and incorporate with the teachings of Versluis by using the teachings of Reagor, Andersen, Terhal, Béjanin, Sete_18, Sete_patent_21, and Hilder, with the teaching of Versluis in after applying the coupler flux biases at the parking values to the respective tunable-frequency coupler devices in parallel to deactivate the respective tunable-frequency coupler devices during a time step where a qubit device is decoupled over time. One of ordinary skill in the art would be motivated to do so because by integrating the framework of Versluis into the methods of Reagor, Andersen, Terhal, Béjanin, Sete_18, Sete_patent_21, and Hilder, one with ordinary skill in the art would achieve “further advantages … include a flux control scheme that is compatible with logical operations (both single- and two-qubit) for both planar- and defect-type logical qubits; and a flux control scheme that optimizes use of coherence sweet-spots,” (see Versluis in [0035]). Claim 21: Regarding claim 21, it comprises of similar additional limitations as corresponding claim 9, and is rejected under the same rationale under 35 U.S.C. 103. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WENWEI ZENG whose telephone number is (571)272-7111. The examiner can normally be reached Monday-Friday, 8am-5pm. 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