Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 3-4, 6-7, 12, 15 & 16 are objected to because of the following informalities: The following claims are objected to because of informalities and improper terminology. Appropriate correction is required.
Claim 3 is objected to because it recites “module the blanking time value.” The term “module” is improper in this context and appears to be a typographical error. For purposes of examination, the Examiner interprets this limitation to mean “modulate the blanking time value.”
Claims 4 and 12 are objected to due to improper claim grammar separating a current source from the current it provides.For purposes of examination, the Examiner interprets the recited limitations as a single current source configured to provide a charging current proportional to the predefined set current.
Claims 6, 7, 15, and 16 are objected to because they recite a “non-inverting output” or an “inverting output” of a comparator. A comparator does not have inverting or non-inverting outputs; rather, it has inverting and non-inverting inputs.For purposes of examination, the Examiner interprets these limitations as referring to the non-inverting input or inverting input of the respective comparator.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1–18: The term “stage” lacks adequate written description support. The specification never uses “stage” in this context and provides no description of any distinct stage structure. For example, the original specification disclose in paragraphs [0012]–[0015], [0028]–[0048], [0060]–[0071], and [0083]–[0096] a functional components (e.g., comparators, capacitor, current sources, AND gate) but do not disclose any “compare stage,” “output stage,” or “blanking time stage” as recited.
Claims 1 & 9: The limitations regarding “determining that a blanking time value is higher than a predefined reference value” and “generating/modulating the blanking time value” lack written description support. The specification discloses comparing a timer capacitor voltage to a reference voltage (e.g., the original specification disclose in paragraphs [0036], [0041]–[0042], [0088]–[0090]) and modulating discharge time via current sources (e.g., and [0024]–[0027], [0033]–[0035], [0103]–[0104]), but does not describe generating, comparing, or modulating a separate “blanking time value” as a distinct entity or parameter.
Claims 17 &18: The claims recite a computer program product comprising a non-transitory computer-readable medium with instructions. The specification lacks written description and enablement support. It describes only analog hardware circuitry (see original specification paragraphs [0012]–[0104]) and provides no disclosure of software, instructions, algorithms, processor, memory, or execution details. The single conclusory reference in [0072] is insufficient.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 7, 9-11 & 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites a compare stage, a blanking time stage, and an output stage.
The specification does not define or describe what constitutes a “stage.” The specification discloses individual circuit components, such as comparators, current sources, capacitors, logic gates, and switches (see paragraphs [0028]–[0032], [0036], [0040]–[0046], [0091]–[0096]), but does not disclose any structural or functional grouping of such components into a “compare stage,” “blanking time stage,” or “output stage.”
Further, claim 1 recites determining that a blanking time value is higher than a predefined reference value. The specification discloses comparing a voltage across a timer capacitor to a predefined reference voltage using a comparator (see paragraphs [0036], [0041]–[0042], [0087]–[0089]). The specification does not disclose a blanking time value as a signal, variable, or parameter, nor does it disclose comparing a time value to a reference value.
Accordingly, the specification’s disclosure of voltage comparison does not match the claimed determination of a time value being higher than a reference value, rendering the scope of claim 1 indefinite.
Claim 2 recites that the blanking time value is inversely proportional to a magnitude by which the load current exceeds a predefined set current.
The specification states, in paragraph [0024], that “in an example” the blanking time value is inversely proportional to the overcurrent magnitude. However, the specification does not disclose any mathematical expression, circuit topology, control loop, or algorithm that enforces inverse proportionality. The disclosed implementation describes capacitor charging and discharging behavior driven by current sources (see paragraphs [0034]–[0036], [0084]–[0086]) but does not disclose how such behavior results in inverse proportionality. Because the specification merely asserts inverse proportionality without defining or implementing it, the disclosure does not clearly support the claimed limitation, and the scope of claim 2 is indefinite.
Claim 4 recites a first current source and separately recites a current provided by the first current source that is proportional to the predefined set current.
The specification discloses that a current source may be proportional to a predefined set current (see paragraphs [0030], [0035], [0085]). However, the specification does not disclose how such proportionality is implemented, nor does it define the proportional relationship. The claim grammar separates the current source from the current it provides, creating ambiguity as to whether the proportional current is a separate element or a functional result. Because the relationship between the current source and the proportional current is not clearly defined in the claim or fully described in the specification, the scope of claim 4 is indefinite.
Claim 7 recites a second comparator having an inverting output and an output stage. The specification discloses a second comparator comparing load current and predefined set current (see paragraphs [0044], [0093]–[0095]). However, the specification does not disclose an “inverting output” of a comparator. The comparator outputs a logical signal; inverting and non-inverting characteristics apply to inputs, not outputs.
Further, the specification discloses an AND gate generating an overcurrent signal (see paragraphs [0045]–[0046], [0096]), but does not define or identify this circuitry as an “output stage.”
Because the claim terminology does not match the disclosed comparator structure and because “output stage” is undefined, the scope of claim 7 is indefinite.
Claim 9 is a method claim reciting steps performed by a compare stage and a blanking time stage. The specification does not disclose stages performing method steps. Instead, the specification describes analog circuit behavior such as capacitor charging and comparator switching (see paragraphs [0034]–[0036], [0086]–[0090]). The specification does not disclose any sequence of method steps executed by a stage, nor does it disclose control logic mapping stages to method operations. Because the actor performing each method step is unclear and not supported by the specification, the scope of claim 9 is indefinite.
Claim 10 depends from claim 9 and recites modulating a blanking time value.
The specification discloses capacitor discharge rates changing based on current magnitude (see paragraphs [0034]–[0036], [0103]–[0104]). However, the specification does not disclose a blanking time value as a parameter being modulated, nor does it disclose a stage performing a modulation step. Accordingly, the specification’s disclosure does not match the claimed limitation, and the scope of claim 10 is indefinite.
Claim 11 depends from claim 9 and recites controlling output based on a determination. The specification discloses that a comparator output may trigger an AND gate to generate an overcurrent signal (see paragraphs [0045]–[0046], [0096]). However, the specification does not disclose a method step of controlling output in response to a determination performed by a stage. Because the specification discloses only circuit behavior and not a method step performed by a stage, the scope of claim 11 is indefinite.
Claim 12 recites limitations similar to claim 4 regarding current sources and proportional current. As discussed with respect to claim 4, the specification discloses proportional current sources in general terms (see paragraphs [0030], [0035], [0085]) but does not disclose how proportionality is implemented or enforced. The claim grammar further obscures the relationship between the current source and the proportional current. Accordingly, claim 12 is indefinite.
Claim 13 depends from claim 12 and continues to rely on stage-based terminology. The specification does not disclose a stage performing the recited functions, nor does it define how such a stage is formed or operates (see paragraphs [0028]–[0032], [0040]–[0046]). Therefore, the scope of claim 13 remains indefinite.
Claim 14 further limits claim 13. Although the specification discloses a third current source (see paragraphs [0037]–[0039], [0091]–[0094]), the claim continues to rely on undefined stage terminology and does not clarify how the additional limitation is implemented within a stage. Accordingly, claim 14 is indefinite.
Claim 15 recites comparator outputs using improper terminology and relies on an output stage. The specification discloses comparator inputs and outputs as logical signals (see paragraphs [0041]–[0042], [0093]–[0096]) but does not disclose inverting or non-inverting outputs. The specification also does not define an output stage. Because the claim language does not match the disclosed circuitry, the scope of claim 15 is indefinite.
Claim 16 is a method claim corresponding to claim 15. The specification does not disclose method steps performed by stages, nor does it disclose executing such steps via software or control logic. The disclosure is limited to analog circuit behavior (see paragraphs [0034]–[0036], [0086]–[0096]). Accordingly, claim 16 is indefinite.
Examiner Interpretation for Purposes of Examination
For purposes of examination, the Examiner has interpreted unclear claim language in the broadest reasonable manner consistent with the specification and the understanding of one of ordinary skill in the art.
Specifically:
“Stage” is interpreted as a functional grouping of circuit components.
“Blanking time value” is interpreted as a time duration derived from capacitor behavior.
Comparator output terminology is interpreted as referring to comparator inputs.
However, even under these interpretations, the specification disclosures in paragraphs [0024], [0028]–[0036], [0040]–[0046], and [0084]–[0096] do not clearly support the claimed limitations. Therefore, the claims remain indefinite under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rigoni et al. (U.S. 2024/0079867 A1) in view of Zhang et al. (U.S. 2010/0328831 A1).
Regarding claim 1, Rigoni et al. disclose an over current protection circuit arranged for providing an over current signal (over-current protection circuitry controlling disconnect switch (S51) S1, paragraphs [0065], [0082]); a compare stage arranged for determining that a blanking time value is higher than a predefined reference value (comparator 535 comparing capacitor voltage VCINT to threshold VREF to determine expiration of timing window, paragraphs [0124], [0174]); an output stage arranged for outputting the over current signal based on the determination (gate driver logic that shuts off switch (S51) S1 upon comparator output, paragraphs [0124], [0147]); and a blanking time stage arranged for generating the blanking time value (timing control circuitry 151 implementing TBLANK using external RC components and capacitor charging, paragraphs [0057], [0099]–[0106]). Rigoni et al. further disclose that the blanking time stage is arranged to start generating the blanking time value upon a load current exceeding a predefined set current (OCP monitoring activated after startup and blanking, current IDS exceeding threshold TL1, paragraphs [0101], [0125]).
Rigoni et al. do not explicitly disclose that the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.
Zhang et al. disclose the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current (see [0035], wherein modulating (via modulation PWM, see [0133]) a timing value based on a magnitude by which a current exceeds a predefined current threshold by measuring the time between activation of a switch (S51) and triggering of a comparator, wherein larger overcurrent magnitudes cause the comparator to trigger sooner; wherein timer 106 measuring response time between switch (S51) activation and comparator trigger, paragraphs [0027] &[0036]; Zhang et al. further disclose that this magnitude-dependent timing is used to control over-current protection behavior, see paragraph [0037], Fig. 1).
It therefore would have been obvious to one skilled in the art, prior to the effective filing date, to modify Rigoni et al. by incorporating magnitude-dependent modulation of the blanking time value as taught by Zhang et al., as doing so would enable adaptive protection response proportional to over-current severity and improve protection reliability during rapid runaway current conditions (see Zhang’s paragraphs [0035]–[0037]).
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Regarding claim 2, Rigoni et al. disclose modulating (via modulation PWM, see [0133]) a blanking time value using capacitor-based timing circuitry (TBLANK generated via RC components coupled to IN pin, paragraphs [0099]–[0106]).
Rigoni et al. do not explicitly disclose that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current.
Zhang et al. disclose that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current (see Fig. 1, wherein as the magnitude of the over-current increases, the time between switch (S51) activation and comparator triggering decreases; measurement of response time using timer 106, paragraphs [0035], [0036]); under the broadest reasonable interpretation, this teaches an inverse proportional relationship between over-current magnitude and a timing interval).
It therefore would have been obvious to one skilled in the art to modify Rigoni et al. such that the blanking time value is inversely proportional to the over-current magnitude as taught by Zhang et al., thereby providing faster protective response for more severe over-current conditions (see Zhang’s paragraphs [0035]–[0037]).
Regarding claim 3, Rigoni et al. disclose generation of a blanking time value using RC-based timing circuitry (see paragraphs [0057] & [0060]).
Rigoni et al. do not disclose that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current.
Zhang et al. disclose the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current (wherein Zhang disclose the nonlinear current growth behavior and nonlinear timing response under runaway over-current conditions, including equations demonstrating nonlinear dependence of current increase on timing parameters, see paragraphs [0032], [0033]; under BRI, this teaches nonlinear modulation of timing behavior as a function of over-current magnitude, encompassing square-law proportional relationships).
It therefore would have been obvious to apply Zhang et al.’s nonlinear magnitude-based timing modulation to Rigoni et al.’s blanking time stage to enhance protection accuracy under high-severity over-current events (see Zhang’s paragraphs [0032]–[0035]).
Regarding claim 4, Rigoni et al. and Zhang et al. disclose the over current protection circuit in accordance with claim 1, wherein Rigoni et al. further disclose a blanking time stage comprising a timer capacitor (C1, see [0149]) arranged for storing energy (capacitor CINT, paragraphs [0123], [0174]); a first current source arranged for charging the timer capacitor (C1, see [0149]) (current 505-2 charging CINT, paragraph [0123]); a current provided by the first current source that is proportional to the predefined set current (charging current controlled by resistor R1 and threshold configuration, paragraphs [0132]–[0135]); a second current source arranged for discharging the timer capacitor (C1, see [0149]) (discharge paths via logic and switch (S51)ing, paragraphs [0113], [0149]); and an output of the timer capacitor (C1, see [0149]) connected to the compare stage (VCINT compared to VREF by comparator 535, paragraph [0124]).
Regarding claim 5, Rigoni et al. and Zhang et al. disclose the over current protection circuit in accordance with claim 4, wherein Rigoni et al. further disclose a third current source for discharging the timer capacitor (C1, see [0149]), wherein the third current source provides a constant current (constant current source 599 charging capacitor CINT at a fixed rate, paragraphs [0176]).
Regarding claim 6, Rigoni et al. and Zhang et al. disclose the over current protection circuit in accordance with claim 4, wherein Rigoni et al. further disclose a compare stage comprising a first comparator having an inverting input connected to the output of the timer capacitor (C1, see [0149]) and a non-inverting input connected to a predefined reference value (comparator 535 comparing VCINT to VREF, paragraphs [0124], [0174]).
Regarding claim 7, Rigoni et al. and Zhang et al. disclose the over current protection circuit in accordance with claim 5, wherein Rigoni et al. further disclose a second comparator arranged to receive a predefined set current and a load current (Vds fault comparator monitoring IDS relative to threshold TL1, paragraphs [0118], [0124]); and an AND port arranged for receiving an output stage comprising logic that outputs an over current signal based on outputs of two comparators wherein the AND port has an output that is the over current signal (logic controlling switch (S51) S1 shutoff, paragraphs [0124], [0147]).
Regarding claim 8, Rigoni et al. and Zhang et al. disclose the over current protection circuit in accordance with claim 7, wherein Rigoni et al. further disclose a switch (S51) connected in series with a constant current source for activating and deactivating the current source, wherein the switch (S51) is controlled by a comparator output of the second comparator (switch (S51) S55 controlling constant current source 599 based on comparator logic, paragraphs [0174]–[0176]).
Regarding claim 9, Rigoni et al. and Zhang et al. disclose method for providing an over current signal using an over current protection circuit in accordance with claim 1, wherein Rigoni et al. further disclose a method for providing an over current signal including determining that a blanking time value exceeds a predefined reference value (see paragraphs [0101]), outputting an over current signal, and generating, by the blanking time stage, the blanking time value, wherein the blanking time value is started to be generated upon a load current exceeding a predefined set current, wherein the step of generating comprises modulating (via modulation PWM, see [0133]) the blanking time value based on a magnitude in which the load current exceeds the predefined set current (see paragraphs [0124] & [0149]).
Regarding claim 10, Rigoni et al. and Zhang et al. disclose the method in accordance with claim 9, wherein Rigoni et al. further disclose the step of modulating (via modulation PWM, see [0133]) further comprises: modulating (via modulation PWM, see [0133]) the blanking time value so that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current (see paragraphs [0078] & [0101 ).
Regarding claim 11, , Rigoni et al. and Zhang et al. disclose the method in accordance with claim 9, wherein Rigoni et al. further disclose wherein the step of modulating (via modulation PWM, see [0133]) further comprises: modulating (via modulation PWM, see [0133]) the blanking time value so that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current (see paragraphs [0141] & [0146]).
Regarding claim 12, Rigoni et al. and Zhang et al. disclose the method in accordance with claim 9, wherein Rigoni et al. further disclose a timer capacitor (C1, see [0149]), first current source proportional to set current, second current source proportional to load current, and capacitor output connected to a compare stage (see paragraphs [0124] & [0167]).
Regarding claim 13, Rigoni et al. and Zhang et al. disclose the method in accordance with claim 10, wherein Rigoni et al. further disclose the recited timer capacitor (C1, see [0149]) and a current provided by the first current source is proportional to the predefined set current; a second current source arranged for discharging the timer capacitor; a current provided by the second current source is proportional to the load current; and an output of the timer capacitor is connected to the compare stage (see paragraphs [0123]–[0135]).
Regarding claim 14, Rigoni et al. and Zhang et al. disclose the method in accordance with claim 12, wherein Rigoni et al. further disclose the blanking time stage further comprises: a third current source for discharging the timer capacitor (see [0174]), wherein the third current source provides a current that is constant (current source 599, paragraph [0176]).
Regarding claim 17, Rigoni et al. and Zhang et al. disclose the controller to implement a method in accordance with claim 9, wherein Rigoni et al. further disclose a non-transitory computer readable medium (see [0032]) having instructions stored thereon which, when executed by a controller (see controller 140 executing timing control circuitry 151, paragraphs [0054], [0178]–[0179]).
Regarding claim 18, Rigoni et al. and Zhang et al. disclose the controller to implement a method in accordance with claim 10, wherein Rigoni et al. further disclose computer program product (see [0032]) comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller (timing control circuitry 151, paragraphs [0057], [0178]).
Allowable Subject Matter
Claims 15-16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
In terms of claim 15, the prior art of record does not teach alone or in combination of “a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value; a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current; a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator; wherein the output circuit comprises: an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal” in combination with all other elements in claims 1, 9 & 12.
In terms of claim 16, the prior art of record does not teach alone or in combination of “a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value; a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current; a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator; wherein the output circuit comprises: an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal” in combination with all other elements in claims 1, 9 & 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2010/0026268 A1 to Change et al. disclose a control method for adjusting leading edge blanking time in a power converting system is disclosed. The control method includes: receiving a feedback signal relative to a load connected to an output terminal of the power converting system; determining the leading edge blanking time to be a first value if the feedback signal has a magnitude about a first voltage; and determining the leading edge blanking time to be a second value if the feedback signal has a magnitude about a second voltage, wherein the first value is smaller than the second value, and the first voltage is greater than the second voltage.
U.S. 7,558,037 B1 to Gong et al. disclose circuit and method for providing over-current and overloading protection with a single additional pin. A converter controller circuit is provided that includes a voltage controlled oscillator and outputs upper and lower gating signals for driving the upper and lower driving transistors in a voltage converter, for example, in an inductor-inductor capacitor half-bridge circuit topology. A current sense input pin of the circuit receives a voltage corresponding to the current flowing in the half-bridge circuit. A feedback input pin has an external capacitor coupled to it and receives a voltage from an output voltage sensor at the output terminals. Over-current protection is provided by sensing the voltage at the current sense input pin with no external components needed. Overload protection is provided by utilizing the external feedback capacitor and the feedback input pin during overload conditions. Methods for providing over-current and overload protection are disclosed.
U.S. 2020/0195004 A1 to Xiong et al. disclose a current protection circuit for a high voltage system includes: a power supply module to supply power to a load through a high voltage bus and a low voltage bus; a detection module connected to the high voltage bus and used to detect a value of current flowing through the high voltage bus; a signal processing module electrically connected to the detection module and used to amplify the current flowing through the high voltage bus; and a control module electrically connected to the signal processing module, the power supply module, and the load, and used to disconnect the load from the power supply module or perform current limiting for the load when the value of the amplified current exceeds a preset threshold.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
December 18, 2025
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858