Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. This office action is responsive to communication(s) filed on 3/6/2026.
2. Claims 1-4 and 7-22 are presented for examination.
3. Applicant's arguments with respect to the newly added limitations have been considered but have not been found persuasive. Therefore, claims 9-15 that are still rejected for the same reason as set forth in the previous Office action that are provided below for your convenience including the rejections of newly added limitations.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 9-15 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Chu US Pub. No. 20020004875 (previous cited).
As per claims 9 and 14, Figs. 1-2 of Chu are directed to a method, comprising: receiving a structure comprising a first ferroelectric transistor (n transistor) over a substrate (abstract or par. 23) and a second ferroelectric transistor (p transistor) vertically above the first ferroelectric transistor (Fig. 2), wherein the structure further comprises a ferroelectric material (ferroelectric, Fig. 1 and 3) interfacing with an insulating layer (Figs. 1 and 3) of the substrate.; applying a write voltage (2V, par. 21) to a gate of the first ferroelectric transistor and a gate of the second ferroelectric transistor to set polarization states of the first ferroelectric transistor and the second ferroelectric transistor (par. 21); and after applying the write voltage (2V to -7V, par. 22), applying a zero voltage to the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor, such that one of the first and second ferroelectric transistors presents a high drain current level and another one of the first and second ferroelectric transistors presents a low drain current level, the low drain current level being less than the high drain current level (par. 19).
As per claims 10-12, Fig. 2 and the paragraphs 21-22 of Chu disclose during applying the zero voltage to the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor, applying a first input signal (Vds) and a second input signal (Vs) to a source region of the first ferroelectric transistor and a source region of the second ferroelectric transistor, respectively; and after applying the first input signal and the second input signal, reading an output signal from a terminal connecting with a drain region of the first ferroelectric transistor and a drain region of the second ferroelectric transistor (par. 21).
As per claim 13, the paragraph 21 of Chu discloses wherein during applying the write voltage, a source region of the first ferroelectric transistor and a source region of the second ferroelectric transistor are biased with zero voltage.
As per claim 15, Fig. 1a and 1B of Chu disclose the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor each comprises: an interfacial layer (a top surface of a channel); a ferroelectric layer (ferroelectric, Fig. 1a or 1b) over the interfacial layer; and a gate electrode layer (abstract) over the ferroelectric layer.
Allowable Subject matter
7. Claims 1-4, 7-8 and 16-22 are allowed.
8. The following is a statement of reasons for the indication of allowable subject matter: See the arguments in Applicant’s remark for these allowed claims.
Response to Arguments
9. Applicants’ arguments have been fully considered but they are not persuasive.
Applicant argues, “Chu is silent regarding "a structure comprising a first ferroelectric transistor over a substrate and a second ferroelectric transistor vertically above the first ferroelectric transistor.”
Examiner respectfully disagrees. Fig. 3 and a paragraph 23 of Chu disclose these limitations.
For the above reasons, it is believed that the rejections should be sustained. Feature of an invention not found in the claims can be given no patentable weight in distinguishing the claimed invention over the prior art.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
10. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827
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