Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on April 29, 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The Examiner thanks the Applicant for disclosing that a co-pending application (18/801,285) was rejected for double patenting over the present application.
Response to Arguments
Applicant’s arguments, see REMARKS, filed April 29, 2026, with respect to the rejection(s) of claims 1 – 3 and 5 – 20 under 35 U.S.C. 103 have been fully considered and are persuasive. The Examiner agrees the motivation relied upon in the previous rejection is not sufficient to render the amended claims obvious. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of new art found in further search of prior art prompted by the amendments.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 – 3 and 5 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Barrilado Gonzalez (US Patent Application Publication 2018/0121282) in view of Cassidy et al. (US Patent 10,831,595), hereinafter Cassidy.
Regarding claim 1, Barrilado Gonzalez teaches an apparatus, comprising:
execution circuitry of a first integrated circuit processing element (Paragraph 0042, the controller and ASIC are integrated circuits, and may be a single element) to execute a current set of registers of a register test operation (Paragraph 0040, CRC is generated for a current memory zone) to verify operation of the first integrated circuit processing element (Paragraph 0004, the process is for detecting errors), wherein the execution circuitry is to store results of the current set of registers in one or more first data registers (Paragraph 0048, the execution circuitry has write access to the registers being tested. The contents of registers are interpreted as being equivalent to their results); and
hash value calculation circuitry (Paragraph 0033, the CRC generator may be circuitry) of the first integrated processing element to store, responsive at least in part to execution of the current set of instructions (Paragraphs 0035 – 0038 and 0083, the registers that are checked are modified as part of the execution of the application), a hash value for the current set of instructions in a hash value register of the first integrated circuit processing element (Paragraphs 0080 and 0084, the CRC result is written to a result register) to preserve one or more error indications through to a conclusion of the register test operation (Paragraph 0062, CRC errors are held for the full CRC cycle; Paragraph 0008, CRC is cumulative, and the cumulative result is used to check for the error, i.e. the error indication is preserved through to a conclusion of the full CRC cycle), wherein the hash value for the current set of registers is based at least in part on one or more data elements obtained from one or more specified data registers, including at least the one or more first data registers (Paragraph 0004, the values from the set of registers are used to compute the CRC result), and further based at least in part on a previously-stored hash value, obtained from the hash value register and fed back to the hash value calculation circuitry (Paragraph 0094, the CRC result stored in the seed/result register may be fed back as the seed for the next CRC calculation), for a previous set of registers of the register test operation (Paragraphs 0008 and 0016, a previous CRC result may be used as a seed for a subsequent calculation), such that the one or more error indications are preserved notwithstanding execution of the one or more of the current set of instructions that clear or overwrite at least one of the one or more specified data structures (Paragraph 0008, CRC is cumulative, and the cumulative result is used to check for the error, i.e. the error indication is preserved through to a conclusion of the full set of instructions, even if the register state changes).
Barrilado Gonzalez does not teach that the operation is an instruction test operation, and is instead a register test operation.
Cassidy teaches:
hash value calculation circuitry of a first integrate circuit processing element to store (Column 6 line 15 – 29, hardware circuitry that determines a runtime check sequence; Column 6 lines 63 – 67 disclose that the runtime check sequence may include the result of a CRC or cryptographic hash) responsive at least in part to execution of a current set of instructions of an instruction sequence test operation (Summary, runtime check sequence is determined during the execution of a deterministic program, the deterministic program being the instruction sequence), a hash value for the current set of instructions in a hash value register of the first integrated circuit processing element to preserve one or more error indications through to a conclusion of the instruction sequence test operation, such that one or more error indications are preserved notwithstanding execution of one or more of the current set of instructions that clear or overwrite the at least one of one or more specified data registers (Column 7 lines 2 – 7, the runtime check sequence may be stored in a hardware register. Note in Fig. 3 that the runtime check sequence is checked and errors identified after the execution of the deterministic program, meaning the error indications are preserved).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the application of Barrilado Gonzalez could be an instruction sequence test as taught by Cassidy. They would be motivated to do so because using a known test sequence advantageously allows for the hash value computation to robustly verify the data plane of the processor (Cassidy Column 10 lines 5 – 12). A fixed test sequence would furthermore be able to be designed to maximize test coverage. There is a reasonable expectation for success of such a combination. Cassidy teaches that one method of checking an instruction sequence test is by obtaining values produced by the processor as it performs the instruction sequence test (Cassidy Column 6 lines 30 – 55), and then further applying a hash value calculation to those values (Cassidy Column 6 lines 56 – 67). This is similar to Barrilado Gonzalez’s method of checking register state during execution of an application (Barrilado Gonzales paragraphs 0035 – 0038). Both Cassidy and Barrilado Gonzalez check the values produced by a processor to determine whether the processor is operating correctly. One of ordinary skill in the art would be able to recognize the benefit of using a test program such as Cassidy’s, designed to validate the performance of a processor, especially in the context of safety-critical (Barrilado Gonzalez paragraph 0003) systems such as Barrilado Gonzalez.
Regarding claim 2, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, wherein the current set of instructions comprises one or more instructions and wherein the previous set of instructions comprises one or more instructions to immediately precede the current set of instructions (Cassidy column 5 lines 20 – 40, the test sequence may be a set of instructions or output of instructions; Cassidy Fig. 5 shows the instructions in the instruction memory, which can clearly be separated into sequential sets).
Regarding claim 3, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, wherein the current set of instructions comprises a single instruction and wherein the previous set of instructions comprises a single instruction to immediately precede the current set of instructions (Cassidy Fig. 5, each individual instruction under test could be considered a current set of instructions, and most instructions are immediately preceded by another instruction).
Regarding claim 5, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, wherein the hash value for the current set of instructions comprises a cyclic redundancy check value for the current set of instructions, and wherein the hash value for the previous set of instructions comprises a cyclic redundancy check value for the previous set of instructions (Barrilado Gonzalez paragraph 0004).
Regarding claim 6, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 5, wherein the hash value calculation circuitry comprises circuitry to store the cyclic redundancy check value for the current set of instructions in the hash value register of the first integrated circuit processing element (Barrilado Gonzalez paragraph 0080, the CRC result is written to a result register), wherein the cyclic redundancy check value for the current set of instructions is based at least in part on the one or more data elements obtained from the one or more specified data registers, including at least the one or more first data registers (Barrilado Gonzalez paragraphs 0004 and 0033) and further based at least in part on the cyclic redundancy check value for the previous set of instructions (Barrilado Gonzalez paragraphs 0008 and 0016).
Regarding claim 7, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, further comprising selection circuitry to indicate to the hash value calculation circuitry the one or more specified data registers (Barrilado Gonzalez paragraph 0061, a multiplexer is used to select which register set is accessed by the CRC generator).
Regarding claim 8, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 7, wherein the selection circuitry comprises a selection register to store one or more data elements indicative of the one or more specified data registers (Barrilado Gonzalez paragraph 0061, the selection register 230).
Regarding claim 9, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, further comprising a control circuit of the first integrated circuit processing element to enable, halt, and/or pause storage of hash values by the hash value calculation circuitry to the hash value register (Barrilado Gonzalez paragraph 0049, the controller 190) responsive at least in part to a first specified value written to a control register (Barrilado Gonzalez paragraph 0049, the trigger register 172 controlling when calculation starts, and start and end address registers 166 and 168 controlling when calculation halts/pauses. The busy/done register 176 is also a control register.).
Regarding claim 10, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 9, wherein the control circuit is to reset the hash value register (Barrilado Gonzalez Fig. 8, the seed/result registers may be cleared by a microcontroller unit in response to a match 530 or completion of error handling procedure 532) responsive at least in part to a second specified value written to the control register (Barrilado Gonzalez Fig. 8, the match 530 and error handling 532 are at least in part responsive to the disabling of the auto trigger 526).
Regarding claim 11, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, further comprising:
a selection register to store one or more data elements indicative of the one or more specified data registers (Barrilado Gonzalez paragraph 0061, the selection register 230);
a control register to store one or more data elements to indicate to a control circuit of the first integrated circuit processing element to enable, halt, reset and/or pause storage of hash values to the hash value register (Barrilado Gonzalez paragraph 0049, the trigger register 172 controlling when calculation starts, and start and end address registers 166 and 168 controlling when calculation halts/pauses. The busy/done register 176 is also a control register.);
wherein the selection register, the control register, and/or the hash value register are accessible via execution of one or more instructions (Barrilado Gonzalez paragraph 0019).
Regarding claim 12, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, wherein the hash value calculation circuitry is implemented within a first processor core of the first integrated circuit processing element (Barrilado Gonzalez paragraph 0042, the controller (including the calculation circuitry) and the ASIC (the circuit running the application under test), may be implemented in a single integrated circuit, or as separate dies in a multi-chip module).
Regarding claim 13, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, wherein the one or more data elements obtained from the one or more specified data registers comprise the previously-stored hash value (Barrilado Gonzalez paragraphs 0008 and 0016, a previous result may be used as a seed for a subsequent calculation; Barrilado Gonzalez paragraph 0109, the seed/result register may also be written to registers 354c/d, which, as shown in Paragraph 0105, are among the specified data registers).
Regarding claim 14, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, further comprising circuitry of the first integrated circuit processing element to, responsive to a storage of the hash value for the current set of instructions to the hash value register, write the hash value for the current set of instructions from the hash value register to at least one of the one or more specified data registers (Barrilado Gonzalez paragraph 0109, the result may be stored in seed/result registers 364c/d, and then stored back in seed/result registers 354c/d) for use in a subsequent set of instructions to be executed by the execution circuitry as part of the instruction sequence test operation (Barrilado Gonzalez paragraph 0112, the result of the DCR calculation may be stored in the MCU memory or ASIC seed/result register for use in a future calculation).
Claim 16 recites similar language to claim 1, and is similarly rejected as being unpatentable over Barrilado Gonzalez in view of Cassidy.
Regarding claim 17, Barrilado Gonzalez in view of Cassidy teaches the method of claim 16, further comprising:
writing one or more data elements indicative of the one or more specified data registers in a selection register (Barrilado Gonzalez paragraph 0061, the selection register 230);
writing one or more data elements to a control register to indicate a control circuit of the first processor core to enable, halt, reset, and/or pause storage of hash values to the hash value register (Barrilado Gonzalez paragraph 0049, the trigger register 172 controlling when calculation starts, and start and end address registers 166 and 168 controlling when calculation halts/pauses. The busy/done register 176 is also a control register);
writing the hash value for the current set of instructions to a memory (Barrilado Gonzalez paragraphs 0093/0094, the seed/result registers; Alternatively, Barrilado Gonzalez paragraph 0112, the MCU may save the value in its internal memory) in accordance with one or more additional instructions decoded by an instruction decode unit (Barrilado Gonzalez paragraph 0019, instructions executed by a processing unit);
wherein the selection register, the control register, and/or the hash value register are accessible via execution of one or more instructions (Barrilado Gonzalez paragraph 0019).
Claim 18 recites similar language to claim 14, and is similarly rejected.
Claim 19 recites similar language to claim 15, and is similarly rejected.
Regarding claim 20, Barrilado Gonzalez in view of Cassidy teaches a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus (Barrilado Gonzalez paragraph 0019, Cassidy columns 11 and 12).
Claim 20 otherwise recites similar language to claim 1, and is similarly rejected.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Barrilado Gonzalez in view of Cassidy as applied to claim 1 above, and further in view of the well-known operations for a processor.
Regarding claim 15, Barrilado Gonzalez in view of Cassidy teaches the apparatus of claim 1, further comprising circuitry of the first integrated circuit processing element to, responsive to a storage of the hash value for the current set of instructions to the hash value register, write the hash value for the current set of instructions from the hash value register to the at least one of the one or more specified data registers (Barrilado Gonzalez paragraph 0109, the result may be stored in seed/result registers 364c/d, and then stored back in seed/result registers 354c/d).
Barrilado Gonzalez in view of Cassidy does not explicitly teach that execution of the current set of instructions is to have cleared at least one of the one or more specified data registers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the instructions executed by Barrilado Gonzalez in view of Cassidy as applied to claim 1 would include clearing a register. The examiner takes official notice that clearing a register is a commonly known operation in a computer system. Cassidy teaches that the instructions include operands and opcodes in Fig. 4. One of ordinary skill in the art would recognize that one of these operand – opcode combinations could result in clearing a register.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN PAI SONG HUANG whose telephone number is (571)272-0510. The examiner can normally be reached Monday - Friday 11:30 AM - 8:30 PM.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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