DETAILED ACTION
This office action is in response to communication filed on 02/06/2026. Claims 1, 9 and 17 have been amended. Claims 1 – 20 are pending on this application.
Response to Arguments
2. Applicant’s arguments, with respect to amended claims 1, 9 and 17 “sequences, wherein each path generates its processed sequences using samples from a single respective ADC” have been considered but are moot because a new ground of rejection (Lewis et al. Pub. No. 2014/0152477) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-6, 9-14 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lewis et al. Pub. No. 2014/0152477.
Regarding claim 1. Fig. 2B of Lewis discloses a system (210) for correcting distortion (paragraph 0020) in an analog input signal (input 207), the system comprising: a plurality of analog-to-digital converters (ADC 201-1….ADC 201-n) configured for receiving the analog input signal (207) having the distortion (paragraph 0020), each of the analog-to-digital converters (each of ADC 201-1….ADC 201-n) configured for generating an N- bit digital signal (N bit output from each ADC 201-1….ADC 201-n), each of the plurality of ADCs (each of ADC 201-1….ADC 201-n) configured for generating a sequence of samples (sequence samples output from each digital process path); and a digital processing circuit (204-1…204-n and 205-1…205-n) configured for receiving each of the N-bit digital signals (N-bit from each ADC 201-1….ADC 201-n), the digital processing circuit (204-1…204-n and 205-1…205-n) including: a plurality of parallel processing paths (parallel paths of 204-1…204-n and 205-1…205-n), each path (each path of 204-1…204-n and 205-1…205-n) corresponding to one of the ADCs (one of ADC 201-1….ADC 201-n) and configured to process the sequence of samples (sequence samples output from each digital process path) to generate processed sequences (output sequences of 205-1…205-n), wherein each path (each path of sequence samples output from each digital process path); generates its processed sequences (output sequences of 205-1…205-n) using samples from a single respective ADC (each of ADC 201-1); and a plurality of memories (241-1…241-n and 251-1…251-n), each memory (each of 204-1…204-n. 251-1…251-n) associated with one of the parallel processing paths (parallel paths of 204-1…204-n and 205-1…205-n) and configured for storing distortion correction term (Gain and Offset correction 204-1…204-n. 251-1…251-n),wherein the digital processing circuit (204-1…204-n and 205-1…205-n) is configured for: applying the distortion correction terms (Gain correction and Offset correction) from the memories (241-1…241-n and 251-1…251-n) to the processed sequences (output sequences of 205-1…205-n); and generating a correction 0-bit digital signal (Correction digital signal from 205-1…2005-n) ,wherein a first subset (241-1…241-n) ) of the memories (241-1…241-n and 251-1…251-n) is configured for storing a first distortion correction term (Gain Offset correction) for correcting a first type of error (Gain error) , and wherein a second subset (251-1…251-n) of the memories (241-1…241-n and 251-1…251-n) is configured for storing a second distortion correction term (Offset correction) different than the first distortion correction term (Gain correction) for correcting a second type of error (Offset error).
Regarding claim 2. The system of claim 1, Fig. 2B further discloses wherein the first type of error (Gain error) is common to all of the plurality of ADCs (ADC 201-1…. ADC 201-n).
Regarding claim 3. The system of claim 1, Fig. 2B further discloses wherein the plurality of ADCs included an interleave ADC (paragraph 0007) having a first sub-ADC (ADC 201-1) and a second sub-ADC (ADC 201-n).
Regarding claim 4. The system of claim 3, Fig. 2B further discloses wherein the first distortion correction term (Gain) corrects a nonlinearity (step 126 in Fig. 1B discloses non-linearity) and the second distortion correction term (Offset Correction) corrects the nonlinearity (step 126) plus an error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-n).
Regarding claim 5. (Original) The system of claim 4, Fig. 2B further discloses wherein the error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-1) is an interleaving mismatch error (paragraph 0021).
Regarding claim 6. The system of claim 1, Fig. 2B further discloses wherein the plurality of ADCs comprises at least two ADCs (ADC 201-1…. ADC 201-n).
Regarding claim 9. Fig. 2B of Lewis discloses a method for correcting distortion (paragraph –0020) in an analog input signal (Input 207) , the method comprising: storing (Memories 241-1…241-n and 251--1…251-n), in a subset of memories (subset of 241-1…241-n), first distortion correction terms (Gain Correction of 204-1…204) for correcting a first type of error (Gain error); storing, in a second subset of the memories (sublet Memory 251--1…251), a second distortion correction term (Offset correction of 205-1…205-n) different than the first distortion correction term (Gain Correction of 204-1…204) for correcting a second type of error (error of offset); receiving, using a plurality of analog-to-digital converters (ADC 201-1….ADC 201-n), the analog input signal (207) having the distortion (distortion (paragraph –0020); generating, via each of the plurality of ADCs (ADC 201-1….ADC 201-n), an N-bit digital signal (bits output of each ADC 201-1….ADC 201-n) from a sequence of samples (sequence samples output from each digital process path); processing, via a plurality of parallel processing paths (parallel paths of each 204-1…204-n and 205-1…205-n), the sequence of samples (sequence samples output from each digital process path) to generate processed sequences (output sequences of 205-1…205-n), wherein each path (each path of sequence samples output from each digital process path) corresponds to one of the ADCs (one of ADC 201-1….ADC 201-n), wherein each path generates (each path of sequence samples output from each digital process path) its processed sequences (output sequences of 205-1…205-n) using samples from a single respective ADC (single ADC 201-1….ADC 201-n); applying the first correction distortion correction term (Gain Correction) and the second distortion correction term (offset correction) to the processed sequences (output sequences of 205-1…205-n); and generating a correction O-bit digital signal (Correction digital signal from 205-1…2005-n).
Regarding claim 10. The method of claim 9, Fig. 2B further discloses wherein the first type of error (Gain error) is common to all of the plurality of ADCs (ADC 201-1…. ADC 201-n).
Regarding claim11. The method of claim 9, Fig. 2B further discloses wherein receiving, using the plurality of analog-to-digital converters (ADC 201-1…. ADC 201-n), the analog input signal (207) having the distortion (paragraph 0020) includes: receiving, using an interleave ADC (paragraph 0007) having a first sub-ADC (ADC 201-1) and a second sub-ADC (ADC 201-n).
Regarding claim 12. The method of claim 11, Fig. 2B further discloses wherein the first distortion correction term (Gain) corrects a nonlinearity (step 126 in Fig. 1B) and the second distortion correction term (Offset Correction) corrects the nonlinearity (step 126) plus an error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-n).
Regarding claim 13. The method of claim 12, Fig. 2B further discloses wherein the error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-1) is an interleaving mismatch error (paragraph 0021).
Regarding claim 14. The method of claim 9, Fig. 2B further discloses wherein receiving, using the plurality of analog-to-digital converters (ADC 201-1…. ADC 201-n), the analog input signal (207) having the distortion (paragraph 0020) includes: receiving, using at least two ADCs (ADC 201-1…. ADC 201-n), the analog input signal (207) having the distortion (paragraph 0020).
Regarding claim 17. Fig. 2B of Lewis discloses a system (210) for correcting distortion (paragraph 0020) in an analog input signal (207), the system (210) comprising: an interleaved ADC (paragraph 0007) having a first sub-ADC and a second sub-ADC (ADC 201-1…. ADC 201-n) and configured for receiving the analog input signal (207) having the distortion (paragraph 0020), each of the first sub-ADC (ADC 201-) and the second sub-ADC (ADC 201-n) configured for generating an N-bit digital signal (bits from each ADC 201-1…. ADC 201-n) from a sequence of samples (sequence samples output from each digital process path); and a digital processing circuit (circuit 204-1…204-n and 205-1…205-n) configured for receiving each of the N-bit digital signals (bits output of ADC 201-1…. ADC 201-n), the digital processing circuit (204-1…204-n and 205-1…205-n) including: a plurality of parallel processing paths (parallel processing path of 204-1…204-n and 205-1…205-n), each path corresponding to one (each digital path of 204-1…204-n and 205-1…205-n) of the ADCs (ADC 201-1…. ADC 201-n) and configured to process the sequence of samples (sequence samples of each ADC 201-1…. ADC 201-n) to generate processed sequences (output sequences of 205-1…205-n), wherein each path (each path 204-1…204-n and 205-1…205-n) of generates its processed sequences (output of 205-1…205-n) using samples from a single respective ADC (samples of each respective ADC 201-1…. ADC 201-n) and a plurality of memories (241-1…241-n and 251--1…251-n), each memory (each of memories 241-1…241-n and 251--1…251-n) of associated with one of the parallel processing paths (parallel processing path of 204-1…204-n and 205-1…205-n) and configured for storing distortion correction terms (gain and offset correction), wherein the digital processing circuit (circuit 204-1…204-n and 205-1…205-n) is configured for: applying the correction distortion correction terms (gain adjustment) from the memories (241-1…241-n and 205-1…205-n) to the processed sequences (processed sequence of 204-1…204-n and 205-1…205-n) ; and generating a correction O-bit digital signal (Gain and offset correction of digital signal of each digital path of 204-1…204-n and 205-1…205-n), wherein a first subset of the memories (241-1…241-n) is configured for storing a first distortion correction term (Gain correction) for correcting a first type of error (gain error) , and wherein a second subset of the memories (251--1…251-n) is configured for storing a second distortion correction term (Offset Correction) different than the first distortion correction term (gain correction) for correcting a second type of error (offset error).
Regarding claim 18. The system of claim 17, Fig. 2B further discloses wherein the first distortion correction term (Gain) corrects a nonlinearity (step 126 in Fig. 1B discloses non-linearity) and the second distortion correction term (Offset Correction) corrects the nonlinearity (step 126) plus an error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-n).
Regarding claim 19. The system of claim 18, Fig. 2B further discloses wherein the error (paragraph 0031 discloses phase error) of the second sub-ADC (ADC 201-n) relative to the first sub-ADC (ADC 201-1) is an interleaving mismatch error (paragraph 21 discloses interleaved of ADC with mismatch error).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 7, 8, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lewis et al. applied to claims 1, 9 and 17 above, in further view of Lok et al. U.S. patent No. 10,483,995.
Regarding claims 7, 15, and 20. Lewis et al. applied to claims 1, 9 and 17 above, do not disclose wherein each memory includes a plurality of memory addresses, wherein at least some of the plurality of memory addresses are configured to store a concatenation of two or more distortion correction terms.
Fig. 6 of Lok et al. discloses a system for correcting distortion (110) for analog-to digital converter (ADC) comprising: a memory 114 includes a plurality of memory addresses (D7, D6) are configured to store a concatenation of two or more distortion correction terms (-.26, +12).
Lewis et al. and Lok et al. are common subject matter of non-linear correction of digital signal for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Lok et al. into Lewis et al. for the purpose of locate the corresponding correction value in the memory for digital signal as suggested by Fig. 6 of Lok et al.
7. Regarding claims 8 and 16. Lewis et al. and Lok et al. applied to claims 7 and 15 above, Fig. 2B Lewis et al. further discloses wherein the two or more distortion correction terms are time delayed (paragraph 0026 discloses “the N ADCs within a time-interleaving ADCs experience different delays).
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
04/01/2016
/LINH V NGUYEN/Primary Examiner, Art Unit 2845