Prosecution Insights
Last updated: April 19, 2026
Application No. 18/736,601

MEMORY SYSTEM, INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND METHOD OF RELOCATING DATA

Final Rejection §103
Filed
Jun 07, 2024
Examiner
JUNG, ANDREW J
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Kioxia Corporation
OA Round
2 (Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
3y 1m
To Grant
95%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allow Rate
80 granted / 139 resolved
+2.6% vs TC avg
Strong +37% interview lift
Without
With
+37.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
9 currently pending
Career history
148
Total Applications
across all art units

Statute-Specific Performance

§101
6.2%
-33.8% vs TC avg
§103
53.4%
+13.4% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 139 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to amendment filed on August 18, 2025. Claims 1, 8, and 16 have been amended. No new claims have been added. The objections and rejections from the prior correspondence that are not restated herein are withdrawn. Response to Arguments Applicant's arguments filed on August 18, 2025 have been fully considered but are moot because the arguments allege that only the newly added limitations are not taught by the prior art of record. It should be noted that a new prior art reference to JUNG teaches the newly added limitations as shown in the rejections below. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C.119 (a)-(d). The certified copy has been filed in parent Application No. JP2023-095506, filed on June 9, 2023. Claim Objections Claim 8 is objected to because of the following informalities: the limitation "the first information being managed in the in the circuitry" contains a typo. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-12, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA (Pub No.: US 20180107593 A1), hereafter OGAWA, in view of JUNG (Pub. No.: US 20240402945 A1), hereafter JUNG. Regarding claim 1, OGAWA teaches: A memory system comprising: a non-volatile memory; and a controller that is communicatively coupled with a host, and configured to control the non-volatile memory (see OGAWA Fig. 2, where [0084] teaches storage medium 240 is an SSD using a NAND flash; Fig. 23 and [0229-0230] teach storage controller 2320 is connected as an independent apparatus via a network or 2343 is mounted on storage medium 2340), […] first information about mapping of data of a file to a logical address space of the memory system (OGAWA [0057] teaches the storage control apparatus 100 includes a determiner 101 and a data rearrangement unit 102. The determiner 101 determines whether data corresponding to a logical address area in a logical address space used by the host computer to access a storage medium 110 can be estimated to be fragmented and stored in a plurality of physical address areas in a physical address space used in the storage medium 110. The data rearrangement unit 102 reads data by designating a logical address area corresponding to data 111 for which it has been determined that the data 111 can be estimated to be fragmented and stored in the physical address space, and instructs the storage medium 110 to write the data in the logical address area while controlling or restricting other write operations so that the data is written in continuous physical address areas 112 in the storage medium), and relocate, in a physical address space of the non-volatile memory, the data of the file that is fragmented in the physical address space so that the data of the file is continuous in the physical address space based on the received first information (OGAWA [0059] teaches the storage controller estimates the fragmentation state of memory areas in a physical address space in a storage medium based on history information of access (read and write) to the storage medium by the OS (Operating System) of the host computer or an application program, and if the fragmentation state exceeds a predetermined state, defragmentation is implemented by collectively rearranging the areas in the fragmentation state; see also [0074] and claim 4), and also on second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space is recorded (OGAWA [0077] teaches for each set of continuous areas in the SSD, the defragmentation control function continuously re-stores, in the SSD, data in an area when fragmentation progresses by a predetermined amount or more with reference to the information recorded by the fragmentation state management function. In the re-storage processing, each data in the area is read, and all the data in the area are written with respect to the file or the LBAs in which the data are originally stored while controlling or restricting other write operations. The re-stored data are rearranged in the same block on the NAND flash and continuously stored, thereby implementing defragmentation). OGAWA does not appear to explicitly teach wherein the controller is further configured to receive, from the host, first information […], the first information being managed in the host. However, JUNG teaches wherein the controller is further configured to receive, from the host, first information about mapping of data of a file to a logical address space of the memory system, the first information being managed in the host (JUNG [0062] & [0088] teach the host may include the start address (Start LBA) and end address (End LBA) of a first file fragment Frag1 among the N file fragments in fields 40 to 47, and may include a start address (Start LBA) and an end address (End LBA) of a N-th file fragment FragN among the N file fragments, where [0159] & Fig. 18 teach flash conversion layer (FTL) 2214 may perform various functions such as address mapping, wear-leveling, and garbage collection, where the address mapping operation is an operation of changing a logical address received from the host into a physical address used to actually store data in the non-volatile memory 2220). Accordingly, it would have been obvious to a person having ordinary skill in the art at the time of the effective filing of the invention, having the teachings of OGAWA and JUNG before them, to modify OGAWA’s system performing defragmentation as taught by JUNG. Using the known technique of including the addressing information of file fragments in the host to provide the predictable result of performing defragmentation with the host including addressing information in OGAWA would have been obvious to a person having ordinary skill in the art, since a person having ordinary skill in the art would recognize that OGAWA was ready for improvement to incorporate the host including the addressing information of file fragments as taught by JUNG. Regarding claim 8, OGAWA teaches: An information processing system, comprising: circuitry configured to update data of a file stored in a non-volatile memory of a memory system (see OGAWA Fig. 2, [0084], [0057], Fig. 23, and [0229-0230] as taught above in reference to claim 1), query the memory system about a number of fragments of the data of the file in a physical address space of the non-volatile memory after the data of the file is updated; and when the number of fragments obtained from the memory system exceeds a threshold, provide, to the memory system, first information about mapping of the data of the file to a logical address space of the memory system (OGAWA [0059] teaches the storage controller estimates the fragmentation state of memory areas in a physical address space in a storage medium based on history information of access (read and write) to the storage medium by the OS of the host computer or an application program. If the fragmentation state exceeds a predetermined state, defragmentation is implemented by collectively rearranging the areas in the fragmentation state); and instruct the memory system to relocate, in the physical address space, the data of the file that is fragmented in the physical address space so that the data of the file is continuous in the physical address space (OGAWA [0057] teaches the data rearrangement unit 102 reads data by designating a logical address area corresponding to data 111 for which it has been determined that the data 111 can be estimated to be fragmented and stored in the physical address space, and instructs the storage medium 110 to write the data in the logical address area while controlling or restricting other write operations so that the data is written in continuous physical address areas 112 in the storage medium). OGAWA does not appear to explicitly teach the first information being managed in the in the circuitry. However, JUNG teaches the limitation (JUNG [0062] & [0088] teach the host may include the start address (Start LBA) and end address (End LBA) of a first file fragment Frag1 among the N file fragments in fields 40 to 47, and may include a start address (Start LBA) and an end address (End LBA) of a N-th file fragment FragN among the N file fragments, where [0159] & Fig. 18 teach flash conversion layer (FTL) 2214 may perform various functions such as address mapping, wear-leveling, and garbage collection, where the address mapping operation is an operation of changing a logical address received from the host into a physical address used to actually store data in the non-volatile memory 2220). Accordingly, it would have been obvious to a person having ordinary skill in the art at the time of the effective filing of the invention, having the teachings of OGAWA and JUNG before them, to modify OGAWA’s system performing defragmentation as taught by JUNG. Using the known technique of including the addressing information of file fragments in the host to provide the predictable result of performing defragmentation with the host including addressing information in OGAWA would have been obvious to a person having ordinary skill in the art, since a person having ordinary skill in the art would recognize that OGAWA was ready for improvement to incorporate the host including the addressing information of file fragments as taught by JUNG. Regarding claim 16, the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. Regarding claim 2, OGAWA in view of JUNG teaches the elements of claim 1 as outlined above. OGAWA also teaches: wherein the controller is further configured to relocate the fragmented data during an idle period during which data is not read from the non-volatile memory in accordance with a read command from the host or data is not written to the non-volatile memory in accordance with a write command from the host (OGAWA [0077] teaches the defragmentation control function continuously re-stores, in the SSD, data in an area when fragmentation progresses by a predetermined amount or more with reference to the information recorded by the fragmentation state management function. In the re-storage processing, each data in the area is read, and all the data in the area are written with respect to the file or the LBAs in which the data are originally stored while controlling or restricting other write operations. The re-stored data are rearranged in the same block on the NAND flash and continuously stored, thereby implementing defragmentation; see also [0057]). Regarding claim 3, OGAWA in view of JUNG teaches the elements of claim 1 as outlined above. OGAWA also teaches: wherein the controller is further configured to: communicate with the host according to a protocol that conforms to a specific standard (OGAWA [0064-0065] teach the host computer accessing the SSD, where an FTL in a controller performs access processing unique to the NAND flash); receive, from the host, the first information in accordance with a first command defined as an extended command by the specific standard (OGAWA [0088] teaches the access executor 301 receives an access request from the OS 211 or application 212 operating on host computer 210, and performs necessary access processing for the storage medium 240. The access executor 301 reads data from an area on the storage medium 240 that is instructed by the defragmentation controller 304, and performs re-storage processing). and detect a number of fragments of the data of the file in the physical address space based on the first information and the second information in accordance with the first command, and transmit to the host information of the number of fragments (see OGAWA Fig. 3 & 5, where [0019-0020] teach determining whether data is fragmented and stored in a plurality of physical address areas in a physical address space, and [0089] teaches determining the fragment count corresponding to the storage destination area, where [0100] teaches a fragmentation state threshold 543 is a threshold for determining execution of rearrangement for defragmentation based on the fragment count 422 of the fragmentation state management table 303 representing the fragmentation state. A defragmentation flag 544 is a flag that indicates execution of rearrangement for defragmentation and is set the fragment count 422 exceeds the fragmentation state threshold 543. Read information 545 is information read from the storage medium 240 based on a request from the OS 211 or application 212. Write information 546 is information written in the storage medium 240 based on a request from the OS 211 or application 212). Regarding claim 4, OGAWA in view of JUNG teaches the elements of claim 3 as outlined above. OGAWA also teaches: wherein the controller is further configured to relocate the fragmented data after receipt, from the host, of a second command that is different from the first command and defined as the extended command by the specific standard after transmission to the host of the information of the number of fragments (OGAWA [0072] teaches data storage in which write access operations are parallelly executed for each series of continuous areas such as a file is managed. Defragmentation is performed by re-storing all data in an area whose fragmentation count has increased to a predetermined number or more or in continuous areas in which a large amount of data is stored at the same time. The occurrence of fragmentation in each area on the LBA space and an area storing continuous data such as a file is estimated from the write data amount of the whole SSD between write requests for the same area and recorded; [0090-0091] teach the fragmentation state management table 303 records the result of estimating the fragmentation state on the NAND flash by the fragmentation state estimator 302, the total write amount of the storage medium 240 at the time of the last write request for each area, and information of the latest fragmentation occurrence frequency, where if the fragment count recorded in a corresponding entry in the fragmentation state management table 303 is equal to or larger than a predetermined value, the defragmentation controller 304 reads all data in the area for the access executor 301. Fig. 5 & [0033] teach the hardware arrangement of a host computer including a storage controller). Regarding claim 6, OGAWA in view of JUNG teaches the elements of claim 1 as outlined above. OGAWA also teaches: wherein the controller is further configured to relocate the fragmented data of the file in the physical address space so that the data of the file is continuous and accessible via a first word line (see OGAWA [0057] as taught above in reference to claim 1, where the storage medium is instructed to write the data so that the data is written in continuous physical address areas 112 in the storage medium, where [0101] teaches logical address/physical address conversion table 551 is a table used to convert the logical address 541 requested to be accessed from the OS 211 or application 212 into the physical address 542 used to access the storage medium 240). Regarding claim 7, OGAWA in view of JUNG teaches the elements of claim 6 as outlined above. OGAWA also teaches: wherein the controller is further configured to relocate other data of another file that is also fragmented in the physical address space so that the data of the another file is continuous and accessible via a second word line, the second word line being different than the first word line (see OGAWA Fig. 8B, where [0114-0115] teach if it is determined that new fragmentation occurs in the storage medium 240 by storing the write data, defragmentation is performed (performed as a loop, i.e. another file accessible via a second word line as taught above in OGAWA [0057] & [0101] in reference to claim 6)). Regarding claim 9, the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. Regarding claim 10, the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale. Regarding claim 11, the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale. Regarding claim 12, the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale. Regarding claim 14, the claim recites similar limitation as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale. Regarding claim 15, the claim recites similar limitation as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale. Regarding claim 17, the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale. Regarding claim 18, the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale. Regarding claim 19, the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale. Claims 5, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA in view of JUNG as applied to claims 1, 8, and 16 above, and further in view of KATO (Pub. No.: US 20230087470 A1), hereafter KATO. Regarding claim 5, OGAWA in view of JUNG teaches the elements of claim 1 as outlined above. OGAWA also teaches: wherein the non-volatile memory has a plurality of blocks, each of the plurality of blocks is an erasure unit of data (OGAWA [0064] teaches NAND flash having blocks that can be erased); and the controller is further configured to relocate the fragmented data by using garbage collection (OGAWA [0066] & [0069] teach performing GC (garbage collection) in the SSD for each block of the NAND flash to collect a memory area storing data that has become unnecessary due to update). OGAWA in view of JUNG does not appear to explicitly teach including a move of valid data from L blocks to K blocks, where L is a natural number of 2 or more, where K is a natural number of 1 or more and less than L, so as to generate free areas for (L - K) blocks. However, KATO teaches the limitation (KATO [0015] teaches a garbage collection process in which valid data of first blocks is moved (rewritten) to second blocks. The number of second blocks is fewer than the number of the first blocks, thus the garbage collection process generates one or more free (available) blocks by a consolidation of valid data into fewer total blocks; see also Fig. 4 & 6). Accordingly, it would have been obvious to a person having ordinary skill in the art at the time of the effective filing of the invention, having the teachings of OGAWA, JUNG, and KATO before them, to include KATO’s garbage collection consolidating cold data in OGAWA and JUNG’s system performing defragmentation. One would have been motivated to make such a combination in order to improve the efficiency of the garbage collection by consolidating cold data in fewer blocks as taught by KATO ([0005]). Regarding claim 13, the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale. Regarding claim 20, the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: KIM (Pub. No.: US 20240241835 A1) – “STORAGE DEVICE SUPPORTING MULTI-NAMESPACE AND METHOD OF OPERATING THE SAME” relates to defragmenting namespaces. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW J JUNG whose telephone number is 571-270-3779. The examiner can normally be reached on Monday through Friday from 9am to 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Wiley can be reached on 571-272-4150. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
Read full office action

Prosecution Timeline

Jun 07, 2024
Application Filed
May 08, 2025
Non-Final Rejection — §103
Aug 18, 2025
Response Filed
Nov 04, 2025
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
95%
With Interview (+37.3%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
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