DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication filed on 06/07/2024. Claims 1-16 are pending on this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wong U.S. patent No. 6,169,503 in view of Knierim U.S. patent No. 4,586,025.
Fig. 7A of Wong discloses an analog-to-digital converter system (Col. 3 lines 56-58) comprising: a sensing circuit (Sense Amplifier 744) coupled to a bit line of a memory array (bit line of memory 710); and encoder (730) to generate digital output (Dout).
Fig. 4 of Wong discloses Sensing circuit (420) generate thermometer code (T1…T7) from bit line sensing (RC1…RC7); and a thermometer-to-Binary Encoder (430).
Fig. 5A of Wong discloses of thermometer-to-binary encoder (530) comprising a latch and logic counter circuit (532).
Fig. 1 of Knierim discloses an analog-to- digital converter to convert analog input signal (Vi) to binary digital output (B1…B5) comprising sensing circuit (comparator 12) sensing the analog input (Vin) and generate thermometer code (T1…T16); latch logic circuits (18, 20, 22) to convert thermometer (T1…T16) to Binary coding (B1…B5).
Regarding claim 1. Fig. 4, Fig. 5A and Fig. 7A of Wong discloses an analog-to-digital conversion device (Col. 3 lines 49-51) , comprising: a sensing circuit (420) , coupled to a bit line of a memory array (bit lines of 710 in in Fig. 7B), and used to sense a current in the bit line (current of bit line RC1, RC2,… RC7) in to generate a bit-sequence (T1….T7) , the bit-sequence (T1…T7) has a form of a thermometer code (Col. 5 lines 25-35) to represent an analog value (analog value of bit line RC1, RC2, RC3); and a latch logic circuit (thermometer-to-binary encoder 430; see Fig. 5 of discloses thermometer-to-binary encoder comprising latch logic circuit 534), to form a page buffer (page buffer of T1…T7) of the memory array (710 in in Fig. 7A), and used to generate a bit-set ( bit set D0, D1, D3) according to the bit-sequence (T1…T7) , the bit-set (D0, D1, D3) has a form of a binary code (binary of D0, D1, D3) to represent a digital value (digital value of D0, D1, D3) ; wherein, the latch (thermometer-to-binary encoder 430; see Fig. 5 of discloses thermometer-to-binary encoder comprising latch logic circuit 534) perform a conversion process (thermometer-to-binary encoder 430) to convert the bit-sequence (T1…T7) into the bit-set (bit set D0, D1, D3), and the conversion process (thermometer-to-binary encoder 430) has a bit width (three bit width of D0, D1, D3).
However, Wong does not disclose the latch logic including a plurality of latches and a plurality of logic circuits; wherein the latches and the logic circuits perform a conversion process to convert the bit-sequence into the bit-set.
Fig. 1 of Knierim discloses an analog-to-digital conversion device (Col. 1 lines 18-19) comprising a latch logic (18, 20, 22) including a plurality of latches (latches 18; Col. 3 lines 42 discloses “latch pipelines 18 “) and a plurality of logic circuits (“AND” gates 20 and “OR” gates 22 logic circuits) to form a page buffer (page buffer for thermometer code T1…T16); wherein the latches (latches 18) and the logic circuits (“AND” gates 20 and “OR” gates 22 logic circuit) perform a conversion process (conversion of thermometer code T1…T16 to Binary code B1…B5) to convert a bit-sequence (thermometer sequence T1…T16) into binary bit-set ( B1…B5).
Wong and Knierim are common subject matter of Latch for thermometer to binary conversion; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Latch logic of Knierim into the latch logic of Wong for the purpose of providing a improved thermometer-to-binary encoder which minimizes the deviation of the magnitude of its binary code output from the ideal approximation magnitude resulting from an out-of-sequence error in its thermometer code input (Col. 2 lines 50-54 of Knierim).
Regarding claim 3. Wong and Knierim applied to claim 1 above, Fig. 4 of Knierim further discloses wherein the sensing circuit (420) comprising: a sensing amplifier (427, 42), having an input end input end of 744) coupled to the bit line (bit lines of 710), the input end has a first node (input node of 744), and the first node has a first node voltage (input node voltage of 744); wherein, the sensing circuit (744) generates the bit-sequence (bit sequence output of 744) according to the first node voltage (input voltage of 744) and a threshold voltage of the sensing amplifier (threshold voltage of 174; see threshold Vcc of 420 in Fig. 4 for sensing ).
Regarding claim 4. Wong and Knierim applied to claim 3 above, Fig. 1 of Knierim further discloses wherein one of the latches (first latch of 18) of the latch logic circuit (18) is coupled to an output end of the sensing amplifier ( (12) to receive the bit-sequence (bit sequences output of 12), and another one of the latches (another latch of 18) is coupled to a data input/output path (path of 20, 16) to transmit the bit-set (B1…B5).
Regarding claim 5. Wong and Knierim applied to claim 3 above, Fig. 4 of Wong further discloses wherein when the first node voltage (input voltage of 427 and 428) is greater than or less than the threshold voltage (Vcc), the bit-sequence (T1…T7) has a logic value “0” or a logic value “1” (high of T1…T7; see TABLE 1 on Col. 5 lines 25-35).
Regarding claim 6. Wong and Knierim applied to claim 3 above, Fig. 4 of Wong further discloses wherein the sensing circuit (420) generates the bit-sequence (T1…T7) according to a plurality of sensing time points (426) at which the first node voltage (node input voltage of 427 and 428) decreases to the threshold voltage (less than Vcc then PMOS 427 is on).
Regarding claim 7. Wong and Knierim applied to claim to claim 6 above, Fig. 4 of Wong further discloses wherein when the bit width (2 bits width D0, D1) of the conversion process (conversion process of 430) is equal to two D0 and D1 equals to 2 bis; TABLE 1 on Col. 5 lines 25-35; the sensing circuit (420) generates the bit-sequence (bit sequence of T1…T3) according to a first time point (time point of RC1), a second time point (time point of RC2) and a third time point (time point of RC3) of the sensing time points (sensing time points of RC1…RC3).
Regarding claim 9. Wong and Knierim applied to claim 6 above, Fig. 4 of Wong further discloses wherein when the bit width (three bits D0..D3) of the conversion process is greater than or equal to three (three bits D0..D3), the sensing circuit ( generates one bit of the bit-sequence (T1..T7) according to at least one fourth time point (7 time points of RC1…RC7) of the sensing time points (sensing time points of RC1…RC7).
Regarding claim 10. Wong and Knierim applied to claim 9 above, Fig. 5 of Wong further discloses, wherein the latch logic circuit (530) generates at least one bit of most significant bits (MSB) of the bit-set (most significant bit set of Dout) by a successive-approximation register (SAR) mechanism (Col. 1 lines 64-66) according to the at least one fourth time point (sensing time points of RC1…RC7).
5. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wong and Knierim applied to claim 1 above, in further view of Kumar et al. Pub. No. 2014/0232827.
Wong and Knierim applied to claim 1 above, Fig. 1 Knierim further disclose discloses wherein the latches (latches 18) and the logic circuits (“AND” gates 20 and “OR” gates 22 logic circuit) perform a conversion process (conversion of thermometer code T1…T16 to Binary code B1…B5); but does not disclose the latch logic circuit include an inverter and two NAND gates, and the inverter and the NAND gates execute a truth value conversion for the thermometer code and the binary code as claimed.
Fig. 4 and Fig. 5 of Kumar et al. discloses a thermometer to binary code (paragraph 0076) comprising the latch logic circuit (SR LATCH, NAND TAP1 and inverters TPA2…TAP7) include an inverter (inverters TAP 2…TAP 7) and two NAND gates (two NAND GATES of SR LATCH), and the inverter (inverters TAP 2…TAP 7) and the NAND gate (two NAND GATES of SR LATCH) execute a truth value conversion (true value logic of NAND gate and true value logic of inverter) for the thermometer code and the binary code (paragraph 0076).
Wong/Knierim and Kumar et al. are common subject matter of thermometer-to-binary conversion; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Latch logic of Kumar et al. into the latch logic of Wong/Knierim for the purpose of providing time-to-digital conversion with reduced power consumption (paragraph 0004 of Kumar et al.).
Allowable Subject Matter
6. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts considered individual or combination does/do not teach: wherein the latch logic circuit generates two bits of least significant bits (LSB) of the bit-set by a time-to-digital conversion (TDC) mechanism according to the first time point, the second time point and the third time point.
7. Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts considered individual or combination does/do not teach: at least one latch element, coupled to the sensing circuit, and used to set an initial charge amount of the first node.
8. Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts considered individual or combination does/do not teach: wherein the first node is coupled to a second node through a capacitor, the second node has a second node voltage, and the first node voltage and the second node voltage gradually decreases according to at least one step-voltage-difference.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
12/02/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845