DETAILED ACTION
Response to Arguments
Applicant’s arguments, see pages 1-3 of the remarks, filed on March 04, 2026, with respect to the rejection(s) of claim(s) 1, 9, and 10 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CN 1909408A and US 2016/0277177 A1.
Claim Objections
Claims 19 and 21 objected to because of the following informalities:
Claim 19, lines 4-5, “signal arrival detection” should be “signal arrival detection,”.
Claim 21 depends from claim 19, therefore it is also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 7, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 2006/0189288 A1), hereinafter “Jin” in view of O’SHEA et al. (US 2018/03 68082 A1), hereinafter “O’Shea” and FU et al. (CN 1909408A), hereinafter “Fu”.
Regarding claims 1 and 7, Jin discloses a method for operating a wireless communications device (abstract; pars. [0068]-[0069]: radio frequency mobile device), the method comprising: periodically enabling a radio frequency receiver circuit (abstract: wake-up periods and sleep periods; par. [0053]: receiver is “placed in a sleep mode (i.e., a low power mode such as being turned off)” and active when in a wake-up period: “wakes up to receive signals”; par. [0065]: after decoding signal during the wake-up period, processor can place the receiver in sleep mode by “turn[ing] off power to the receiver” and sets a timer for the next wake up time), the radio frequency receiver circuit being partitioned into a plurality of power domains (par. [0061]: LNA (low noise amplifier) stages of the receiver permit selective amplification depending on power of the received signal; stages are separately active or bypassed according to the gain level required depending on the received signal power); and controlling power consumption of the radio frequency receiver circuit by selectively disabling at least one of the plurality of power domains during an on-time of the radio frequency receiver circuit (par. [0069]: gain controller adjusts gain of receive signal during wake time; par. [0061] adjusting gain levels by bypassing LNA stages, including optionally bypassing all stages, the power consumption being controlled based on signal arrival detection and an average received signal power (par. [0061]-[0062]: received mean power of signal is used to determine signal strength (“weak” or “strong”) by comparison with thresholds R1, F1, R2 & F2 shown in Fig. 8A; gain states are determined accordingly for each stage of the LNA, with selective bypassing of LNA stages to adjust amplification of the signal; par. [0051]: gain control is responsive to the signal level; monitoring the signal level and determining average power necessarily includes detecting the signal that arrives at the receiver; see also RSSI (received signal strength indicator) from par. [0056]). Selectively controlling the gain at each LNA (low noise amplifier) stage as described in Jin necessarily controls power consumption of the receiver circuit because the required power depends on the amplification level or bypassing of each stage.
However, Jin is silent to power consumption being controlled by selectively setting the gain or bypassing LNA stages.
In the same field of wireless communications, O’Shea teaches in at least paragraphs [0086] and [0087] that adjusting gain of a bank of LNAs of a receiver circuit to selectively bypass or attenuate is specifically for power saving.
Jin also fails to show or teach that wherein the plurality of power domains includes a local oscillator power domain, a radio frequency front-end circuit power domain, and an automatic gain control and a demodulator power domain (and a frame controller power domain recited in claim 7).
Fu illustrates a device in FIG. 2 comprising: a wireless receiver; an analogue front end AFE; a voltage-controlled oscillator VCO; a phase-locked loop PLL; a logic FPGA; a digital signal processor DSP; a wireless modem; a monitor interface; and a radio frequency switch controlling signal interface, wherein the wireless receiver is used for receiving a radio frequency coupling to a TD-SCDMA radio frequency signal, and demodulating to obtain 1.6 MHz of an analog baseband signal into AI and AQ of I, Q two-path to the AFE.
Fu further teaches that the DSP is configured to receive DSP controls to generate the radio frequency switch signal to control the power amplifier and low noise amplifier, generate an automatic frequency control signal to control the voltage-controlled oscillator VCO voltage controlled oscillator VCO for generating a clock signal, the clock signal is provided directly to the wireless receiver, receive the control command of the monitoring interface or the wireless modem, obtain the second conversion point, and search the FPGA after demodulating sent by downlink TD-SCDMA digital baseband signal and an oversampled.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement Jin’s wireless communication system to selectively modify the operation of a plurality LNAs of an LNA bank of a receiver circuit in order to implement a power saving mode by selectively bypassing LNAs as taught by O’Shea, thereby reducing the voltage swing at the LNA input to maximize protection of the LNA input, as taught by O’Shea in paragraph [0060], and taught by Fu that the specific power domains are standard components in RF receiver architecture controlled by a processor circuit, like the low-noise amplifier (LNA) and bandpass filters that operate at the antenna input, often requiring separate power control to manage noise figure, a local oscillator (LO) produces a strong oscillation signal, which often requires a separate, stable, and well-isolated power domain to prevent its strong signal from interfering with the weak incoming RF signal (crosstalk), and an automatic gain control (AGC) AGC regulates the gain of the amplifier chain based on signal strength, and along with the demodulator, it handles the processed intermediate frequency (IF) or baseband signa in order to utilize a plurality of distinct power domains to manage power efficiency, noise, and isolation.
Regarding the apparatus claims 9 and 16, similar to the method claims 1 and 7, the claim features recited in claims 9 and 16 are similar to the claim features of claims 1 and 7 for the similar reasons described in claims 1 and 7 above.
Regarding the dependent claims 2-6, 8, 10-16, 17, and 18, the examiner takes Official Notice to reject the claims that they are not new and well-known in the art for the following reasons:
Regarding claims 2 and 11, each claim recites a fundamental, textbook concept in digital signal processing (DSP) and wireless communications. For example, the estimated instantaneous power of a signal is the square of its magnitude (e.g., in volts) over time, the moving average (often implemented via a sliding window) is universally used to smooth fluctuations, turning a highly variable instantaneous power reading into a rolling average power measurement, and comparing an averaged signal metric to a predetermined threshold is the core principle of Energy Detection (often associated with Constant False Alarm Rate, or CFAR, processing). It is commonly used for signal detection, spectrum sensing in cognitive radio, or determining if a signal is present above the noise floor.
Regarding claim 3, it is not new in the art that a receiver periodically wakes up into a low-power “packet receive state” to listen for a preamble. Once it detects the preamble, it specifically looks for the “synchronization word.” If the sync word is detected, the receiver stays awake to process the rest of the packet. If it is not detected, it immediately drops back into a deep sleep to save power. It is also known in the art by using a synchronization word to validate a packet and trigger further circuit activation is a foundational concept in digital communications. Prior art (such as standard RF transceiver datasheets from Texas Instruments, Silicon Labs, or Nordic Semiconductor dating back to the late 2000s and 2010s) frequently describes putting a receiver in a “sniff” or “preamble-detect” mode where power states are contingent on sync word detection.
Regarding claims 4 and 14, power domains (shutting off power to inactive circuit blocks) and “sleep” modes triggered by inactivity or timeouts are a well-established foundational concept in electrical engineering and computer architecture. The concept utilizes a standard timing mechanism (a detection window and timeout) to trigger an equally standard hardware state (disabling power domains). Combining these two known elements for power efficiency is often considered routine design optimization.
Regarding claims 5 and 13, the basic principle of turning off idle parts of an integrated circuit to save static leakage and dynamic power and turning them back on when needed is fundamental not new in the art, for example, protocols like Bluetooth, Zigbee, and Wi-Fi have long employed preamble detection to trigger full-chip wake-ups.
Regarding claims 6 and 15, as far back as the early 2000s, engineers realized that digital circuits like network routers or interface controllers draw substantial idle or “leakage” power when simply waiting for the next transmission. to prevent this, microcontrollers and systems were designed to automatically detect the “tail flit” (the end of a packet) and assert a sleep signal to cut power to the logic and memory arrays. This is now an automated part of modern chip manufacturing, where implementation tools parse text-based power design files (like Unified Power Format or UPF) to insert sleep transistors between the circuit and the power supply.
Regarding claim 8, correlator banks have been a fundamental signal processing technique used for decades to detect known sequences (like preambles or spreading codes). They operate by calculating a measure of similarity between an incoming signal and locally generated template signals. Applying mathematical transformations (e.g., Fourier transforms, wavelets) to a received symbol before correlating it with templates is a classic methodology for handling signal distortions, frequency offsets, and phase shifts. Using a peak output from a correlator bank to determine exactly when a signal arrives is standard operating procedure across multiple fields, most notably in GPS/GNSS receivers and spread-spectrum communications.
Regarding claim 10, the use of a correlator bank to detect signal arrival is the foundation of spread-spectrum communication (like CDMA or GPS) and many radar systems. Matching a received symbol against a set of expected template signals is the core mechanism of matched filters and rake receivers, which have been standard in telecommunications for decades. Comparing multiple transformed versions of a signal to find the highest correlation (to determine which symbol or bit was sent) is a textbook technique for demodulating digital signals.
Regarding claim 12, using a synchronization word (or preamble) to wake up or control power domains in a receiver is a foundational concept in wireless communications. It is universally known as Duty Cycling or Packet-Based Power Management. Instead of keeping the entire receiver circuitry fully powered and listening to static, receivers (like those using Bluetooth Low Energy or Zigbee protocols) operate in ultra-low-power sleep modes. They periodically power up only their demodulator and a basic correlator to scan for the synchronization word. When the correlator detects the synchronization word, it immediately generates an indication that valid data is arriving. This indication acts as a hardware interrupt or control signal to power up the higher-power domains (like the main processor, memory, or digital signal processors) to receive the rest of the packet. This prevents enormous amounts of wasted energy and battery drain. This specific methodology using synchronization detection to transition a circuit between power states has been documented in both academic literature and numerous patents for decades because the constituent components (a demodulator, a correlator, and a power management controller) are all standard digital logic elements.
Regarding claim 17 as described in claim 1 above, the functional components listed of a RF front-end, a Local Oscillator (LO), an Automatic Gain Control (AGC), a demodulator, and a frame controller represent the standard, classical layout of almost any modern digital wireless transceiver (such as Wi-Fi, Bluetooth, or cellular basebands). Isolating different circuit blocks into separate power domains is a mature technique known as Power Gating or Dynamic Voltage and Frequency Scaling (DVFS). It is universally used in RF integrated circuits (RFICs) to reduce battery drain and prevent cross-talk or noise interference (e.g., preventing the LO's switching noise from leaking into the sensitive front-end amplifier). Allocating specific circuit sections (like the front-end or demodulator) to independent power domains so they can be turned off or powered down individually is widely documented in existing literature and patents regarding power management.
Regarding claim 18, the use of a permanent power domain to control switchable, collapsible power domains is widely documented. It is the fundamental principle behind low-power SoCs and microcontrollers (e.g., ARM processors) to save battery. Selectively activating sections of a receiver circuit during its active “on-time” (duty cycling) is a common method used to minimize power consumption in transceivers.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over in view of O’SHEA and de Ruijter et al. (US 2016/0277177 A1), hereinafter “de Ruijter”.
Regarding claim 19, similar to the independent method claim 1, parts of the claim features recited in claim 19 are similar the claim features of claim 1 for the similar reasons described in claim 1 above. However, as amended in claim 19, both Jin and O’Shea fail to show or teach that the controlling power consumption of the means for receiving and demodulating the radio frequency signal based on signal arrival detection and, an average received signal power, and also detection of a synchronization word in a received packet.
De Ruijter illustrates a circuit arrangement for a receiver in FIG. 1 comprising: an antenna 15; a low noise amplifier (LNA) 20; a mixer 30; a reference or local oscillator (LO) frequency provided by LO 25; an analog to digital converter (ADC) 35; a signal processing circuitry 40 including a digital signal arrival (DSA) detector 48; and data processing circuitry 55.
De Ruijter also teaches that using “multi-tiered” signal detection and power-saving hierarchy designed to avoid wasting battery on environmental noise or irrelevant transmissions. This architecture includes: Instead of keeping the high-power receiver circuitry fully active 100% of the time, the radio relies on a low-power listening mode. By using the correlator and RSSI detectors (absolute and relative), the radio can sense if any actual radio frequency (RF) energy is present in the environment. The frequency offset detector ensures the signal is actually on the expected channel, preventing the radio from waking up to random adjacent-channel interference. If a signal is detected, the receiver evaluates the average received signal power to gauge the link quality. This helps determine if the transmission is strong enough to be reliably decoded, allowing the processor to ignore signals that are too weak to be useful. Before waking up the main microcontroller or keeping the demodulator fully powered for the duration of a long packet, the radio searches for a specific, predefined “Sync Word” (or preamble) in the packet header. This acts as a digital key. If the sync word matches, the radio confirms it is receiving a valid packet intended for this specific device.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement Jin’s wireless communication system to selectively modify the operation of a plurality LNAs of an LNA bank of a receiver circuit in order to implement a power saving mode by selectively bypassing LNAs as taught by O’Shea, thereby reducing the voltage swing at the LNA input to maximize protection of the LNA input, as taught by O’Shea in paragraph [0060], and taught by de Ruijter to improve Jin’s wireless communications device using multi-tiered means for periodically enabling and controlling power consumption of the means for receiving and demodulating the radio frequency signal based on signal arrival detection and, an average received signal power, and detection of a synchronization word in a received packet in order to utilize the low-power digital signal arrival (DSA) detection to keep the radio in "sleep" mode and use the Sync Word Detector as the final validation to power on only for valid data to improve the device's battery life extension from weeks to years.
Regarding claim 21, in additional to claim 19 described above, the examiner takes the Official Notice that the periodically enabling and controlling power consumption of the means for receiving and demodulating the radio frequency signal is further based on an indication of detection of an end of the received packet is technically known as packet-based duty cycling or early-termination power management, and has been a staple in wireless communications for years. For example, power-saving techniques in wireless transceivers revolve around a basic principle includes shut down or reduce power to the receiver circuitry as soon as it is no longer actively needed, and wake it up only when required. Systems routinely monitor signals (e.g., using Received Signal Strength Indicators (RSSI), preamble detection, or packet-length metadata embedded in the header). Once the receiver's logic detects that the packet's payload has completely arrived or identifies an empty/irrelevant packet it terminates the listening window early. Further, devices like Bluetooth, Wi-Fi, and ZigBee use similar mechanisms (like Discontinuous Reception (DRX) or Wake-Up Receivers (WUR)) to power down RF chains immediately after a data packet ends, rather than waiting for an arbitrary timer to expire.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al. relates to an integrated circuit for a modem processor includes processing units that are partitioned into "always-on" and "collapsible" power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing units in the power domain are not needed. A power control unit within an always-on power domain powers down the collapsible power domains after going into sleep and powers up these domains after waking up from sleep. Tasks for powering down the collapsible power domains may include (1) saving pertinent hardware registers for these power domains, (2) freezing output pins of the IC to minimally disturb external units, (3) clamping input pins of the collapsed power domains, (4) powering down a main oscillator and disabling the oscillator clock, and so on. Complementary tasks are performed for powering up the collapsed power domains.
SEVERINO et al. relates to an integrated circuit includes first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.
BHATTAD et al. relates to a method for communication includes a user equipment (UE) periodically awakening to monitor for a wake-up signal (WUS) in a wake-up signal search space, the wake-up signal having a shorter length than a length of a control channel communication to allow the UE to determine whether the UE should monitor for the control channel communication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
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/Young T. Tse/Primary Examiner, Art Unit 2632
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