Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of 1-18 in the reply filed on 19-20 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1-5 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiani et al. (US 6388208 B1) hereinafter Kiani in view of Kumar et al. (US 2019/0289710 A1).
Regarding claim 1, Kiani discloses, in Fig.1A and Fig.1C), a first via (26’) fabricated through the printed circuit board (see printed circuit board 10’ in Fig.1A), wherein the first via includes a first conductive metal plating (see 26a and 26b), the first via includes; a first via portion (26b) connected to a first ground trace (26b is connected to a ground layer) of the printed circuit board; and a second via portion (26a ) connected to a first trace (26a is connected to a signal trace), wherein the first and second via portions are formed in the first conductive metal plating (see 26a and 26b are formed in the plating); and a second via (see 66 in Fig.4) fabricated through the printed circuit board, wherein the second via includes a second conductive metal plating (see s and g forming a conductive plate in Fig.4), the second via includes ;a third via portion (see g in Fig.4) connected to a second ground trace (66a is connected to a ground trace) of the printed circuit board; and a fourth via portion connected to a second trace (s in Fig.4 is connected to a second signal trace) printed circuit board, wherein the third and fourth via portions are formed in the second conductive metal plating (see s and g formed in 66).
Kiani is silent with respect to the second via portion connected to a first trace of a differential pair of the printed circuit board and fourth via portion connected to a second trace of the differential pair of the printed circuit board
Kumar discloses a second via portion (see left via 124; Fig.1) connected to a first trace (left 126) of a differential pair of the printed circuit board and fourth via portion (see right via 124;Fig.1) connected to a second trace (see right 126) of the differential pair of the printed circuit board (see 100 in Fig.1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kumar to modify the second via portion and the fourth via portion of Kiani in order to transmit high speed electrical signals to perform various circuit operations.
Regarding claim 2, Kiani discloses wherein first and second sections (see left gap 29a and right gap 29b; Fig.1C) of the first conductive metal plating is removed to form the first and second via portions (see 26a and 26b).
Regarding claim 3, Kiani discloses wherein the first and second sections (29a and 29b; Fig.1C) are removed along a line of symmetry ( 28) of the first via (26’;see Fig.1C).
Regarding claim 4, Kiani discloses, wherein first and second sections of the second conductive metal plating is removed to form the third and fourth via portions ( see openings formed between s and g in Fig.4).
Regarding claim 5, Kiani discloses the first and second sections are removed along a line of symmetry of the second via. ( see openings formed between s and g in Fig.4).
Regarding claim 10, Kiani discloses a printed circuit board ( Fig.1A and Fig.1C) comprising a first via (26’) fabricated through the printed circuit board (see printed circuit board 10’ in Fig.1A), wherein the first via includes a first conductive metal plating (see 26a and 26b), the first via includes; a first via portion (26b) connected to a first ground trace (26b is connected to a ground layer) of the printed circuit board; and a second via portion (26a ) connected to a first trace (26a is connected to a signal trace), wherein the first and second via portions are formed in the first conductive metal plating (see 26a and 26b are formed in the plating); and a second via (see 66 in Fig.4) fabricated through the printed circuit board, wherein the second via includes a second conductive metal plating (see s and g forming a conductive plate in Fig.4), the second via includes ;a third via portion (see g in Fig.4) connected to a second ground trace (66a is connected to a ground trace) of the printed circuit board; and a fourth via portion connected to a second trace (s in Fig.4 is connected to a second signal trace) printed circuit board, wherein the third and fourth via portions are formed in the second conductive metal plating (see s and g formed in 66).
Kiani is silent with respect to the second via portion connected to a first trace of a differential pair of the printed circuit board and fourth via portion connected to a second trace of the differential pair of the printed circuit board
Kumar discloses a second via portion (see left via 124; Fig.1) connected to a first trace (left 126) of a differential pair of the printed circuit board and fourth via portion (see right via 124;Fig.1) connected to a second trace (see right 126) of the differential pair of the printed circuit board (see 100 in Fig.1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kumar to modify the second via portion and the fourth via portion of Kiani in order to transmit high speed electrical signals to perform various circuit operations.
Regarding claim 11, Kiani discloses wherein first and second sections (see left gap 29a and right gap 29b; Fig.1C) of the first conductive metal plating is removed to form the first and second via portions (see 26a and 26b).
Regarding claim 12, Kiani discloses wherein the first and second sections (29a and 29b; Fig.1C) are removed along a line of symmetry ( 28) of the first via (26’;see Fig.1C).
Regarding claim 13, Kiani discloses, wherein first and second sections of the second conductive metal plating is removed to form the third and fourth via portions ( see openings formed between s and g in Fig.4).
Regarding claim 14, Kiani discloses the first and second sections are removed along a line of symmetry of the second via. ( see openings formed between s and g in Fig.4).
Allowable Subject Matter
Claim 6-9 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claim 6-7, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the first ground trace is located on a first side of the first trace. " in combination with the remaining limitations of the claim 1.
Regarding claim 8, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a void section located around the second via portion and not around the first via portion" in combination with the remaining limitations of the claim 1.
Regarding claim 9, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a void section located around the fourth via portion and not around the third via portion." in combination with the remaining limitations of the claim 1.
Regarding claim 15-16, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the first ground trace is located on a first side of the first trace. " in combination with the remaining limitations of the claim 10.
Regarding claim 17, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a void section located around the second via portion and not around the first via portion" in combination with the remaining limitations of the claim 10.
Regarding claim 18, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a void section located around the fourth via portion and not around the third via portion." in combination with the remaining limitations of the claim 10/
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
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