DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/737,046 has a total of 20 elected claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 09/05/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cox et al. (US pub. 2018/0254079), hereinafter, “Cox”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 11 and 20, Cox discloses a memory module, comprising: a first memory channel, comprising: a plurality of first random access memory (RAM) chips [subarrays 272 of fig. 2B, 3B; see paragraph 0038, which discloses “in one example, multichip memory 120 represents a memory package to contain two low power double data rate (LPDDR) memory chips or memory dies 122. The memory dies or memory chips can be referred to as DRAM (dynamic random access memory) devices or dies. Multichip memory 120 includes circuitry or logic to enable the selection of CAS application to the two LPDDR dies” and paragraphs 0035 and 0047] each comprising: a plurality of first data output pins [see figs. 3B and 9, paragraph 0035, which discloses “memory die 122 can include two or more memory chips. Each die can support one or more channels, referring to combinations of signal lines for CA bus and corresponding DQ bus. DQ paths 126 represent data paths from the packaging of multichip memory 120 to memory dies 122. DQ paths 126 can be or include external packaging interface hardware such as a connector, ball, or pin, and an electrical pathway to a corresponding pin or pad of memory dies 122. In one example, the signal lines for DQ and ECC on DQ bus 114 are routed in a way that selected lines connect to selected I/O (input/output) data pins of memory dies 122. In one example, DQ paths 126 can be global I/O paths, and a path can be shared among multiple I/O interfaces of memory dies 122. For example, the same DQ path 126 can be routed to an I/O interface of two separate memory dies 122. The path can then be switched or selected between the two memory dies 122 to enable sharing of the communication pathway in time based on switching between which device accesses it at what time”]; a first command/address (C/A) input; and a first chip select pin; at least one first C/A bus coupled to at least one first C/A input of each of the plurality of first RAM chips (see fig. 3B and paragraph 0035); a plurality of first chip select inputs each coupled to a respective first chip select pin of a first RAM chip of the plurality of first RAM chips [see paragraph 0037, which discloses “in system 100, CAS select 124 provides the ability within multichip memory 120 to select among multiple different CAS signals to cause memory dies 122 to access different portions of their memory arrays. Thus, in one example, memory dies 122 can operate in byte mode and be selected to access different portions of their memory arrays through the same DQ I/O interfaces. In byte mode, memory dies 122 restrict access to only selected ones of their I/O ports (e.g., 8 DQ pins instead of 16 DQ pins on the die). But with CAS selection, the memory die can apply the memory transaction to a different portion of the memory array, resulting in using more of the memory array. Otherwise, for example, certain I/O would not ever be used, and much of the memory array would be unused”]; and a plurality of first parallel data buses each coupled to the plurality of first data output pins of a respective first RAM chip of the plurality of first RAM chips [see paragraph 0102, which discloses “in one example, CMD 934 represents signal lines shared in parallel with multiple memory devices. In one example, multiple memory devices share encoding command signal lines of CMD 934, and each has a separate chip select (CS_n) signal line to select individual memory devices”]; wherein: each first RAM chip of the plurality of first RAM chips is configured to assert a first data word on a first parallel data bus of the plurality of first parallel data buses coupled to the first RAM chip, in response to a memory read address on the at least one first C/A input and a chip select enable signal on a first chip select input of the plurality of first chip select inputs coupled to the first chip select pin of the first RAM chip (see paragraphs 0037 and 0105).
3. As per claim 2, Cox discloses “The memory module of claim 1” [See rejection to claim 1 above], further comprising: a second memory channel, comprising: a plurality of second RAM chips (subarrays 282 of fig. 2B, 3B; see paragraph 0038) each comprising: a plurality of second data output pins; a second C/A input; and a second chip select pin; a second C/A bus coupled to the second C/A input of each of the plurality of second RAM chips; a plurality of second chip select inputs each coupled to a respective second chip select pin of a second RAM chip of the plurality of second RAM chips; and a plurality of second parallel data buses each coupled to the plurality of second data output pins of a respective second RAM chip of the plurality of second RAM chips; wherein: each second RAM chip of the plurality of second RAM chips is configured to assert a second data word on a second parallel data bus of the plurality of second parallel data buses coupled to the second RAM chip, in response to a memory read address on the second C/A input and a chip select enable signal on a second chip select input of the plurality of second chip select inputs coupled to the second chip select pin of the second RAM chip (see fig. 3B, paragraphs 0035, 0038 and 0047).
4. As per claims 3 and 16, Cox discloses wherein: the plurality of first RAM chips comprises eight (8) first RAM chips; the plurality of first data output pins for each first RAM chip of the plurality of first RAM chips comprises four (4) first data output pins; the plurality of first chip select inputs comprises eight (8) first chip select inputs; the plurality of first parallel data buses comprises eight (8) first parallel data buses each 4-bits wide; and each first RAM chip of the eight (8) first RAM chips is configured to assert the first data word comprising a 4-bit data word on a first parallel data bus of the eight (8) first parallel data buses coupled to the first RAM chip, in response to a memory read address on the at least one first C/A input and a chip select enable signal on a first chip select input of the eight (8) first chip select inputs coupled to the first chip select pin of the first RAM chip (see paragraphs 0035, 0038 and 0047).
5. As per claim 4, Cox discloses wherein: the at least one first C/A bus coupled to the at least one first C/A input comprises a first C/A bus coupled to the first C/A input of each of a first four (4) first RAM chips of the eight (8) first RAM chips and a second C/A bus coupled to a second C/A input of each of a second four (4) first RAM chips of the eight (8) first RAM chips not included in the first four (4) first RAM chips; wherein: each of a first RAM chip of the first four (4) first RAM chips is configured to assert the first data word comprising a first 4-bit data word on a first parallel data bus of the plurality of first parallel data buses coupled to the first RAM chip, in response to the memory read address on the first C/A input and the chip select enable signal on the first chip select input of the plurality of first chip select inputs coupled to the first chip select pin of the first RAM chip; and each of a second RAM chip of the second four (4) first RAM chips is configured to assert a second data word comprising a second 4-bit data word on a second parallel data bus of the plurality of first parallel data buses coupled to the second RAM chip, in response to the memory read address on the second C/A input and the chip select enable signal on the first chip select input of the plurality of first chip select inputs coupled to the first chip select pin of the second RAM chip (see paragraphs 0035, 0038 and 0047).
6. As per claim 5, Cox discloses wherein: the plurality of first RAM chips comprises eight (8) first RAM chips; the plurality of first data output pins for each first RAM chip of the plurality of first RAM chips comprises eight (8) first data output pins; the plurality of first chip select inputs comprises eight (8) first chip select inputs; the plurality of first parallel data buses comprises eight (8) first parallel data buses each 8-bits wide; and each first RAM chip of the eight (8) first RAM chips is configured to assert the first data word comprising an 8-bit data word on a first parallel data bus of the eight (8) first parallel data buses coupled to the first RAM chip, in response to the memory read address on the at least one first C/A input and the chip select enable signal on the first chip select input of the eight (8) first chip select inputs coupled to the first chip select pin of the first RAM chip (see paragraphs 0035, 0038 and 0047).
7. As per claim 6, Cox discloses wherein: the at least one first C/A bus coupled to the at least one first C/A input comprises a first C/A bus coupled to the first C/A input of each of a first four (4) first RAM chips of the eight (8) first RAM chips and a second C/A bus coupled to a second C/A input of each of a second four (4) first RAM chips of the eight (8) first RAM chips not included in the first four (4) first RAM chips; wherein: each of a first RAM chip of the first four (4) first RAM chips is configured to assert the first data word comprising a first 8-bit data word on a first parallel data bus of the plurality of first parallel data buses coupled to the first RAM chip, in response to the memory read address on the first C/A input and the chip select enable signal on the first chip select input of the plurality of first chip select inputs coupled to the first chip select pin of the first RAM chip; and each of a second RAM chip of the second four (4) first RAM chips is configured to assert a second data word comprising a second 8-bit data word on a second parallel data bus of the plurality of first parallel data buses coupled to the second RAM chip, in response to the memory read address on the second C/A input and the chip select enable signal on the first chip select input of the plurality of first chip select inputs coupled to the first chip select pin of the second RAM chip (see paragraphs 0035, 0038 and 0105).
8. As per claim 7, Cox discloses wherein: the plurality of first RAM chips comprises four (4) first RAM chips; the plurality of second RAM chips comprises four (4) second RAM chips; the plurality of first data output pins for each first RAM chip of the four (4) first RAM chips comprises eight (8) first data output pins; the plurality of second data output pins for each second RAM chip of the four (4) second RAM chips comprises eight (8) second data output pins; the plurality of first chip select inputs comprises four (4) first chip select inputs; the plurality of second chip select inputs comprises four (4) second chip select inputs; the plurality of first parallel data buses comprises four (4) first parallel data buses each 8-bits wide; and the plurality of second parallel data buses comprises four (4) second parallel data buses each 8-bits wide; and each first RAM chip of the four (4) first RAM chips is configured to assert the first data word comprising a first 8-bit data word on a first parallel data bus of the four (4) first parallel data buses coupled to the first RAM chip, in response to a first memory read address on the first C/A input and the chip select enable signal on the first chip select input of the four (4) first chip select inputs coupled to the first chip select pin of the first RAM chip; and each second RAM chip of the four (4) second RAM chips is configured to assert the second data word comprising a second 8-bit data word on a second parallel data bus of the four (4) second parallel data buses coupled to the second RAM chip, in response to a second memory read address on the second C/A input and the chip select enable signal on the second chip select input of the four (4) second chip select inputs coupled to the second chip select pin of the second RAM chip (see paragraphs 0035, 0038 and 0105).
9. As per claims 8 and 19, Cox discloses wherein the plurality of first RAM chips comprises a plurality of dynamic RAM (DRAM) chips (see paragraph 0038).
10. As per claim 9, Cox discloses wherein the plurality of first DRAM chips comprises a plurality of first double data rate (DDR) DRAM chips (see paragraphs 0030 and 0096).
11. As per claim 12, Cox discloses wherein the memory module is configured to not assert another data word on any of the plurality of first parallel data buses not including the first parallel data bus in response to the memory read access (see paragraph 0123. Note, the condition of this claim/limitation is met when power is removed from the system).
12. As per claim 13, Cox discloses wherein the memory controller is further configured to generate a plurality of memory read accesses by being configured to: sequentially assert a plurality of memory addresses on the at least one first C/A bus for the plurality of first RAM chips; and sequentially assert a plurality of chip select enable signals on the plurality of first chip select inputs coupled to the plurality of first RAM chips according to the respective plurality of memory addresses; the memory module configured to sequentially assert a plurality of data words on the respective plurality of first parallel data buses coupled to the respective plurality of first RAM chips in response to the respective plurality of memory read accesses (see paragraph 0104 and 0134).
13. As per claim 14, Cox discloses wherein the memory controller is further configured to generate a memory read access for a memory line by being configured to: sequentially assert a plurality of memory addresses for the memory line on the at least one first C/A bus for each of the plurality of first RAM chips; and sequentially assert a plurality of chip select enable signals on the plurality of first chip select inputs coupled to each of the plurality of first RAM chips according to the respective plurality of memory addresses; the memory module configured to sequentially assert a plurality of data words on the plurality of first parallel data buses coupled to the respective plurality of first RAM chips in response to the memory read access (see paragraph 0102 and 0104).
14. As per claim 15, Cox discloses wherein the memory controller is further configured to generate a memory line read access by being configured to: sequentially assert a plurality of memory addresses for a memory line on the at least one first C/A bus for the addressed RAM chip of the plurality of first RAM chips; and sequentially assert a plurality of chip select enable signals on the first chip select input of the plurality of first chip select inputs coupled to the addressed RAM chip according to the plurality of memory addresses; the memory module configured to sequentially assert a plurality of data words on the first parallel data bus of the plurality of parallel data buses coupled to the respective addressed RAM chip in response to the memory line read access (see paragraph 0104 and 0134).
15. As per claim 17, Cox discloses wherein: the plurality of first RAM chips comprises eight (8) first RAM chips; the plurality of first data output pins for each first RAM chip of the plurality of first RAM chips comprises eight (8) first data output pins; the plurality of first chip select inputs comprises eight (8) first chip select inputs; the plurality of first parallel data buses comprises eight (8) first parallel data buses each 8-bits wide; and the memory controller is configured to: assert the chip select enable signal on a first chip select input of the eight (8) first chip select inputs coupled to the first chip select pin of the first RAM chip; and the memory module is configured to assert the first data word of the first data width by being configured to assert the first data word comprising an 8-bit data word on a first parallel data bus of the eight (8) first parallel data buses coupled to the first RAM chip (see paragraphs 0035, 0038 and 0047)..
16. As per claim 18, Cox discloses wherein: the memory controller is further configured to: assert a second chip select enable signal on a first chip select input of the eight (8) first chip select inputs coupled to the first chip select pin of another first RAM chip of the plurality of first RAM chips; and the memory module is further configured to assert a second data word of the first data width by being configured to assert the second data word comprising an 8-bit data word on another first parallel data bus of the eight (8) first parallel data buses coupled to the other first RAM chip (see paragraphs 0035, 0038 and 0047)..
Claim Rejections - 35 USC § 103
17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over Cox et al. (US pub. 2018/0254079), hereinafter, “Cox”, in view of Sutera et al. (US pub. 2024/0004577), hereinafter, “Sutera”.
19. As per claim 10, Cox discloses “The memory module of claim 1” [See rejection to claim 1 above], but fails to expressly discloses integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Sutera discloses integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter [see claim 11 of Sutera, which discloses “the processor-based device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter”].
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Sutera’s teaching of a method for extending functionality of memory controllers in a processor-based device having a memory access intercept circuit that is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request, into Cox’s teaching a multi-die memory device having fixed bandwidth interfaces to selectively connect portions of the interfaces of multiple memory dies as a memory channel for the multi-die device, for the benefit of improving latency via encryption and decryption being performed at least in part in parallel with associated memory controller issuing commands.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights