DETAILED ACTION
The present application, filed 06/07/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 3, 9, 10, and 16 are objected to because of the following informalities:
Re claim 3, it appears that “a change” (line 2) should be “the change”. It appears that “the current feedback signal” (line 3) should be “the peak current feedback signal”.
Re claim 9, it appears that “the current feedback signal” (line 3) should be “the peak current feedback signal”.
Re claim 10, it appears that “a change” (line 1-2) should be “the change”.
Re claim 16, it appears that “the current feedback signal” (line 3) should be “the peak current feedback signal”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 15, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nene (US 2014/0239922).
Re claim 1, Nene teaches an apparatus [100, Fig 1A, 2A], comprising: a switched power converter [102] comprising an inductor [as described in paragraph 5], the switched power converter to: produce a voltage output [Vout] based on a pulse-width modulated (PWM) signal [PWM(1), PWM(2), PWM(n), also referred as PWM waveforms, paragraph 8]; and produce a peak current feedback signal [Ifb], the peak current feedback signal representative of a peak current through the inductor [paragraph 5]; a comparator [216(1) details in Fig 2A] to generate a PWM control input (PCI) signal [output of 216(1)] based on whether the peak current feedback signal has reached a reference current [Ipref]; a PWM generation circuit [216(2)] to generate the PWM signal to control switching of the switched power converter based on the PCI signal [Fig 2A, signal passes through 216(2) to produce the PWM waveforms for 102]; and a synchronization circuit [216(3)] to delay a change in the PCI signal [paragraph 33].
Re claim 3, Nene teaches wherein the synchronization circuit is to delay a change in the PCI signal issued by the comparator from reaching the PWM generation circuit when the current feedback signal has reached the reference current [paragraph 36, 216(3) becomes active when the sensed current signal 220 reaches the peak current Ipeak].
Re claim 15, Nana teaches a method [100, Fig 1A, 2A], comprising: with a switched power converter [102], the switched power converter comprising an inductor [as described in paragraph 5]: producing a voltage output [Vout] based on a pulse-width modulated (PWM) signal [PWM(1), PWM(2), PWM(n), also referred as PWM waveforms, paragraph 8]; and producing a peak current feedback signal [Ifb], the peak current feedback signal representative of a peak current through the inductor [paragraph 5]; generating a PWM control input (PCI) signal [output of 216(1)] based on whether the peak current feedback signal has reached a reference current [Ipref]; generating the PWM signal to control switching of the switched power converter based on the PCI signal [Fig 2A, signal passes through 216(2) to produce the PWM waveforms for 102]; and with a synchronization circuit [216(3)], delaying a change in the PCI signal [paragraph 33].
Re claim 17, Nana teaches delaying the change in the PCI signal from reaching a PWM generation circuit [216(2)] when the peak current feedback signal has reached the reference current [paragraph 36, 216(3) becomes active when the sensed current signal 220 reaches the peak current Ipeak].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nene in view of Chen et al. (“Chen”, US 2016/0006358).
Re claim 2, Nene teaches the limitations as applied to the claim above but does not teach wherein the synchronization circuit is to delay the change in the PCI signal through delay of a change in the peak current feedback signal from reaching the comparator to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current.
Chen teaches a device [Fig 5] having a circuit [534] configured to delay the change in the PCI signal [output of 5335] through delay of a change in the peak current feedback signal [measured from 531] from reaching the comparator [5335, 534 delays the current for a blanking period as described in paragraph 49] to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current [output of 5334]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nana to include the features of Chen because it is used to shut down or mask the circuit during dangerous operating condition, thus improving the safety of the device, which increases efficiency.
Re claim 16, Nene teaches the limitations as applied to the claim above but does not teach wherein the synchronization circuit is to delay the change in the PCI signal through delay of a change in the peak current feedback signal from reaching the comparator to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current.
Chen teaches a device [Fig 5] having a circuit [534] configured to delay the change in the PCI signal [output of 5335] through delay of a change in the peak current feedback signal [measured from 531] from reaching the comparator [5335, 534 delays the current for a blanking period as described in paragraph 49] to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current [output of 5334]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nana to include the features of Chen because it is used to shut down or mask the circuit during dangerous operating condition, thus improving the safety of the device, which increases efficiency.
Claims 4-7 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nene in view of Spini et al. (“Spini”, US 2013/0057323).
Re claim 4, Nene teaches the limitations as applied to the claim above but does not teach wherein the synchronization circuit comprises a latch to maintain the PCI signal based on a leading edge blanking (LEB) signal.
Spini teaches a device [100, Fig 5] having a synchronization circuit [10] comprising a latch [5] to maintain the PCI signal [Vc] based on a leading edge blanking (LEB) signal [output of 10 to 5, paragraph 44]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because latches are known for retaining its state without continuous power which makes it ideal for low-power or battery-operated devices, thus improving the utility of the device, which increases efficiency.
Re claim 5, Nene teaches the limitations as applied to the claim above but does not teach wherein the LEB signal is to mask the PCI signal for a period of time when the PWM signal transitions.
Spini teaches a device [Fig 9] wherein the LEB signal [output of 10 to 5] is to mask the PCI signal for a period of time [Tb] when the PWM signal transitions [paragraph 58 teaches mask block 202 that blanks the output for time Tb]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 6, Nene teaches the limitations as applied to the claim above but does not teach wherein: the synchronization circuit is to detect a PWM output transition; based upon the PWM output transition, begin counting a LEB period; during the LEB period, hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition.
Spini teaches wherein: the synchronization circuit is to detect a PWM output transition [transition of output Q of 5]; based upon the PWM output transition, begin counting a LEB period [function of MF10]; during the LEB period [T2 as described in paragraph 56], hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition [signal R transitions after the period]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 7, Nene teaches the limitations as applied to the claim above but does not teach wherein the latch is reset at a termination of the LEB period.
Spini teaches wherein the latch is reset at a termination of the LEB period [paragraph 58]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 18, Nene teaches the limitations as applied to the claim above but does not teach delaying the change in the PCI signal with a latch to maintain the PCI signal based on a leading edge blanking (LEB) signal.
Spini teaches a device [100, Fig 5] having a synchronization circuit [10] comprising a latch [5] to maintain the PCI signal [Vc] based on a leading edge blanking (LEB) signal [output of 10 to 5, paragraph 44]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because latches are known for retaining its state without continuous power which makes it ideal for low-power or battery-operated devices, thus improving the utility of the device, which increases efficiency.
Re claim 19, Nene teaches the limitations as applied to the claim above but does not teach wherein the LEB signal is to mask the PCI signal for a period of time when the PWM signal transitions.
Spini teaches a device [Fig 9] wherein the LEB signal [output of 10 to 5] is to mask the PCI signal for a period of time [Tb] when the PWM signal transitions [paragraph 58 teaches mask block 202 that blanks the output for time Tb]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 20, Nene teaches the limitations as applied to the claim above but does not teach wherein: the synchronization circuit is to detect a PWM output transition; based upon the PWM output transition, begin counting a LEB period; during the LEB period, hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition.
Spini teaches wherein: the synchronization circuit is to detect a PWM output transition [transition of output Q of 5]; based upon the PWM output transition, begin counting a LEB period [function of MF10]; during the LEB period [T2 as described in paragraph 56], hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition [signal R transitions after the period]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Claims 8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nene in view of Guo et al. (“Guo”, US 2022/0057323).
Re claim 8, Nene teaches a system [100, Figs 1A, 2A] comprising: a switched power converter [102] comprising an inductor [as described in paragraph 5], the switched power converter to: produce a voltage output [Vout] based on a pulse-width modulated (PWM) signal [PWM(1)-PWM(n)]; and produce a peak current feedback signal [Ifb], the peak current feedback signal representative of a peak current through the inductor [paragraph 5]; an error calculation circuit [110] to receive the feedback voltage at an input and to output an error signal [Vcomp]; a slope compensation circuit [114], the slope compensation circuit to modify the error signal and to generate a slope compensation output [Ipref]; a comparator [216(1), details in Fig 2A] to generate a PWM control input (PCI) signal [output of 216(1)] based on whether the peak current feedback signal has reached a reference current [Ipref] indicated by the slope compensation output [Ipref is the output of the slope compensation output]; a PWM generation circuit [216(2)] to generate the PWM signal to control switching of the switched power converter based on the PCI signal [as shown in Fig 2A, signal passes through 216(2) to produce the PWM waveforms for 102]; and a synchronization circuit [216(3)] to delay a change in the PCI signal [paragraph 33], but does not teach a resistive voltage divider coupled to the voltage output, the resistive voltage divider to produce a feedback voltage.
Guo teaches a device [Fig 2] having a resistive voltage divider [208] coupled to the voltage output [200A], the resistive voltage divider to produce a feedback voltage [VFB]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Guo because it is used as a simple and cost-effective solution for voltage management, thus improving the utility of the device, which increases efficiency.
Re claim 10, Nene teaches wherein the synchronization circuit is to delay a change in the PCI signal issued by the comparator from reaching the PWM generation circuit when the current feedback signal has reached the reference current [paragraph 36, 216(3) becomes active when the sensed current signal 220 reaches the peak current Ipeak].
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nene in view of Guo and Chen.
Re claim 9, Nene teaches the limitations as applied to the claim above but does not teach wherein the synchronization circuit is to delay the change in the PCI signal through delay of a change in the peak current feedback signal from reaching the comparator to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current.
Chen teaches a device [Fig 5] having a circuit [534] configured to delay the change in the PCI signal [output of 5335] through delay of a change in the peak current feedback signal [measured from 531] from reaching the comparator [5335, 534 delays the current for a blanking period as described in paragraph 49] to prevent the comparator from changing the PCI signal when the peak current feedback signal has reached the reference current [output of 5334]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nana to include the features of Chen because it is used to shut down or mask the circuit during dangerous operating condition, thus improving the safety of the device, which increases efficiency.
Claims 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nene in view of Guo and Spini.
Re claim 11, Nene teaches the limitations as applied to the claim above but does not teach wherein the synchronization circuit comprises a latch to maintain the PCI signal based on a leading edge blanking (LEB) signal.
Spini teaches a device [100, Fig 5] having a synchronization circuit [10] comprising a latch [5] to maintain the PCI signal [Vc] based on a leading edge blanking (LEB) signal [output of 10 to 5, paragraph 44]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because latches are known for retaining its state without continuous power which makes it ideal for low-power or battery-operated devices, thus improving the utility of the device, which increases efficiency.
Re claim 12, Nene teaches the limitations as applied to the claim above but does not teach wherein the LEB signal is to mask the PCI signal for a period of time when the PWM signal transitions.
Spini teaches a device [Fig 9] wherein the LEB signal [output of 10 to 5] is to mask the PCI signal for a period of time [Tb] when the PWM signal transitions [paragraph 58 teaches mask block 202 that blanks the output for time Tb]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 13, Nene teaches the limitations as applied to the claim above but does not teach wherein: the synchronization circuit is to detect a PWM output transition; based upon the PWM output transition, begin counting a LEB period; during the LEB period, hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition.
Spini teaches wherein: the synchronization circuit is to detect a PWM output transition [transition of output Q of 5]; based upon the PWM output transition, begin counting a LEB period [function of MF10]; during the LEB period [T2 as described in paragraph 56], hold the PCI signal constant; and after the LEB period, allow the PCI signal to transition [signal R transitions after the period]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Re claim 14, Nene teaches the limitations as applied to the claim above but does not teach wherein the latch is reset at a termination of the LEB period.
Spini teaches wherein the latch is reset at a termination of the LEB period [paragraph 58]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Nene to include the features of Spini because it is used as a low cost means for power timing, thus improving the utility of the device, which increases efficiency.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Examiner, Art Unit 2838