DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1, 3-5, 7-18 are pending in this amended application.
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. The claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Claims 1, 3-5, 7-18 are directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 is rejected under 35 U.S.C. 101, because the claimed invention directed to abstract idea without significantly more. The claim recites “an image inspection apparatus comprising: an image reader; and a multi-core central processing unit, the multi-core central processing unit comprising: a generation controller that controls, based on acquired image data, generation of a reference image to be used for inspection of an image formed on a recording medium; and an inspection controller that controls, based on the reference image, execution of inspection of the image formed on the recording medium, which has been read by the image reader, and wherein the generation controller and the inspection controller are configured by assigning a core to each controller in the multi-core central processing unit”.
The claim limitation of “a generation controller that controls, based on acquired image data, generation of a reference image to be used for inspection of an image formed on a recording medium; and an inspection controller that controls, based on the reference image, execution of inspection of the image formed on the recording medium, which has been read by the image reader, and wherein the generation controller and the inspection controller are configured by assigning a core to each controller in the multi-core central processing unit”, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer component. That is, other than reciting “by a generation controller”, “by an inspection controller” nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the “by a generation controller”, “by an inspection controller” in the context of this claim encompasses the user manually acquiring image data for inspection and generates reference image for execution of the inspection of image data. Similarly, the limitations of acquiring image data for inspection and generates reference image for execution of the inspection of image data as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer component. For example, but for the by “by a generation controller, by an inspection controller” in the context of this claim encompasses the user thinking that the image inspection apparatus should be acquiring image data for inspection and generates reference image for execution of the inspection of image data. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim doesn’t recite even one additional element – using a generation controller, an inspection controller to perform both the generation, formation & execution steps. The inspection controller & inspection controller in last step recited at a high-level of generality (i.e., as a generic control unit performing a generic computer function of ranking information based on a determined amount of use) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, the provided claimed limitations does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include any additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the claimed limitations using a generation controller & an inspection controller to perform the generation, formation & execution steps amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
The other independent claims 9-10 are obviously claimed the same subject matter as found in the claim 1 and therefore would be rejected based on same rationale applied on claim 1.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 8-11, 15, 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kobayashi, US Pub 2023/0336668.
As to claim 1 [independent], Kobayashi teaches an image inspection apparatus comprising:
an image reader [fig. 3, element 310; 0034, 0041]; and
a multi-core central processing unit [fig. 3, element 302; 0042], the multi-core central processing unit comprising [fig. 3, element 302; 0042 Kobayashi teaches processor 302 (CPU 302) contains at least dual cores or multiple cores (e.g., dual-core, quad-core) to handle multiple demanding tasks simultaneously such as scanning image data, generating reference image from the scanned image data and performes inspection process/task based on assigned core to each scanning, generating & inspecting units]:
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a generation controller [fig. 3, element 302; 0042] that controls, based on acquired image data, generation of a reference image to be used for inspection of an image formed on a recording medium [fig. 3, element 110 & fig. 4; 0047, 0054-0055 Kobayashi teaches the inspection device acquires image data as print data for inspection purpose, the image reading device 310 scans the acquired image data and generates a reference image from the scanned image data (e.g., fig. 4, step 402; 0054)]; and
an inspection controller [fig. 3, element 305; 0042, 0044] that controls, based on the reference image, execution of inspection of the image formed on the recording medium, which has been read by the image reader [fig. 3, element 305; 0042, 0044, 0055-0056 Kobayashi teaches executes the inspection process of the scanned image based on the reference image as the correct image (e.g., 0044)], and
wherein the generation controller and the inspection controller are configured by assigning a core to each controller in the multi-core central processing unit [fig. 3, element 302; 0042 Kobayashi teaches processor 302 (CPU 302) contains at least dual cores or multiple cores (e.g., dual-core, quad-core) to handle multiple demanding tasks simultaneously such as scanning image data, generating reference image from the scanned image data and performed inspection process/task based on assigned core to each scanning, generating & inspecting units].
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As to claim 8 [dependent from claim 1], Kobayashi teaches wherein the generation of the reference image and the formation of the image on the recording medium are performed in parallel [fig. 4; 0054-0055 Kobayashi teaches that the inspection device 110 acquires image data as printed image data on a sheet for inspection purpose, the image reading device 310 in parallel scans the acquired image data printed image data and generates a reference image from the scanned image data (e.g., fig. 4, step 402; 0054)].
As to claims 9-10 [independent], However, the independent claims 9-10 essentially claimed same subject matter as claimed in the independent claim 1 for/and/with other claim limitations, and are therefore the independent claims 9-10 would be rejected based on same rationale as applied to the independent claim 1.
As to claim 11 [dependent from claim 1], Kobayashi teaches a formation controller that controls, based on the acquired image data, formation of the image on the recording medium formed with an image former [0039, 0041, 0054-0055 Kobayashi teaches that the printer unit 210 correspond to an image former prints the received binary bitmap data on a sheet using color material. The processor 202 sends an instruction to the printer unit 210 on the basis of the printing instruction from the user stored in the memory 203. For example, when the instruction from the user is to print on coated paper, the CPU 202 sends an instruction to the printer unit 210 to output a sheet from a non-illustrated sheet cassette storing coated paper inside the printer 100 (e.g., 0039). Then the inspection device 110 acquires image data as print data for inspection purpose, the image reading device scans the acquired image data and generates a reference image from the scanned image data (e.g., fig. 4, step 402; 0054-0055)];
wherein the generation controller, the formation controller, and the inspection controller are configured by assigning a core to each controller in a multi-core central processing unit (CPU) [fig. 3, element 302; 0042 Kobayashi teaches processor 302 (CPU 302) contains at least dual cores or multiple cores (e.g., dual-core, quad-core) to handle multiple demanding tasks simultaneously such as scanning image data, generating reference image from the scanned image data and performed inspection process/task based on assigned core to each scanning, generating & inspecting units].
As to claim 15 [dependent from claim 11], Kobayashi teaches wherein a core is assigned to the generation controller in preference to the inspection controller [fig. 3, element 302; 0042 Kobayashi teaches processor 302 (CPU 302) contains at least dual cores or multiple cores (e.g., dual-core, quad-core) to handle multiple demanding tasks simultaneously such as scanning image data, generating reference image from the scanned image data and performes inspection process/task based on assigned core to each scanning, generating & inspecting units].
As to claim 18 [dependent from claim 11], Kobayashi teaches the image former [0039, 0041 Kobayashi teaches that the printer unit 210 correspond to the image former prints the received binary bitmap data on a sheet using color material].
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 3-5, 7, 12-14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi, US Pub 2023/0336668 in view of Mutsuno, US Pub 2023/0101468.
As to claim 3 [dependent from claim 1], Kobayashi and Matsuno combining together teach wherein the number of cores assigned to each hardware processor is changed based on an inspection condition for the inspection [fig. 3, element 302; 0042 Kobayashi teaches processor 302 (CPU 302) contains at least dual cores or multiple cores (e.g., dual-core, quad-core) to handle multiple demanding tasks simultaneously such as scanning image data, generating reference image from the scanned image data and performed inspection process/task based on assigned core to each scanning, generating & inspecting units].
While, Matsuno teaches the claim recited based on an inspection condition for the inspection [paras., 0061-0071 that the job/inspection orchestration, multi-page IDs, and conditions determining inspection flow. Dynamically reallocating cores among concurrently running functional blocks based on inspection load/conditions is a routine, predictable scheduling optimization to satisfy throughput/latency constraints].
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate Mutsuno teaching to number of corers to perform inspection based on the changed condition of the inspection to modify Kobayashi’s teaching to equipped with second core that registers the image data received as the reference image from the printing apparatus, and notifies the printing apparatus of completion of registration of the reference image, and inspects a sheet on which printing is performed in the printing apparatus in response to instruction for inspection. The suggestion/motivation for doing so would have been benefitted to the user to adjust core allocations in response to varying inspection conditions (e.g., higher inspection level or more variable regions causing increased compute load) to maintain line speed and reduce inspection latency, yielding a predictable improvement.
As to claim 4 [dependent from claim 3], Kobayashi teaches wherein the inspection condition includes at least one of the number of inspection exclusion regions, the number of variable regions, an amount of information in a variable region, and an inspection level [figs. 4, 6; 0058-0064 Kobayashi teaches that the inspection device obtaining an inspection target image with inspection settings that includes indicating variable regions, levels etc., in which the inspection process to be executed].
As to claim 5 [dependent from claim 1], Mutsuno teaches wherein cores are assigned to the generation controller and the inspection controller in preference to a formation controller [fig. 2b; 0033-0041 Mutsuno that the each CPU as shown in fig. 2b having at least one core assigned and the generation & inspection processors have preference over the formation processor].
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate Mutsuno teaching to employ the first hardware processor, the second hardware processor, and the third hardware processor operates independently to modify Kobayashi’s teaching to obtains image data for printing from print job, and registers the image data as a reference image in an inspection apparatus which comprises a second controller that comprises multiple second processors and registers the image data received as the reference image from the printer, and notifies the printer of completion of registration of the reference image, and inspects a sheet on which printing is performed in the printer in response to instruction for inspection. The suggestion/motivation for doing so would have been benefitted to the user to have system prevents inspection failure caused by executing print job, and provides inspection instruction before the reference image is registered in the inspection apparatus.
As to claim 7 [dependent from claim 2], Kobayashi and Matsuno combining together teach wherein in a case where an inspection level is changed during the inspection of the image [figs. 4, 6; 0058-0064 Kobayashi teaches that the inspection device obtaining an inspection target image with inspection settings that includes indicating variable regions, levels etc., in which the inspection process to be executed], While, Matsuno teaches the ratio of the cores assigned to the first hardware processor and the third hardware processor is changed based on the change in the inspection level [0061-0074 Matsuno teaches that the multi-processor providing control context in which computational resources are allocated across functional blocks].
It would have been obvious to a person of ordinary skill in the art, at the time of the invention, to adjust the allocation of processing resources between the reference-image generation function (first processor) and the inspection function (third processor) in response to a change in inspection level in order to maintain line speed and deterministic inspection latency. In modern multicore processor architectures, assigning and reassigning CPU cores among concurrently executing tasks in response to workload or quality-of-service requirements is a well-understood, routine scheduling optimization that yields predictable results (e.g., increased throughput or reduced latency for the bottleneck stage). Thus, when the inspection level is increased (e.g., finer sensitivity/thresholding in Kobayashi ¶[0058-0064]) and the inspection stage’s computational demand rises, a skilled person would have been motivated to increase the ratio of cores assigned to the inspection task relative to reference generation; conversely, if inspection level is decreased, to shift cores back to reference generation to balance the pipeline an application of known resource management to the combined Kobayashi/Mutsuno system.
As to claim 12 [dependent from claim 11], However, the dependent claim 12 essentially claimed same subject matter as claimed in the dependent claim 3 for/and/with other claim limitations, and are therefore the dependent claim 12 would be rejected based on same rationale as applied to the dependent claim 3.
As to claim 13 [dependent from claim 12], However, the dependent claim 13 essentially claimed same subject matter as claimed in the dependent claim 4 for/and/with other claim limitations, and are therefore the dependent claim 13 would be rejected based on same rationale as applied to the dependent claim 4.
As to claim 14 [dependent from claim 11], However, the dependent claim 14 essentially claimed same subject matter as claimed in the dependent claim 5 for/and/with other claim limitations, and are therefore the dependent claim 14 would be rejected based on same rationale as applied to the dependent claim 5.
As to claim 16 [dependent from claim 11], However, the dependent claim 16 essentially claimed same subject matter as claimed in the dependent claim 7 for/and/with other claim limitations, and are therefore the dependent claim 16 would be rejected based on same rationale as applied to the dependent claim 7.
As to claim 17 [dependent from claim 11], However, the dependent claim 17 essentially claimed same subject matter as claimed in the dependent claim 8 for/and/with other claim limitations, and are therefore the dependent claim 17 would be rejected based on same rationale as applied to the dependent claim 8.
Response to Arguments
9. Applicant’s arguments with respect to claims 1, 3-5, 7-18 have been considered but are moot because the new prior reference(s) is/are being employed in this current rejection and the arguments do not apply to any of the references being used in the current rejection.
Conclusion
10. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARIS SABAH whose telephone number is (571)270-3917. The examiner can normally be reached on Monday/Friday from 9:00AM to 5:30PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Benny Tieu, can be reached on (571)272-7490. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The Examiner’s personal fax number is (571)270-4917.
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/HARIS SABAH/Examiner, Art Unit 2682
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