DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending on this application. Claims 1, 16, and 20 are in independent forms.
Priority
3. Foreign priority has been claimed to KR application # 10-2023-0098521 filed on 07/27/2023 and KR application #. 10-2023-0165902 filed on 11/24/2023.
Information Disclosure Statement
4. The information disclosure statements (IDS's) submitted on 06/07/2024 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. The drawings filed on 06/07/2024 are accepted by the examiner.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-3, 5-6, 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saarinen US Patent Application Publication No. 2022/0171885 (hereinafter Saarinen) in view of Porterfield et al. US Patent Application Publication No. 2021/0311799 (hereinafter Porterfield).
Regarding claim 1, Saarinen discloses a cryptography processor (Fig. 1 cryptographic co-processor 110) comprising:
“at least one interface circuit configured to communication with at least one of a host device and a semiconductor memory device” (see Saarinen par. 0032, the cryptographic co-processor 310, the computing device 300 also comprises a CPU 350 (host device), random access memory (RAM) 355, an electrically erasable programmable read only memory (EEPROM) 360, one or more input/output interfaces 365, a random number generator 370, and possible other cryptographic modules 375. The CPU 350 may comprise a RISC processor);
“at least one register configured to store at least a portion of intermediate data, of a common operation, and control data received from the host device” (see Saarinen par. 0026, The control registers 115 may be used to store one or more of: status (e.g. busy or awaiting instruction), a function to perform, sizes for source and/or destination data, memory locations for source and/or destination data, shift parameters, increment parameters for one or more of address and data arrays, and/or indicators to show whether a current function is complete. The external processing unit may be configured to read a value stored within the control registers 115 to determine whether an output of a function is available, may receive an interrupt from the cryptographic co-processor and/or may wait a predetermined number of clock cycles associated with a function. Different approaches may be used depending on implementation requirements);
“a plurality of common operation circuits, respectively configured to perform different operations” (see Saarinen par. 0022, the functions implemented by the arithmetic engine of the co-processor may allow code or lattice-based cryptographic operations to be rapidly performed, e.g. by off-loading many common low-level binary logic functions such as integer addition, subtraction and multiplication. The co-processor may be configured or pre-programmed with a set of available functions that may be selected by the processing unit via a function flag or variable in the control register of the co-processor. The co-processor may be able to more rapidly compute certain functions by avoiding the need to load and interpret distinct instructions as required by the processing unit);
Saarinen does not explicitly discloses a plurality of function circuits configured to control at least one of the plurality of common operation circuits to perform a workload allocated from the host device, the workload configured to execute at least one function of a cryptographic operation; wherein at least one of the plurality of common operation circuits is configured to be controlled by different function circuits, among the plurality of function circuits, to execute different functions of the cryptographic operation.
However, in analogues art, Porterfield discloses a plurality of function circuits configured to control at least one of the plurality of common operation circuits to perform a workload allocated from the host device, the workload configured to execute at least one function of a cryptographic operation (see Porterfield par. 0021, The host 102 and/or the controller 104 can be configured to assert a signal and/or a command to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive workloads and perform tasks and/or functions corresponding to the workloads. When the signal and/or command is asserted to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive a workload, the hardware devices 116-1 to 116-N can commence performance of tasks and/or functions associated with completing the workload); wherein at least one of the plurality of common operation circuits is configured to be controlled by different function circuits, among the plurality of function circuits, to execute different functions of the cryptographic operation (see Porterfield par. 0022, the processing unit 110 can monitor the hardware devices 116-1 to 116-N during performance of the tasks and/or functions associated with completing the workload(s) to determine characteristics corresponding to execution of the workload(s) by the hardware devices 116-1 to 116-N. The characteristics can include quantifiable attributes corresponding to execution of the workloads by the hardware devices 116-1 to 116-N. Some examples of characteristics corresponding to execution of the workloads by the hardware devices 116-1 to 116-N can include an amount of processing resources consumed by the hardware devices 116-1 to 116-N in executing of the workloads, an amount of time taken by the hardware devices 116-1 to 116-N in executing the workloads, thermal properties of the hardware devices 116-1 to 116-N (e.g., an amount of heat increase or decrease exhibited by the hardware devices 116-1 to 116-N) during execution of the workloads, etc.).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Porterfield into the system of Saarinen to allow for improved computing system performance because, in contrast to approaches that do not allow for communication between hardware devices, such as hardware accelerators, tasks and/or functions (e.g., workloads) can be allocated to optimize performance of the computing system in embodiments described herein (see Porterfield par. 0011).
Regarding claim 2, Saarinen in view of Porterfield discloses the cryptography processor of claim 1,
Saarinen further discloses wherein among the plurality of common operation circuits, a first common operation circuit comprises a plurality of stage circuits configured to perform different potions of a common operation on a shared input data based on different clock signals (see Saarinen par. 0057, the internal RAM 750 may comprise a dual-port type memory that allows two access operations per clock cycle of the APU 720. This may thus allow four memory addresses to be read in two clock cycles. In this case, there may be three source registers and one destination (i.e. A, B, C and D), as the data for these registers may be fetched from memory in two clock cycles).
Regarding claim 3, Saarinen in view of Porterfield discloses the cryptography processor of claim 2,
Saarinen further discloses wherein a number of stages performed by the plurality of stage circuits is defined based on an operating frequency (see Saarinen par. 0057, the clock cycles of the APU 720 may be at the same frequency as the control CPU 710 or may differ depending on implementation).
Regarding claim 5, Saarinen in view of Porterfield discloses the cryptography processor of claim 1,
Saarinen further discloses wherein the at least one register comprises: a control register configured to store the control data (see Saarinen par. 0026, The control registers 115 may be used to store one or more of: status (e.g. busy or awaiting instruction), a function to perform, sizes for source and/or destination data, memory locations for source and/or destination data, shift parameters, increment parameters for one or more of address and data arrays, and/or indicators to show whether a current function is complete); and a general-purpose register configured to store at least one of input data, intermediate data, and output data of each of the plurality of function circuits (see Saarinen par. 0027, One of the set of control registers 115 may be configured to store an indication of a function that is to be performed using the arithmetic engine 125. The function may be selected from a set of available functions, where the set of available functions may be pre-configured (e.g. pre-programmed into, or configured within, an ASIC or FPGA)), and wherein the control data comprises at least one of a function identifier identifying each of the plurality of function circuits, operation information associated with execution of a function, or input data of a function (see Saarinen Fig. 8, par. 0056, a function specifier or identifier—CRBL_R_OPER; a status readout—CRBL_R_STAT; dimensions for the multi-dimensional array—CRBL_R_SIZX and CRBL_R_SIZY (e.g. as shown in FIG. 5A); for each of the available sources and the destination, a start address—CRBL_z_ADDR—and increments for each of the dimensions—CRBL_z_INCX and CRBL_z_INCY; and for the source registers, a shift control parameter CRBL_z_CSRL (as described with reference to FIG. 6)—in this case z is one of A, B, C or D as shown).
Regarding claim 6, Saarinen in view of Porterfield discloses the cryptography processor of claim 1,
Saarinen further discloses wherein among the plurality of function circuits, a second function circuit is configured to control at least one third common operation circuit, among the plurality of common operation circuits, to perform at least a portion of a first function in a pipelined manner (see Saarinen par. 0068, certain operations may be performed in parallel and/or optimised to speed up operation of the co-processor. For example: at a first step in the pipeline addresses are generated for the sources and/or destination; at a second step in the pipeline, data words are fetched from the source addresses and optionally shifted (e.g. as per FIG. 6); at a third step a function may be performed, e.g. as D=f.sub.i(A, B, C) or (D, carry)=f.sub.i(A, B, C, carry)).
Regarding claim 16, Saarinen discloses a method of performing a cryptographic operation on a cryptographic processor (Fig. 1 cryptographic co-processor 110), the cryptographic processor comprising a plurality of function circuits configured to execute functions allocated from a host device and a plurality of common operation circuits configured to perform different common operation (see Saarinen par. 0022, the functions implemented by the arithmetic engine of the co-processor may allow code or lattice-based cryptographic operations to be rapidly performed, e.g. by off-loading many common low-level binary logic functions such as integer addition, subtraction and multiplication. The co-processor may be configured or pre-programmed with a set of available functions that may be selected by the processing unit via a function flag or variable in the control register of the co-processor. The co-processor may be able to more rapidly compute certain functions by avoiding the need to load and interpret distinct instructions as required by the processing unit), the method comprising:
“wherein the first function and the second function are functions serving to execute a function of the cryptographic operation” (see Saarinen par. 0074, an operation for a second function may be prepared as the co-processor is executing a first function. In certain cases, a co-processor method call may be defined (e.g. as a C API call) to avoid needing to write to the CRBL_R_OPER register directly. A similar co-processor method call may be defined for a waiting operation, where the method call will block until all running co-processor operations are finished, e.g. either by polling the CRBL_R_STAT status register or by waiting for an interrupt. Both co-processor method calls are calls that are executed by the main processing unit);
Saarinen does not explicitly discloses controlling, by a first function circuit among the plurality of function circuits, a first common operation circuit among the plurality of common operation circuits, to perform at least a portion of a first workload based on an execution command of the first workload from a host; controlling, by a second function circuit among the plurality of function circuits, the first common operation circuit to execute at least a portion of a second workload based on an execution command of the second workload from the host.
However, in analogues art, Porterfield discloses controlling, by a first function circuit among the plurality of function circuits, a first common operation circuit among the plurality of common operation circuits, to perform at least a portion of a first workload based on an execution command of the first workload from a host (see Porterfield par. 0021, The host 102 and/or the controller 104 can be configured to assert a signal and/or a command to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive workloads and perform tasks and/or functions corresponding to the workloads. When the signal and/or command is asserted to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive a workload, the hardware devices 116-1 to 116-N can commence performance of tasks and/or functions associated with completing the workload); controlling, by a second function circuit among the plurality of function circuits, the first common operation circuit to execute at least a portion of a second workload based on an execution command of the second workload from the host (see Porterfield par. 0022, the processing unit 110 can monitor the hardware devices 116-1 to 116-N during performance of the tasks and/or functions associated with completing the workload(s) to determine characteristics corresponding to execution of the workload(s) by the hardware devices 116-1 to 116-N. The characteristics can include quantifiable attributes corresponding to execution of the workloads by the hardware devices 116-1 to 116-N. Some examples of characteristics corresponding to execution of the workloads by the hardware devices 116-1 to 116-N can include an amount of processing resources consumed by the hardware devices 116-1 to 116-N in executing of the workloads, an amount of time taken by the hardware devices 116-1 to 116-N in executing the workloads, thermal properties of the hardware devices 116-1 to 116-N (e.g., an amount of heat increase or decrease exhibited by the hardware devices 116-1 to 116-N) during execution of the workloads, etc.).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Porterfield into the system of Saarinen to allow for improved computing system performance because, in contrast to approaches that do not allow for communication between hardware devices, such as hardware accelerators, tasks and/or functions (e.g., workloads) can be allocated to optimize performance of the computing system in embodiments described herein (see Porterfield par. 0011).
Regarding claim 17, Saarinen in view of Porterfield discloses the method of claim 16,
Saarinen further discloses controlling, by the first function circuit, the first common operation circuit in a pipelined manner such that different portions of a common operation on a shared input data are performed based on different clock signals (see Saarinen pars. 0036, the arithmetic unit 430 comprises three source registers 460 and one destination register 465. These are shown as internal registers of the arithmetic unit 430 but may alternatively comprise a pipeline cache of the cryptographic co-processor. Each function in the set of available functions is configured (e.g. as a programmed HDL function) to read data from the three source registers 460, perform a set of computations, and then output the result to the destination register 465).
Regarding claim 20, Saarinen discloses an electronic device comprising:
“a host device configured to perform at least a portion of a cryptographic operation or instruct a cryptographic operation device to execute a function of a cryptographic operation” (see Saarinen par. 0026, the control registers 115 are accessible to the external processing unit (e.g. CPU 220) (host device). The external processing unit is able to write data to the control registers 115 to control the operation of the cryptographic co-processor 110);
“a semiconductor memory device configured to store at least one of input data required to execute the function and output data of the function” (see Saarinen par. 0032, the cryptographic co-processor 310, the computing device 300 also comprises a CPU 350, random access memory (RAM) 355, an electrically erasable programmable read only memory (EEPROM) 360, one or more input/output interfaces 365, a random number generator 370, and possible other cryptographic modules 375. The CPU 350 may comprise a RISC processor. The EEPROM 360 may be implemented as any programmable memory and may be configured to store operating computer program code for the computing device 300, e.g. may comprise flash memory that stores firmware for an embedded device or system-on-chip. The RAM 355 may comprise a primary memory for the CPU 350. The one or more input/output interfaces 365 may comprise, amongst others, network and communication interfaces and peripheral interfaces); and
“a cryptographic processor configured to perform the function based on an instruction of the host device” (see Saarinen par. 0043, A set of iterations by the cryptographic co-processor may form part of an atomic operation from the point of view of the external processing unit. For example, they may be instructed with a single instruction of the external processing unit. The set of iterations may be used to perform a single cryptographic operation upon a plurality of sources, where those sources have an associated multi-dimensional array of data. The set of iterations may be synchronised to the clock cycle of the external processing unit, e.g. the complete set may be performed in one clock cycle of the external processing unit. This may allow a considerable speed increase as the same cryptographic operation as performed on the external processing unit may require a plurality of fetch, decode and execute cycles on both data and address memory, while the cryptographic co-processor may allow the result to be available in accessible memory following a much shorter time period); wherein the cryptographic processor comprises
“a plurality of common operation circuits configured to perform different common operations” (see Saarinen par. 0022, the functions implemented by the arithmetic engine of the co-processor may allow code or lattice-based cryptographic operations to be rapidly performed, e.g. by off-loading many common low-level binary logic functions such as integer addition, subtraction and multiplication. The co-processor may be configured or pre-programmed with a set of available functions that may be selected by the processing unit via a function flag or variable in the control register of the co-processor. The co-processor may be able to more rapidly compute certain functions by avoiding the need to load and interpret distinct instructions as required by the processing unit);
Saarinen does not explicitly discloses a plurality of function circuits respectively configured to control at least one of the plurality of common operation circuits; and wherein the at least one of the plurality of common operation circuits is configured to be controlled by different function circuits, among the plurality of function circuits, to execute different functions.
However, in analogues art, Porterfield discloses a plurality of function circuits respectively configured to control at least one of the plurality of common operation circuits (see Porterfield par. 0021, The host 102 and/or the controller 104 can be configured to assert a signal and/or a command to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive workloads and perform tasks and/or functions corresponding to the workloads. When the signal and/or command is asserted to the processing unit 110 and/or to the hardware device(s) 116-1 to 116-N to cause the hardware device(s) 116-1 to 116-N to receive a workload, the hardware devices 116-1 to 116-N can commence performance of tasks and/or functions associated with completing the workload); and wherein the at least one of the plurality of common operation circuits is configured to be controlled by different function circuits, among the plurality of function circuits, to execute different functions (see Porterfield par. 0022, the processing unit 110 can monitor the hardware devices 116-1 to 116-N during performance of the tasks and/or functions associated with completing the workload(s) to determine characteristics corresponding to execution of the workload(s) by the hardware devices 116-1 to 116-N. The characteristics can include quantifiable attributes corresponding to execution of the workloads by the hardware devices 116-1 to 116-N. Some examples of characteristics corresponding to execution of the workloads by the hardware devices 116-1 to 116-N can include an amount of processing resources consumed by the hardware devices 116-1 to 116-N in executing of the workloads, an amount of time taken by the hardware devices 116-1 to 116-N in executing the workloads, thermal properties of the hardware devices 116-1 to 116-N (e.g., an amount of heat increase or decrease exhibited by the hardware devices 116-1 to 116-N) during execution of the workloads, etc.).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Porterfield into the system of Saarinen to allow for improved computing system performance because, in contrast to approaches that do not allow for communication between hardware devices, such as hardware accelerators, tasks and/or functions (e.g., workloads) can be allocated to optimize performance of the computing system in embodiments described herein (see Porterfield par. 0011).
8. Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Saarinen US Patent Application Publication No. 2022/0171885 (hereinafter Saarinen) in view of Porterfield et al. US Patent Application Publication No. 2021/0311799 (hereinafter Porterfield) in further view of Jung et al. US Patent Application Publication No. 2019/0180803 (hereinafter Jung).
Regarding claims 4 and 18, Saarinen in view of Porterfield discloses the cryptography processor of claim 1, the method of claim 16,
Saarinen in view of Porterfield does not explicitly discloses wherein among the plurality of function circuits, a first function circuit is configured to control a second common operation circuit and the interface circuit such that at least a portion of a common operation of the second common operation circuit and at least a portion of input/output to the semiconductor memory device are performed using a shared clock signal.
However, in analogues art, Jung discloses wherein among the plurality of function circuits, a first function circuit is configured to control a second common operation circuit and the interface circuit such that at least a portion of a common operation of the second common operation circuit and at least a portion of input/output to the semiconductor memory device are performed using a shared clock signal (see Jung par. 0022, a memory system 100 includes a controller 10 (e.g., a control circuit), a first memory module 12-1 (e.g., a first memory card) including a first rank R1 including n first semiconductor memory devices M11 to M1n, a second memory module 12-2 (e.g., a second memory card) including a second rank R2 including n second semiconductor memory devices M21 to M2n, a clock signal line CKL shared by the controller 10, the first rank R1, and the second rank R2 and transmitting a clock signal CK, a first inverted chip selection signal line CSBL1 connected between the controller 10 and the first rank R1 and transmitting a first inverted chip selection signal CSB1, a second inverted chip selection signal line CSBL2 connected between the controller 10 and the second rank R2 and transmitting a second inverted chip selection signal CSB2, command and address lines CAL shared by the controller 10).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Jung into the system of Saarinen and Porterfield to include a clock signal line shared by the controller, the first rank, and the second rank, and configured to transmit a clock signal; command and address lines shared by the controller, the first rank, and the second rank, and configured to transmit a command and address (see Jung par. 0008).
9. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Saarinen US Patent Application Publication No. 2022/0171885 (hereinafter Saarinen) in view of Porterfield et al. US Patent Application Publication No. 2021/0311799 (hereinafter Porterfield) in further view of Quinnell US Patent Application Publication No. 2018/0081630 (hereinafter Quinnell).
Regarding claim 8, Saarinen in view of Porterfield discloses the cryptography processor of claim 1,
Saarinen in view of Porterfield does not explicitly discloses wherein the plurality of common operation circuits comprise a floating-point adder configured to perform at least one of addition or subtraction operations between operands of a plurality of pieces of real number data, and the floating-point adder comprises a plurality of stage circuits, the plurality of stage circuits respectively configured to perform an operation associated with exponents of the operands, an operation associated with mantissas of the operands, and a round operation.
However, in analogues art, Quinnell discloses wherein the plurality of common operation circuits comprise a floating-point adder configured to perform at least one of addition or subtraction operations between operands of a plurality of pieces of real number data (see Quinnell par. 0031, system includes a floating-point addition (FPA or FADD) unit or circuit 100. In such an embodiment, the FPA 100 is configured to perform addition and/or subtraction on two floating-point operands or values 202 and 204, and generate the result 248), and the floating-point adder comprises a plurality of stage circuits, the plurality of stage circuits respectively configured to perform an operation associated with exponents of the operands, an operation associated with mantissas of the operands, and a round operation (see Quinnell pars. 0088-0089, the adder 158 may include a 60-bit integer adder configured to perform rounding operations. In such an embodiment, the adder 158 may be configured to assume that no exponent shift occurs during the addition. Conversely, in the illustrated embodiment, the adder 160 may include a 60-bit integer adder configured to taking to account overflow or 1-bit left shift and perform the standard normalization operations, the selection logic 218 considers three possible events. If an overflow occurred the exponent portion may be incremented. If a subtraction caused the result to not include a whole number (e.g., 1.0+(−0.75)=0.25, etc.) the significand may be shifted and the exponent adjusted to form a proper normal number (e.g., 0.25 becomes 2.5×10.sup.−1, etc.)).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Quinnell into the system of Saarinen and Porterfield to include an apparatus may include a floating-point addition unit configured to generate a floating-point result by either adding or subtracting two floating-point operands together, wherein each floating-point operand includes a fraction portion and an exponent portion (see Quinnell par. 0006).
Regarding claim 9, Saarinen in view of Porterfield in further view of Quinnell discloses the cryptography processor of claim 8,
Quinnell further discloses wherein the plurality of stage circuits comprise a first stage circuit configured to match the exponents of the operands (see Quinnell par. 0070, The exponent portion 237 may be compared against the output 138 of the PENC 181 to determine if the exponent portion 237 may be decremented as much as the PENC 181 suggests. In the illustrated embodiment, this may be done by the clamp detector 282. In the illustrated embodiment, a shift amount selector 284 may select between the output of the maximum shift evaluator 281 and the PENC 181 based upon the output of the clamp detector 282), at least one second stage circuit configured to perform at least one of addition or subtraction operations on mantissas of the operands (see Quinnell par. 0038, the Far path 298 may be configured to perform all ranges of the addition operation or the subtraction operation when the exponent portions of the two operands 202 and 204 differ by more than an order of magnitude (e.g., 1,234−34, etc.). Conversely, the Close path 299 may be configured to perform the subtraction operation when the exponent portion (or absolute value) of the two operands 202 and 204 differ by less than an order of magnitude (e.g., 1,234+−1,236, etc.)), and a third stage circuit configured to perform a rounding operation on an output of the second stage circuit (see Quinnell pars. 0052-0053, the operands 212 and 214 may be input into an integer addition circuit 296. In the illustrated embodiment, the integer addition circuit 296 may include a pair of integer adders 158 and 160. In one embodiment, a first adder 158 may assume there is no overflow in the addition, and a second adder 160 may assume there will be an overflow in the addition, or in the case of subtraction, may assume there will be a 1-bit shift. In such an embodiment, the second adder 160 may make use of a carry-save arithmetic circuit 162 (e.g., a 3:2 compressor, etc.). In various embodiments, the adders 158 and 160 may also receive as input various rounding constants 116, in various embodiments, these two integer adders 158 and 160 may be employed in parallel to increase the speed and ease of computation. In various embodiments, an integer addition selector 264 may be employed to select between the two outputs of the adders 158 and 160).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to Incorporate the teachings of Quinnell into the system of Saarinen and Porterfield to include an apparatus may include a floating-point addition unit configured to generate a floating-point result by either adding or subtracting two floating-point operands together, wherein each floating-point operand includes a fraction portion and an exponent portion (see Quinnell par. 0006).
Allowable Subject Matter
10. Claims 7, 10-15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim et al. (US 2021/0295944 A1): discloses A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.
Hyland (US 2005/0213762 A1): discloses A cryptographic device may include a cryptographic module and a communications module removably coupled thereto. The cryptographic module may include a first housing and a first connector carried thereby, and the communications module may include a second housing and a second connector carried thereby and being removably mateable with the first connector of the cryptographic module.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL AMBAYE whose telephone number is (571)270-7635. The examiner can normally be reached M-F 9:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached at (571) 272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL AMBAYE/Examiner, Art Unit 2433
/JEFFREY C PWU/Supervisory Patent Examiner, Art Unit 2433