DETAILED ACTION
The instant action is in response to application 7 June 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for priority to 7 June 2024.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 12, 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
As to claim 9, applicant claims “a duty cycle associated with an on-time of the power transistor according to the control signal is greater than an inverse of a switching frequency of the switching regulator power stag”. This reads as though the on-time is greater than a period, which should not be the case in a buck converter, which appears to be governed by PWM given in the specification [Period = 1 /Frequency = 1/(Ton+Toff) = Ton + Toff; Duty = Ton/(Ton+Toff)]. The claim requires major revision. For the purposes of examination, there will be a relationship assumed between on time/duty cycle and slew rate.
As to claim 12, there is a similar problem to claim 9 above and will be interpreted in a similar manner.
As to claim 17, there is a similar problem to claim 9 above and will be interpreted in a similar manner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7, 8, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381).
As to claim 1, Lee explicitly discloses a power supply circuit comprising: a power supply rail (Fig. 2, Vin); a switching regulator power stage comprising a power transistor (Fig. 3A, HS FET) and an input coupled to the power supply rail; a transient voltage sensing circuit (Fig. 2 2061) having an input coupled to the power supply rail; an
Lee does not explicitly disclose an input voltage sensing circuit having an input coupled to the power supply rail or a first input coupled to an output of the transient voltage sensing circuit, and a second input coupled to an output of the input voltage sensing circuit. Though this is heavily implied by paragraph 49, he does not explicitly show separate input voltage sensing circuit, though the information could easily come from Vin or item 2061. Also, Lee is explicitly teaching a transient response both to the input slew rate and the input voltage, and it has been held as obvious been held to be within the general skill of a worker in the art to make plural parts unitary as a matter of engineering design choice. In re Larson, 144 USPQ 347 (CCPA 1965); In re Lockart 90 USPQ 214 (CCPA 1951).
As to claim 4, Lee makes obvious wherein the input voltage sensing circuit comprises: a voltage divider (Fig. 7, unlabelled divider) having an input coupled to the power supply rail; and a comparator having a first input coupled to a tap of the voltage divider, a second input coupled to a reference voltage source (Fig. 7 pre), and an output (2269) coupled to the second input of the control logic (though technically part of the transient sensing circuit, this is obvious in a similar manner as described above, with a single part forming multiple functions).
As to claim 7, Lee makes obvious wherein the control logic is configured to lower a slew rate of a control signal for the power transistor from a first slew rate to a second slew rate when a transient voltage level sensed by the transient voltage sensing circuit is greater than a first threshold voltage level (¶52 “when the transient slew rate of the input voltage Vin exceeds the transient slew rate upper limit, the control circuit 206 adjusts a frequency response gain from the stable state frequency response gain to the transient state frequency response gain; thus, by adjusting the mechanism of feedback control, the present invention can prevent the output current Iout from exceeding the current upper limit Iup, and/or prevent the transient response time Ttr of the output current Iout from exceeding a threshold transient time period.”) and an input voltage level sensed (¶53 “In one preferable embodiment, when the transient voltage Vin of the input voltage Vin does not exceed a stable voltage upper limit, or when the transient slew rate of the input voltage Vin does not exceed a stable slew rate upper limit, the control circuit 206 adjusts the frequency response gain from the transient state frequency response gain to the stable state frequency response gain.”) by the input voltage sensing circuit is greater than a second threshold voltage level (Note that the slew rate is decreasing, since during transient operation, switch GSW is open, forcing a slower response due to the resistor Rg).
As to claim 8, Lee teaches wherein the control logic has a third input coupled to an output of the switching regulator power stage and is further configured to: receive an indication of an output current of the switching regulator power stage via the third input; and raise the slew rate of the control signal for the power transistor from the second slew rate to the first slew rate when the output current of the switching regulator power stage is below a threshold current ( ¶49 “The control circuit 206 is coupled to the power stage circuit 202 and the current sense circuit 204, and is configured to operably generate the operation signal GD according to the input voltage Vin and the current sense signal CS”).
As to claim 10, Lee makes obvious A method of supplying power with a power supply circuit, comprising: sensing a transient voltage level at an input of a switching regulator power stage; sensing an input voltage level at the input of the switching regulator power stage; and when the transient voltage level is greater than a first threshold voltage level and the input voltage level is greater than a second threshold voltage level, lowering a slew rate of a control signal for a power transistor of the switching regulator power stage (this is an apparatus claim corresponding to claim 1 above and is obvious per MPEP 2112.02).
As to claim 11, Lee teaches further comprising: subsequent to the lowering, sensing an output current of the switching regulator power stage; and when the output current is less than a threshold current, increasing the slew rate of the control signal for the power transistor (¶52, 53).
Claims 2-3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381) in view of Kayuzuki (JP 2020180932)
As to claim 2, Lee does not explicitly teach wherein the transient voltage sensing circuit comprises: a filter having an input coupled to the power supply rail; a transistor having a gate coupled to an output of the filter and a source coupled to the power supply rail; and a comparator having an input coupled to a drain of the transistor and an output coupled to the first input of the control logic.
Kayuzuki teaches wherein the transient voltage sensing circuit comprises: a filter having (Fig. 1, R5, unlabelled capacitor) an input coupled to the power supply rail (Vin); a transistor (m10) having a gate coupled to an output of the filter and a source coupled to the power supply rail; and a comparator (items generating out_UVLO) having an input coupled to a drain of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use on-time slew rate adjsutment as disclosed in Kayuzuki to prevent the circuit from acting without sufficient voltage..
As to the limitation, an output coupled to the first input of the control logic, this would be taught by the combination, with the UVLO signal acting as an enable signal for the circuit..
As to claim 3, Lee in view of Kayuzuki makes obvious wherein the comparator comprises a Schmitt trigger. Though the feedback shown is open loop, only open loop, positive, or negative feedback is possible. Thea dvantage of open loop is generally faster slew rate, the advantage of negative feedback is more stability, and the advantage of positive feedback is hysteresis. Thea dvantages of each are known and therefore not patentable. It has been held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 5, Lee does not explicitly teach further comprising: a switching device coupled between the power supply rail and the input of the input voltage sensing circuit.
Kayuzuki teaches a switching device coupled between the power supply rail and the input of the input voltage sensing circuit (Fig. 4, M11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use on-time slew rate adjsutment as disclosed in Kayuzuki to prevent the circuit from acting without sufficient voltage..
Claims 9, 12, 17 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381) in view of Wu (US 20120038331).
As to claim 9, Lee teaches wherein the control logic is configured to lower a slew rate of a control signal for the power transistor from a first slew rate to a second slew rate when an input voltage level sensed by the input voltage sensing circuit is greater than a threshold voltage level (¶53.)
Lee does not disclose and a duty cycle associated with an on-time of the power transistor according to the control signal is greater than an inverse of a switching frequency of the switching regulator power stage.
Wu teaches and a duty cycle associated with an on-time of the power transistor according to the control signal is greater than an inverse of a switching frequency of the switching regulator power stage (Claim 15, 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use on-time slew rate adjsutment as disclosed in Wu to provide DCM operation.
As to claims 12 and 17, these appear to be method claims corresponding to claim 9 above and are obvious for similar reasons.
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381) in view of Faeber (US 20100007318)
As to claim 13,, Lee teaches raising the slew rate, subsequent to the lowering, when at least one of: the transient voltage level is no longer greater than the first threshold voltage level; the input voltage level is no longer greater than the second threshold voltage level;not explicitly teach (¶52, 53).
Lee does not teach the power supply circuit enters a pulse-skipping mode; or after a programmable period has elapsed.
Faeber teaches the power supply circuit enters a pulse-skipping mode; or after a programmable period has elapsed (Fig. 6, step 62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use DCM as disclosed in Faeber to increase operational range.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381) in view of You (US 20210143735)
As to claim 14, Lee does not teach wherein lowering the slew rate comprises: setting a latch circuit to cause a multiplexer to cease providing a first signal associated with a first slew rate control setting as the control signal and begin providing a second signal associated with a second slew rate control setting as the control signal.
You teaches wherein lowering the slew rate comprises: setting a latch circuit to cause a multiplexer to cease providing a first signal associated with a first slew rate control setting as the control signal and begin providing a second signal associated with a second slew rate control setting as the control signal (Fig. 2, ¶59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use multiplexed slew rates as disclosed in You to ease synchronization.
As to claim 15, Lee in view of You teaches further comprising: sensing an output current of the switching regulator power stage; and when the output current is less than a threshold current, resetting the latch circuit to cause the multiplexer to cease providing the second signal as the control signal and begin providing the first signal as the control signal (Lee, ¶52, 53).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170331381) in view of Faeber (US 20100007318) and Lin (US 9939830)
As to claim 16, Lee teaches wherein sensing the input voltage level comprises sensing the input voltage level using the input voltage sensing circuit.
He does not teach effectively disabling an input voltage sensing circuit when the power supply circuit is in a pulse-skipping mode.
Faeber teaches a pulse skipping mode (Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use DCM as disclosed in Faeber to increase operational range.
Lin teaches disabling an voltage sensing circuit when the power supply circuit is in a pulse-skipping mode (Col. 8, line 40 “It is worth explaining that, during the sleep mode, all the circuit units stop working except the input voltage detecting unit 11 may be activated by the detection enabling signal En_sel.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use an enable circuit on the input voltage detector as disclosed in Lin to save power.
Allowable Subject Matter
Claims 6 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 6, the prior art fails to disclose: “further comprising a driver circuit coupled between the output of the control logic and the gate of the power transistor, wherein the control logic comprises: a latch circuit having the first input and the second input; a first register configured to store a first slew rate control setting; a second register configured to store a second slew rate control setting; and a multiplexer having a control input coupled to an output of the latch circuit, a first input coupled to the first register, and a second input coupled to the second register, wherein the driver circuit has a signal input coupled to the output of the control logic, a control input coupled to an output of the multiplexer, and an output coupled to the gate of the power transistor.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER M NOVAK/ Primary Examiner, Art Unit 2839