Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-6, 9, 16, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1) in further view of Ding (US 20230131382 A1).
Regarding independent claim 1, Hwang teaches a semiconductor package (Fig. 1A, 1000; [0025], “Referring to the exemplary embodiments of FIGS. 1A and 1B, a semiconductor package 1000 may include…”), comprising: a buffer chip (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”); a plurality of semiconductor chips stacked on the buffer chip (Fig. 3, 100; [0035], “…the number of semiconductor chips 100 stacked on the base chip 200 is not limited thereto.”); and a molding layer on the buffer chip and the plurality of semiconductor chips (Fig. 1B, 400; [0025], “…a semiconductor package 1000 may include a semiconductor chip 100, a base chip 200, an adhesive film 300, and a sealing material 400.”), wherein the buffer chip comprises a device layer (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”), and wherein the device layer comprises a plurality of transistors that constitute logic circuits ([0034], “In an exemplary embodiment, the base chip 200 of the semiconductor package 1000 may be, for example, an interface chip including a plurality of logic devices and/or memory devices in the device layer 210.”). However, Hwang does not teach a capacitor layer on the device layer, wherein the capacitor layer comprises a capacitor, and wherein the plurality of semiconductor chips vertically overlap the capacitor.
However, in the same field of endeavor, Ding teaches a capacitor layer (Fig. 4, CAL; [0071], “The capacitor die ISC may include a capacitor layer CAL…”), wherein the capacitor layer comprises a capacitor (Fig. 4, CAP; [0079], “The capacitor layer CAL may include a capacitor CAP…”), and wherein the plurality of semiconductor chips vertically overlap the capacitor (Fig. 7, ICS, LGC, CAL; [0103], “The three-dimensional integrated circuit structure ICS may be used as a processor chip of a semiconductor package.”, (The logic die LGC is part of the chip structure ICS and vertically overlaps the capacitor layer CAL as shown in Fig. 7)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of Hwang with the capacitor layer of Ding so that “power transmission efficiency may be increased to improve electrical properties”, (Ding, [0089]).
Regarding dependent claim 2, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. Ding further teaches wherein the capacitor layer comprises: a first dielectric pattern (Fig. 4, 210; [0079], “The capacitor layer CAL may include a capacitor CAP and a first interlayer dielectric layer 210…”); and a second dielectric pattern on the first dielectric pattern (Fig. 4, 220; [0083], “The second interlayer dielectric layer 220 may be provided on the first interlayer dielectric layer 210, covering an upper portion of the capacitor CAP.”), and wherein the capacitor comprises: a lower electrode that penetrates the first dielectric pattern (Fig. 4, EL2; [0080], “The capacitor CAP may include…a second electrode EL2…”); an upper electrode on the lower electrode (Fig. 4, EL1; [0080], “The capacitor CAP may include…a first electrode EL1…”); and a capacitor dielectric layer between the lower electrode and the upper electrode (Fig. 4, DIL; [0080}, “The capacitor CAP may include a bottom electrode BEL, and may also include a first electrode EL1, a dielectric layer DIL…”).
Regarding dependent claim 4, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. Ding further teaches where a lowermost one of the plurality of semiconductor chips is in contact with the capacitor layer of the buffer chip (Fig. 7, ICS, LGC, CAL; [0103], “The three-dimensional integrated circuit structure ICS may be used as a processor chip of a semiconductor package.”, (The logic die LGC is part of the chip structure ICS and is in contact with the capacitor layer CAL as shown in Fig. 7)).
Regarding dependent claim 5, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. However, as previously combined, they do not teach wherein the capacitor is horizontally spaced apart from the molding layer.
However, Ding further teaches wherein the capacitor is horizontally spaced apart from the molding layer (Fig. 4, CAP, (The capacitor has a gap on the side, so that it is spaced apart from the edge, where the molding layer would contact if it were there)).
Therefore, it would have been obvious to one of ordinary skill to combine the semiconductor package as described by the combination of Hwang and Ding with the spaced apart capacitors of Ding so as to isolate it from the molding layer, electrically.
Regarding dependent claim 6, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. However, as previously combined, they do not teach wherein the capacitor layer further comprises a lower electrode line and an upper electrode line on the lower electrode line, wherein the capacitor is between the lower electrode line and the upper electrode line.
However, Ding further teaches wherein the capacitor layer further comprises a lower electrode line and an upper electrode line on the lower electrode line, wherein the capacitor is between the lower electrode line and the upper electrode line (Fig. 4, BEL, TEL; [0080], “The capacitor CAP may include a bottom electrode BEL… and a top electrode TEL that are sequentially stacked on the bottom electrode BEL.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the electrode lines of Ding so as to apply voltages through them to their respective capacitors.
Regarding dependent claim 9, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1, and further teaches wherein a width of each of the plurality of semiconductor chips is the same as each other (Fig. 3A, 100-(1,2,3,4): They are all the same width as each other.), and a width of the buffer chip is greater than the width of the plurality of semiconductor chips (Fig. 3A, 200: The buffer chip extends further than the other chips.).
Regarding independent claim 16, Hwang teaches a semiconductor package (Fig. 5B, 10000; [0087], “In the semiconductor device 10000 shown in the exemplary embodiments of FIGS. 5A and 5B, four semiconductor packages 1000e are mounted on (e.g., disposed on) the interposer 600.”), comprising: an interposer substrate (Fig. 5B, 600; [0087], “In the semiconductor device 10000 shown in the exemplary embodiments of FIGS. 5A and 5B, four semiconductor packages 1000e are mounted on (e.g., disposed on) the interposer 600.”); a logic chip on the interposer substrate ([0101], “…the semiconductor device 10000a may include… a logic chip 700a…”); and at least one chip stack on the interposer substrate and spaced apart from the logic chip (Fig. 7, 100cl(1,2,3); [0107], “In addition, the number of chiplets stacked on the active interposer 600a is also not limited to three. For example, one, two, or four or more chiplets may be stacked on the active interposer 600a.”), wherein the interposer substrate comprises: a lower wiring layer that comprises a plurality of lower pads and a plurality of lower wiring patterns (Fig. 5B, 610, 605; [0091], “A wiring layer 610 may be disposed on a lower surface of the substrate 601.”, [0090], “…the upper pad 605 may be disposed on the upper protection layer 603.”); and an upper wiring layer that comprises a plurality of upper pads and a plurality of upper wiring patterns ([0091], “The wiring layer 610 may have a single-layer or multi-layer wiring structure. In an exemplary embodiment in which the wiring layer 610 has a multi-layer wiring, structure, the wiring lines of different layers may be connected to each other through a vertical contact.”, (This means that the previous description used as evidence for the lower wiring patterns can be used for both the upper and lower, since it can be multi-layer)). However, Hwang does not teach and a first capacitor layer between the lower wiring layer and the upper wiring layer, wherein the first capacitor layer comprises at least one first capacitor, wherein the at least one first capacitor vertically overlaps at least one from among the logic chip and the at least one chip stack, and wherein the at least one first capacitor is electrically connected through the plurality of upper pads and the plurality of upper wiring patterns to at least one from among the logic chip and the at least one chip stack.
However, in the same field of endeavor, Ding teaches a first capacitor layer (Fig. 4, CAL; [0071], “The capacitor die ISC may include a capacitor layer CAL…”), wherein the first capacitor layer comprises at least one first capacitor (Fig. 4, CAP; [0079], “The capacitor layer CAL may include a capacitor CAP…”), wherein the at least one first capacitor vertically overlaps at least one from among the logic chip and the at least one chip stack (Fig. 7, ICS, LGC, CAL; [0103], “The three-dimensional integrated circuit structure ICS may be used as a processor chip of a semiconductor package.”, (The logic die LGC is part of the chip structure ICS and vertically overlaps the capacitor layer CAL as shown in Fig. 7)), and wherein the at least one first capacitor is electrically connected through the plurality of upper pads and the plurality of upper wiring patterns to at least one from among the logic chip and the at least one chip stack (Fig. 7, ICS, LGC, CAL; [0103], “The three-dimensional integrated circuit structure ICS may be used as a processor chip of a semiconductor package.”, (The logic die LGC is part of the chip structure ICS and is in contact with the capacitor layer CAL as shown in Fig. 7)).
Therefore, it would have been obvious to combine the semiconductor package of Hwang with the capacitor layer of Ding so that “power transmission efficiency may be increased to improve electrical properties”, (Ding, [0089]).
Regarding dependent claim 17, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 16, and further teaches wherein each of the at least one chip stack comprises: a buffer chip (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”); and a plurality of memory chips stacked on the buffer chip (Fig. 3, 100; [0035], “…the number of semiconductor chips 100 stacked on the base chip 200 is not limited thereto.”), wherein the buffer chip comprises a device layer (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”). However, as previously combined, they do not teach and a second capacitor layer on the device layer, wherein the second capacitor layer comprises a second capacitor.
However, as Ding has already taught a capacitor layer, it is possible to combine the semiconductor package as described by the combination of Hwang and Ding with another capacitor layer as described by Ding, so that “power transmission efficiency may be [further] increased to improve electrical properties”, (Ding, [0089]).
Regarding dependent claim 19, Hwang, as modified by Ding, teaches the semiconductor package of claim 16, and further teaches further comprising external connection terminals that are correspondingly connected to the plurality of lower pads of the lower wiring layer (Fig. 5B, 510; [0097], “The external connection terminal 510, such as a solder ball., etc., may be disposed under the package substrate 500.”), and Ding teaches wherein the external connection terminals are electrically connected to the at least one first capacitor (Fig. 3, ECT, CAL; [0071], “The capacitor die ISC may include a capacitor layer CAL…”, [0072], “The pads PAD may be correspondingly provided thereon with external connection members ECT.”).
Regarding dependent claim 20, Hwang, as modified by Ding, teaches the semiconductor package of claim 16, and further teaches wherein the at least one chip stack is a plurality of chip stacks that are on the interposer substrate (Fig. 7, 100cl(1,2,3); [0107], “In addition, the number of chiplets stacked on the active interposer 600a is also not limited to three. For example, one, two, or four or more chiplets may be stacked on the active interposer 600a.”).
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1) in further view of Ding (US 20230131382 A1) and Lee (US 20230141447 A1).
Regarding independent claim 11, Hwang teaches a semiconductor package (Fig. 1A, 1000; [0025], “Referring to the exemplary embodiments of FIGS. 1A and 1B, a semiconductor package 1000 may include…”), comprising: a buffer chip (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”), that comprises a device layer (Fig. 3A, 200; [0039], “In an exemplary embodiment, while the base chip 200 may include a plurality of logic devices and/or memory devices in the device layer 210 and may be referred to as a buffer chip…”), wherein the device layer comprises a plurality of transistors that constitute a logic circuit ([0034], “In an exemplary embodiment, the base chip 200 of the semiconductor package 1000 may be, for example, an interface chip including a plurality of logic devices and/or memory devices in the device layer 210.”). However, Hwang does not teach and a memory chip that comprises a wiring layer and a core layer on the wiring layer, wherein the core layer comprises a memory device electrically connected to the capacitor through the upper pad and the front pad, wherein the wiring layer comprises a front pad connected to the upper pad; and a capacitor layer on the device layer; wherein the capacitor layer comprises a capacitor, and wherein the capacitor vertically overlaps with the memory chip.
However, in the same field of endeavor, Lee teaches a memory chip that comprises a wiring layer and a core layer on the wiring layer (Fig. 1B, 220, 215; [0057], “The second wiring structure 225 may be formed in a multi-layer structure…”, “Individual devices 215 constituting an integrated circuit may be disposed on the front surface of the second substrate 210.” (This is the core layer)), wherein the wiring layer comprises a front pad connected to the upper pad (Fig. 1B, 232; [0059], “At least a portion of one of the second pads 232 may be joined to one of the first pads 152 of the first semiconductor chip 100, to form the bonding pad structure…”), wherein the core layer comprises a memory device electrically connected to the capacitor through the upper pad and the front pad (Fig. 1B, 215, [0057], “The individual devices 215 may include…a memory device…”), and Ding teaches a capacitor layer on the device layer (Fig. 4, CAL; [0071], “The capacitor die ISC may include a capacitor layer CAL…”); wherein the capacitor layer comprises a capacitor (Fig. 4, CAP; [0079], “The capacitor layer CAL may include a capacitor CAP…”), and wherein the capacitor vertically overlaps with the memory chip (Fig. 7, ICS, LGC, CAL; [0103], “The three-dimensional integrated circuit structure ICS may be used as a processor chip of a semiconductor package.”, (The logic die LGC is part of the chip structure ICS and vertically overlaps the capacitor layer CAL as shown in Fig. 7)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of Hwang with the memory chip of Lee so as to “integrate more components…into a package structure” (Lee, [0003]), and the capacitor layer of Ding so that “power transmission efficiency may be increased to improve electrical properties”, (Ding, [0089]).
Regarding dependent claim 12, Hwang, as previously modified by Ding and Lee, teaches the semiconductor package of claim 11. Lee further teaches the semiconductor package of claim 11, wherein the memory device comprises a dynamic random access memory (DRAM) ([0090], “…including a volatile memory device such as a DRAM…”).
Regarding dependent claim 13, Hwang, as previously modified by Ding and Lee, teaches the semiconductor package of claim 11. Lee further teaches the semiconductor package of claim 11, wherein the capacitor layer and the wiring layer are in contact with each other, and the upper pad and the front pad are in contact with each other (Fig. 1B, 232; [0059], “At least a portion of one of the second pads 232 may be joined to one of the first pads 152 of the first semiconductor chip 100, to form the bonding pad structure…” (Although no capacitor layer is mentioned here, the pads for this layer and another layer are in contact, as shown by the reference. This other layer can be replaced by the capacitor layer of Ding)).
Regarding dependent claim 14, Hwang, as previously modified by Ding and Lee, teaches the semiconductor package of claim 11. Ding further teaches wherein the capacitor comprises: a plurality of lower electrodes (Fig. 4, EL2; [0080], “The capacitor CAP may include…a second electrode EL2…”); an upper electrode that is on the plurality of lower electrodes (Fig. 4, EL1; [0080], “The capacitor CAP may include…a first electrode EL1…”); and a capacitor dielectric layer between the upper electrode and the plurality of lower electrodes (Fig. 4, DIL; [0080}, “The capacitor CAP may include a bottom electrode BEL, and may also include a first electrode EL1, a dielectric layer DIL…”).
Claim(s) 3 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1) in further view of Ding (US 20230131382 A1), Lee (US 20230141447 A1), and Kim (US 20230076238 A1).
Regarding dependent claim 3, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 2. However, as previously combined, they do not teach wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS).
However, in the same field of endeavor, Kim teaches wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS) ([0060], “…and the separation dielectric pattern 27b may include tetraethylorthosilicate (TEOS).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the TEOS dielectric pattern of Kim so as to make the dielectric pattern out of a material with a high “dielectric constant and mechanical strength” (Kim, [0060]).
Regarding dependent claim 15, Hwang, as previously combined with Ding and Lee, teaches the semiconductor package of claim 11. Ding further teaches wherein the capacitor layer comprises: a first dielectric pattern through which the capacitor penetrates (Fig. 4, 210; [0079], “The capacitor layer CAL may include a capacitor CAP and a first interlayer dielectric layer 210…”); and a second dielectric pattern on the first dielectric pattern (Fig. 4, 220; [0083], “The second interlayer dielectric layer 220 may be provided on the first interlayer dielectric layer 210, covering an upper portion of the capacitor CAP.”). However, as previously combined, they do not teach wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS).
However, in the same field of endeavor, Kim teaches wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS) ([0060], “…and the separation dielectric pattern 27b may include tetraethylorthosilicate (TEOS).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the TEOS dielectric pattern of Kim so as to make the dielectric pattern out of a material with a high “dielectric constant and mechanical strength” (Kim, [0060]).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1) in further view of Ding (US 20230131382 A1), and Lee (US 20230141447 A1).
Regarding dependent claim 7, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. However, as previously combined, they do not teach wherein each of the plurality of semiconductor chips comprises: a circuit layer comprising a front pad; and a core layer comprising a semiconductor device on the circuit layer.
However, in the same field of endeavor, Lee teaches wherein each of the plurality of semiconductor chips comprises: a circuit layer comprising a front pad (Fig. 1A, 120, 152; [0048], “The first semiconductor chip 100 may include…a first circuit layer 120… and first pads 152.”); and a core layer comprising a semiconductor device on the circuit layer (Fig. 1B, 215; [0057], “Individual devices 215 constituting an integrated circuit may be disposed on the front surface of the second substrate 210.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the layers of Lee so as “to integrate more components…into a package structure” (Lee, [0003]).
Regarding dependent claim 8, Hwang, as previously modified by Ding and Lee, teaches the semiconductor package of claim 7. Lee further teaches wherein the capacitor layer comprises an upper pad connected to the capacitor, wherein the upper pad is connected to the front pad of a lowermost one of the plurality of semiconductor chips (Fig. 1B, 232; [0059], “At least a portion of one of the second pads 232 may be joined to one of the first pads 152 of the first semiconductor chip 100, to form the bonding pad structure…”).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1) in further view of Ding (US 20230131382 A1), and Kouassi (US 20250079066 A1).
Regarding dependent claim 10, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 1. However, as previously combined, they do not teach wherein a thickness of the capacitor layer is in a range of 1,500 μm to 2,500 μm.
However, in the same field of endeavor, Kouassi teaches wherein a thickness of the capacitor layer is in a range of 1,500 μm to 2,500 μm ([0081], “…the thickness of multi-level capacitor layer may be 100 μm or more, 150 μm or more, 200 μm or more, 300 μm or more, 400 μm or more, or any other suitable thickness.” (This includes the range of 1500-2500 as given in the application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the thickness of the capacitor layer of Kouassi so as to include multiple capacitors.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20210375823 A1), in further view of Ding (US 20230131382 A1), and Kim (US 20230076238 A1).
Regarding dependent claim 18, Hwang, as previously modified by Ding, teaches the semiconductor package of claim 17. Ding further teaches wherein the capacitor layer comprises: a first dielectric pattern through which the capacitor penetrates (Fig. 4, 210; [0079], “The capacitor layer CAL may include a capacitor CAP and a first interlayer dielectric layer 210…”); and a second dielectric pattern that covers the second capacitor (Fig. 4, 220; [0083], “The second interlayer dielectric layer 220 may be provided on the first interlayer dielectric layer 210, covering an upper portion of the capacitor CAP.”). However, as previously combined, they do not teach wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS).
However, in the same field of endeavor, Kim teaches wherein the first dielectric pattern comprises tetraethylorthosilicate (TEOS) ([0060], “…and the separation dielectric pattern 27b may include tetraethylorthosilicate (TEOS).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Hwang and Ding with the TEOS dielectric pattern of Kim so as to make the dielectric pattern out of a material with a high “dielectric constant and mechanical strength” (Kim, [0060]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20240213140 A1, which pertains to a semiconductor package featuring a device layer and capacitor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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