Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, which discloses the control logic configured to receive control inputs. However, it is not clear from specification or the drawings, which “control inputs “the control logic” is received. Note, Fig. 7 disclose a control logic (790) for generating/outputting via terminals (791A, 791B, 791C and 791D) and there is no receiving as claimed. Clarification is needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roy et al (20170149397), hereafter called ROY.
Regarding claims 1 and 16, ROY (Figs. 13 and 14) discloses a circuit comprising: first gain trim circuitry (114b and 110a) having a first gain trim input (VINP), the first gain trim circuitry including a first differential input transistor pair and a second differential input transistor pair; second gain trim circuitry (114a and 128b) having a second gain trim input (VINN), the second gain trim circuitry including a third differential input transistor pair and a fourth differential input transistor pair; and control logic (control circuit (130) shows in other Figures) having a first gain trim output (VOUTM) and a second gain trim output (VOUTP), the first gain trim output coupled to the first gain trim input, and the second gain trim output coupled to the second gain trim input. Note, Fig. 14 shows block (200), para. [0028], discloses a plurality (N numbers) of differential transistor pairs, which can be first to fourth transistor pairs claimed.
Regarding claim 11, ROY (Fig. 14) discloses a circuit comprising: first differential input transistor pairs; second differential input transistor pairs, see block (200); resistive networks (128a, 128b); first selection circuitry (110a) having a first control input (for controlling the switch), the first selection circuitry coupled between the resistive networks (128a, 128b) and the first differential input transistor pairs; second selection circuitry (110b) having a second control input (for controlling the switch), the second selection circuitry coupled between the resistive networks (128a, 128b) and the second differential input transistor pairs; and control logic (control circuit (130) shows in other Figures) having a first gain trim output and a second gain trim output, the first gain trim output coupled to the first control input, and the second gain trim output coupled to the second control input.
Regarding claim 17, wherein the control inputs include a gain setting selected by a user (HOST/140), see Figs. (1 and 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6, 12, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROY.
Regarding claims 2 and 4, ROY does not disclose W/L ratios of the transistors as claimed. However, W/L ratios are based on the size of the transistors selected, wherein different transistor sizes are readily available for implementation and thus would have been obvious to a person having ordinary skills in the art.
Regarding claims 3 and 5, Fig. 14, wherein each transistor pair comprises a current source and desired current level is based on current selected, which is readily available.
Regarding claim 6, Fig. 14, wherein the differential amplifier circuitry includes resistive networks (114a, 114b), the first gain trim circuitry includes first selection circuitry (128a) coupled between the resistive networks and the first and second differential input transistor pairs, the second gain trim circuitry includes second selection circuitry coupled between the resistive networks and the third and fourth differential input transistor pairs, the first selection circuitry having a first control input, the second selection circuitry having a second control input, the first gain trim output coupled to the first control input, and the second gain trim output coupled to the second control input.
Regarding claims 12 and 13, ROY does not disclose W/L ratios of the transistors and current level as claimed. However, W/L ratios are based on the size of the transistors selected, wherein different transistor sizes are readily available for implementation and thus would have been obvious to a person having ordinary skills in the art and desired current level is based on current selected, which is readily available.
Regarding claim 18, ROY does not disclose the control inputs include a temperature. However, the effect of temperature to the control inputs is inherently seen depend on the utilization of the circuit which is well known in the art.
Allowable Subject Matter
Claims 7-10, 14, 15, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 7-10, prior art(s) does not disclose the differential amplifier circuitry includes a first gain stage, cross-coupled switches before and after the first gain stage, and a feed-forward gain stage, the first gain stage including the first gain trim circuitry and the second gain trim circuitry, and the feed-forward gain stage including third gain trim circuitry and fourth gain trim circuitry, the third gain trim circuitry having a third gain trim input, the fourth gain trim circuitry having a fourth gain trim input, the control logic having a third gain trim output and a fourth gain trim output, the third gain trim output coupled to the third gain trim input, and the fourth gain trim output coupled to the fourth gain trim input.
Regarding claims 14 and 15, prior art(s) does not disclose a feed-forward gain stage including: third differential input transistor pairs; fourth differential input transistor pairs; second resistive networks; third selection circuitry having a third control input coupled to the first gain trim output, the third selection circuitry coupled between the second resistive networks and the third differential input transistor pairs; and fourth selection circuitry having a fourth control input coupled to the second gain trim output, the fourth selection circuitry coupled between the second resistive networks and the fourth differential input transistor pairs.
Regarding claims 19 and 20, prior art(s) does not disclose a device coupled to the differential amplifier circuitry; and a controller coupled to the differential amplifier circuitry and the device, the device configured to: receive a control signal from the controller; perform operations responsive to the control signal; and provide a sense signal, the differential amplifier circuitry configured to: receive the sense signal; and provide an amplified sense signal responsive to the setting of the first gain trim circuitry and the second gain trim circuitry, and the controller configured to: receive the amplified sense signal; and provide the control signal responsive to the amplified sense signal.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Agarwal et al. (20210167731), which is considered to be the closest prior art to the claimed invention. Agarwal et al. (Fig. 3) discloses a circuit including a trimming circuit (320). However, it lacks resistive networks and switching networks.
Zhang et al. (20230036578) and Mengad (20180097490) disclose trim circuit. However, they both lack the differential pairs as claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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