DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/07/2024 and 06/14/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species III (Figs. 21 to 25), including Claims 1-20 in the reply filed on 06/22/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Muramatsu (US20200234887).
With respect to claim 1, Muramatsu discloses a capacitor comprising (see FIG. 1, element 10): a body (see FIG. 1, element 12) that includes a first internal electrode (see FIG. 2, element 18a) and a second internal electrode (see FIG. 2, element 18b) stacked with a dielectric layer (see FIG. 2, element 16) interposed therebetween; a first external electrode (see FIG. 1, element 14) that is disposed to cover an upper surface of the body (see FIG. 1, element 12b) and an outer side surface of the body (see FIG. 1, elements 12c, 12d, 12e and 12f) and is connected to the first internal electrode through the upper surface of the body (see FIG. 2, element 18a) and the outer side surface of the body (see FIG. 2, element 12d); and a second external electrode (see FIG. 2, element 15) that is disposed to cover the upper surface of the body (see FIG. 1, element 12b) and the outer side surface of the body (see FIG. 1, elements 12c, 12d, 12e and 12f) and is connected to the second internal electrode (see FIG. 2, element 18b) through the upper surface of the body (see FIG. 2, element 12b) and the outer side surface of the body (see FIG. 2, element 12c).
With respect to claim 10, Muramatsu discloses each of the first external electrode (see FIG. 1, element 14) and the second external electrode (see FIG. 1, element 15) is disposed adjacent to a corner where an end portion of the body in a length direction (see FIG. 1, element L, noting Y direction) and an end portion of the body in a width direction meet (see FIG. 1, element W, noting Z direction).
With respect to claim 11, Muramatsu discloses each of the first external electrode and the second external electrode is provided in two (see FIG. 1, elements 14a, 14b, 15a and 15b).
With respect to claim 12, Muramatsu discloses the first external electrode (see FIG. 2, element 14b) is connected to a portion of the first internal electrode exposed to the outer side surface of the body (see FIG. 2, element 18a), and the second external electrode (see FIG. 2, element 15a) is connected to a portion of the second internal electrode exposed to the outer side surface of the body (see FIG. 2, element 18b).
With respect to claim 13, Muramatsu discloses a first electrode separation layer disposed between the first external electrode and the second internal electrode (see FIG. 2, elements 14b and 26a, paragraph 41, noting L gaps); and a second electrode separation layer disposed between the second external electrode and the first internal electrode (see FIG. 2, elements 15a and 26a, paragraph 41, noting L gaps).
With respect to claim 14, Muramatsu discloses a capacitor (see FIG. 1, element 10) comprising: a substrate (see paragraph 55); a body (see FIG. 1, element 12) that includes a first internal electrode (see FIG. 2, element 18a) and a second internal electrode (see FIG. 2, element 18b) stacked with a dielectric layer (see FIG. 2, element 16) interposed therebetween and is disposed on the substrate (see paragraph 55); a first external electrode (see FIG. 1, element 14) that is disposed to cover an upper surface of the body (see FIG. 1, element 12b) and an outer side surface of the body (see FIG. 1, elements 12c, 12d, 12e and 12f) and is connected to the first internal electrode; and a second external electrode (see FIG. 1, element 15) that is disposed to cover the upper surface of the body (see FIG. 1, element 12b) and the outer side surface of the body (see FIG. 1, elements 12c, 12d, 12e and 12f) and is connected to the second internal electrode (see FIG. 2, element 18b).
With respect to claim 15, Muramatsu discloses the first external electrode (see FIG. 2, element 14b) is connected to a portion of the first internal electrode exposed to the outer side surface of the body (see FIG. 2, element 18a), and the second external electrode (see FIG. 2, element 15a) is connected to a portion of the second internal electrode exposed to the outer side surface of the body (see FIG. 2, element 18b).
With respect to claim 16, Muramatsu discloses each of the first external electrode (see FIG. 1, element 14) and the second external electrode (see FIG. 1, element 15) is disposed adjacent to a corner where an end portion of the body in a length direction (see FIG. 1, element L, noting Y direction) and an end portion of the body in a width direction meet (see FIG. 1, element W, noting Z direction).
With respect to claim 17, Muramatsu discloses each of the first external electrode and the second external electrode is provided in two (see FIG. 1, elements 14a, 14b, 15a and 15b).
With respect to claim 18, Muramatsu discloses a capacitor (see FIG. 1, element 10) comprising: a substrate (see paragraph 55); a body (see FIG. 1, element 12) that includes a first internal electrode (see FIG. 2, element 18a) and a second internal electrode (see FIG. 2, element 18b) stacked with a dielectric layer (see FIG. 2, element 16) interposed therebetween and is disposed on an upper surface of the substrate (see FIG. 2, element 12d); two first external electrodes (see FIG. 1, elements 14a and 14b) that are disposed to be spaced apart from each other on an upper surface of the body and are connected to the first internal electrode (see FIG. 2 and FIG. 3, elements 14b, 18a); and two second external electrodes (see FIG. 1, elements 15a and 15b) that are disposed to be spaced apart from each other on the upper surface of the body and are connected to the second internal electrode (see FIG. 2 and FIG. 3, elements 15a, 15b and 18b).
With respect to claim 20, Muramatsu discloses a portion of the first external electrodes covers an outer side surface of the body (see FIG. 1, elements 14a and 14b) and is connected to a portion of the first internal electrode exposed to the outer side surface of the body (see FIG. 2, elements 14b and 18a), and a portion of the second external electrodes covers the outer side surface of the body (see FIG. 1, elements 15a and 15b) and is connected to a portion of the second internal electrode exposed to the outer side surface of the body (see FIG. 2, elements 15a and 18b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu in view of Lee et al. (US20220230811).
With respect to claim 2, Muramatsu teaches the capacitor of claim 1 (see FIG. 1, element 10).
Muramatsu does not expressly teach that a first connection via disposed inside the body to connect the first internal electrode and the first external electrode; and a second connection via disposed inside the body to connect the second internal electrode and the second external electrode.
Lee, on the other hand, teaches a first connection via (see FIG. 5, element 231) disposed inside the body (see FIG. 5, element 210) to connect the first internal electrode (see FIG. 7, element 221) and the first external electrode (see FIG. 5, element 241); and a second connection via (see FIG. 5, element 232) disposed inside the body (see FIG. 5, element 210) to connect the second internal electrode (see FIG. 7, element 222) and the second external electrode (see FIG. 5, element 242).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Muramatsu and Lee to form the claimed invention in order to increase the capacitance of the multilayer ceramic capacitor and to improve equivalent series inductance (ESL) (see Lee paragraph 61).
With respect to claim 3, the combined teachings of Muramatsu and Lee teach that a first via separation layer (see FIG. 8B, element 221a) disposed between the first connection via (see FIG. 8B, element 231) and the second internal electrode (see FIG. 8B, element 222).
With respect to claim 4, the combined teachings of Muramatsu and Lee teach that a second via separation layer (see FIG. 8A, element 222a) disposed between the second connection via (see FIG. 8A, element 232) and the first internal electrode (see FIG. 8A, element 221).
With respect to claim 5, the combined teachings of Muramatsu and Lee teach that the first external electrode (see FIG. 5, element 241) contacts the first connection via (see FIG. 1, element 231), and the second external electrode (see FIG. 5, element 242) contacts the second connection via (see FIG. 5, element 232).
With respect to claim 19, the combined teachings of Muramatsu and Lee teach that a first connection via (see FIG. 5, element 231) disposed inside the body (see FIG. 5, element 210) and connected to the first internal electrode (see FIG. 7, element 221); and a second connection via (see FIG. 5, element 232) disposed inside the body (see FIG. 5, element 210) and connected to the second internal electrode (see FIG. 7, element 222).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu and Lee 811’, as applied to claim 2 above, and further in view of Lee et al. (US 20190074137).
With respect to claim 6, Muramatsu and Lee 811’ teaches the capacitor of claim 1 (see FIG. 1, element 10).
Muramatsu and Lee 811’ do not teach that a first connection layer connecting the first external electrode and the first connection via; and a second connection layer connecting the second external electrode and the second connection via.
Lee 137’, on the other hand, teaches a first connection layer connecting the first external electrode and the first connection via (see FIG. 4, elements 151 and 132b, paragraphs 98 and 101); and a second connection layer connecting the second external electrode and the second connection via (see FIG. 4, elements 152 and 142b, paragraphs 98 and 101).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Muramatsu, Lee 811’ and Lee 137’ to form the claimed invention in order to improve electrical connectivity (see Lee 137’ paragraph 110).
With respect to claim 7, the combined teachings of Muramatsu, Lee 811’ and Lee 137’ teach that the first connection layer and the second connection layer are disposed on an uppermost dielectric layer among dielectric layers including the uppermost dielectric layer (see Lee 137’ FIG. 4, elements 132b and 142b, paragraphs 101).
With respect to claim 8, the combined teachings of Muramatsu and Lee 811’ teach that the number of first connection vias including the first connection via (see FIG. 5, elements 231 and 234) is greater than or equal to the number of first external electrodes including the first external electrode (see Lee 811’ FIG. 5, elements 241 and 244).
With respect to claim 9, the combined teachings of Muramatsu and Lee 811’ teach that the number of second connection vias including the second connection via (see FIG. 5, elements 232 and 233) is greater than or equal to the number of second external electrodes including the second external electrode (see Lee 811’ FIG. 5, elements 242 and 243).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESTHER N LIAN whose telephone number is (571)272-5726. The examiner can normally be reached Monday-Friday 8:00 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ESTHER N LIAN/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
Prosecution Insights