DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Response to Election/Restriction on 07/10/2016. The applicant elects Species 1 (Figure 12) without traverse.
Drawings
Figures 3 and 4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities: Claim 4, line 4 recites “the third logic level”, which should be -- a third logic level -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim 21 is objected to because of the following informalities: Claim 21, line 9 recites “a first logic signal and a second logic signal”, which should be -- the first logic signal and the second logic signal -- because these terms were previously presented in the claim; Claim 21, line 11 recites “a phase control signal”, which should be -- the phase control signal -- because this term was previously presented in the claim.
Appropriate correction is required.
Claim 22 is objected to because of the following informalities: Claim 22, line 6 recites “a first logic signal and a second logic signal”, which should be -- the first logic signal and the second logic signal -- because these terms were previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Colbeck et al. (US 2020/0195155), hereinafter Colbeck.
Regarding claim 1, Colbeck discloses (see figures 1-8) a controller (figure 2B, part controller generated by 204 and 130) for a power converter (figure 2B, part 200b), the power converter (figure 2B, part 200b) including a first transistor (figure 2B, part 238) and a second transistor (figure 2B, part 237) coupled to the first transistor (figure 2B, part 238), the controller comprising: a logic controller (figure 2B, part logic controller generated by 113 and 115) including a signal generator (figure 2B, part signal generator inside of logic controller generated by 113 and 115) and configured to generate a first logic signal (figure 2B, part first logic signal generated by Sw) and a second logic signal (figure 2B, part second logic signal generated by Sclk) (paragraph [0054]; FIG. 2B illustrates an LLC converter 200b); and a driver (figure 2B, part driver generated by 111, 250, 234 and 130) configured to generate a first control signal (figure 2B, part GH) and a second control signal (figure 2B, part GL) based at least in part on the first logic signal (figure 2B, part first logic signal generated by Sw) and the second logic signal (figure 2B, part second logic signal generated by Sclk), output the first control signal (figure 2B, part GH) to the first transistor (figure 2B, part 238), and output the second control signal (figure 2B, part GL) to the second transistor (figure 2B, part 237); wherein the signal generator (figure 2B, part signal generator inside of logic controller generated by 113 and 115) is configured to generate a phase control signal (figure 6C, part phase control signal generated by 650); wherein the signal generator (figure 2B, part signal generator inside of logic controller generated by 113 and 115) is further configured to: change the phase control signal (figure 6C, part phase control signal generated by 650) from a first logic level (figure 6C, part phase control signal generated by 650; at first low logic level) to a second logic level (figure 6C, part phase control signal generated by 650; at second high logic level) to start a first switching phase (figures 6B and 6C, part first switching phase of GH/GL from start at 682 to 687) of a first period of a discontinuous conduction mode (figures 6B and 6C, part phase control signal generated by 650; at second high logic level from start at 682 to 687); change the phase control signal (figure 6C, part phase control signal generated by 650; at 687) from the second logic level (figure 6C, part phase control signal generated by 650; at second high logic level) to the first logic level (figure 6C, part phase control signal generated by 650; at first low logic level) to end the first switching phase of the first period of the discontinuous conduction mode (figure 6C, part to end of the first switching phase at 687) and to start a first idle phase (figures 6B and 6C, part first idle phase from 687 to 692) of the first period of the discontinuous conduction mode(figures 6B and 6C, part phase control signal generated by 650; at first low logic level from 687 to 692); and change the phase control signal from the first logic level (figures 6B and 6C, part phase control signal generated by 650; first low logic level at 692) to the second logic level (figures 6B and 6C, part phase control signal generated by 650; at second high logic level at 692) to end the first idle phase of the first period of the discontinuous conduction mode (figures 6B and 6C, part end of first idle phase at 692) and to start a second switching phase of a second period of the discontinuous conduction mode (figures 6B and 6C, part start second switching phase at 692); wherein: the first period of the discontinuous conduction mode (figures 6B and 6C, part the first period of the discontinuous conduction mode from 682 to 692) includes the first switching phase (figures 6B and 6C, part first switching phase of GH/GL from start at 682 to 687) and the first idle phase (figures 6B and 6C, part first idle phase from 687 to 692); and the first switching phase of the first period of the discontinuous conduction mode (figures 6B and 6C, part first switching phase of GH/GL from start at 682 to 687) includes N cycles of a critical conduction mode, N being a positive integer (figures 6B and 6C, part N=2 cycles of a critical conduction mode from 682 to 687) (paragraph [0031]; the discontinuous mode of operation may be characterized by a burst mode. During burst mode, a switch mode power converter, and an LLC converter, may switch at a fixed frequency for short durations as necessary to maintain an output voltage level. These short durations of switching may be referred to as “burst-on” periods or burst-on intervals. Between the short durations, the switching may be inhibited and controller circuits may be temporarily disabled to reduce power consumption. These durations of inhibiting switching may be referred to as “burst-off” periods or burst-off intervals. Control of switching in this manner, where there are transitions or abrupt transitions in frequency in a switch mode power stage, is often referred to as “burst” and/or “burst mode”).
Regarding claim 2, Colbeck discloses everything claimed as applied above (see claim 1). Further, Colbeck discloses (see figures 1-8) the first logic level is a logic low level (figure 6C, part phase control signal generated by 650; at first low logic level); and the second logic level is a logic high level (figure 6C, part phase control signal generated by 650; at second high logic level).
Regarding claim 3, Colbeck discloses everything claimed as applied above (see claim 1). Further, Colbeck discloses (see figures 1-8) during the first idle phase of the first period of the discontinuous conduction mode (figures 6B and 6C, part first idle phase from 687 to 692), the first control signal (figure 2B, part GH) remains at a third logic level (figures 2B and 6B/C, part GH; at third low logic level) so that the first transistor remains being turned off (figure 2B, part 238; turned off); and the second control signal (figure 2B, part GL) remains at the third logic level (figures 2B and 6B/C, part GL; at third low logic level) so that the second transistor remains being turned off (figure 2B, part 237; turned off).
Regarding claim 21, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Colbeck et al. (US 2020/0195155), hereinafter Colbeck, in view of Fahlenkamp et al. (US 10,892,687), hereinafter Fahlenkamp.
Regarding claim 4, Colbeck discloses everything claimed as applied above (see claim 1). Further, Colbeck discloses (see figures 1-8) the first switching phase of the first period of the discontinuous conduction mode (figures 6B and 6C, part first switching phase of GH/GL from start at 682 to 687) includes: N time durations when the first control signal remains at a fourth logic level (figure 2B, part N=2 time durations of GH at high level) and the second control signal remains at the third logic level (figure 2B, part N=2 time durations of GL at low level); and N time durations when the second control signal remains at the fourth logic level (figure 2B, part N=2 time durations of GL at high level) and the first control signal remains at the third logic level (figure 2B, part N=2 time durations of GH at low level); wherein the third logic level (figure 2B, part low level) and the fourth logic level are different (figure 2B, part high level). However, Colbeck does not expressly disclose N+1 time durations.
Fahlenkamp teaches (see figures 1-8) the first switching phase of the first period of the discontinuous conduction mode (figures 1A and 4, part first switching phase of HSGD/LSGD from start at 40) includes: N time durations when the first control signal remains at a fourth logic level (figures 1A and 4, part HSGD at high level at 41) and the second control signal remains at the third logic level (figures 1A and 4, part LSGD at low level at 41); and N+1 time durations when the second control signal remains at the fourth logic level (figures 1A and 4, part LSGD at high level at 40 and 42) and the first control signal remains at the third logic level (figures 1A and 4, part HSGD at low level at 40 and 42); wherein the third logic level (figure 2B, part low level) and the fourth logic level are different (figure 2B, part high level) (columns 6 and 7; lines 33-67 and 1-16).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the first switching phase of Colbeck with the first switching phase features as taught by Fahlenkamp and obtain the first switching phase of the first period of the discontinuous conduction mode includes: N time durations when the first control signal remains at a fourth logic level and the second control signal remains at the third logic level; and N+1 time durations when the second control signal remains at the fourth logic level and the first control signal remains at the third logic level; wherein the third logic level and the fourth logic level are different, because it reduces switching losses through ZVS in order to obtain more efficient control (column 1; lines 60-63).
Regarding claim 5, Colbeck and Fahlenkamp teach everything claimed as applied above (see claim 4). Further, Colbeck discloses (see figures 1-8) the third logic level is a logic low level (figure 2B, part low level); and the fourth logic level is a logic high level (figure 2B, part high level).
Regarding claim 6, Colbeck and Fahlenkamp teach everything claimed as applied above (see claim 4). Further, Colbeck discloses (see figures 1-8) one cycle of the N cycles of the critical conduction mode (figures 6B and 6C, part one cycle of N=2 cycles of a critical conduction mode from 682 to 687) includes the last time duration of the N time durations (figure 2B, part last time duration of N=2 time durations). However, Colbeck does not expressly disclose the last time duration of the N+1 time durations, and the first time duration of the N+1 time durations.
Fahlenkamp teaches (see figures 1-8) one cycle of the N cycles of the critical conduction mode includes the last time duration of the N time durations (figures 1A and 4, part last time duration of the N time durations at 41), the last time duration of the N+1 time durations (figures 1A and 4, part last time duration of the N +1 time durations at 42), and the first time duration of the N+1 time durations (figures 1A and 4, part first time duration of the N+1 time durations at 40) (columns 6 and 7; lines 33-67 and 1-16).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the first switching phase of Colbeck with the first switching phase features as taught by Fahlenkamp and obtain one cycle of the N cycles of the critical conduction mode includes the last time duration of the N time durations, the last time duration of the N+1 time durations, and the first time duration of the N+1 time durations, because it reduces switching losses through ZVS in order to obtain more efficient control (column 1; lines 60-63).
Regarding claim 7, Colbeck and Fahlenkamp teach everything claimed as applied above (see claim 6). Further, Colbeck discloses (see figures 1-8) another cycle of the N cycles of the critical conduction mode (figures 6B and 6C, part another cycle of N=2 cycles of a critical conduction mode from 682 to 687) includes one time duration of the N time durations (figure 2B, part one time duration of the N=2 time durations); wherein: the one time duration of the N time durations is not the last time duration of the N time durations (figure 2B, part one time duration of the N=2 time durations). However, Colbeck does not expressly disclose one time duration of the N+1 time; and the one time duration of the N+1 time durations is not the first time duration of the N+1 time durations and is not the last time duration of the N+1 time durations.
Fahlenkamp teaches (see figures 1-8) one time duration of the N time durations (figures 1A and 4, part one time duration of the N time durations at 41) and one time duration of the N+1 time durations (figures 1A and 4, part one time duration of the N+1 time durations at 40 and 42); wherein: the one time duration of the N time durations is not the last time duration of the N time durations (figures 1A and 4, part one time duration of the N time durations at 41); and the one time duration of the N+1 time durations is not the first time duration of the N+1 time durations (figures 1A and 4, part one time duration of the N+1 time durations at 42) and is not the last time duration of the N+1 time durations (figures 1A and 4, part one time duration of the N+1 time durations at 40).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the first switching phase of Colbeck with the first switching phase features as taught by Fahlenkamp and obtain another cycle of the N cycles of the critical conduction mode includes one time duration of the N time durations and one time duration of the N+1 time durations; wherein: the one time duration of the N time durations is not the last time duration of the N time durations; and the one time duration of the N+1 time durations is not the first time duration of the N+1 time durations and is not the last time duration of the N+1 time durations, because it reduces switching losses through ZVS in order to obtain more efficient control (column 1; lines 60-63).
Regarding claim 8, Colbeck and Fahlenkamp teach everything claimed as applied above (see claim 4). Further, Colbeck discloses (see figures 1-8) each cycle of the N cycles of the critical conduction mode (figures 6B and 6C, part each cycle of N=2 cycles of a critical conduction mode from 682 to 687) does not share any of the N time durations with any other cycle of the N cycles of the critical conduction mode (figures 6B and 6C, part each cycle of N=2 cycles of a critical conduction mode from 682 to 687). However, Colbeck does not expressly disclose each cycle of the N cycles of the critical conduction mode does not share any of the N+1 time durations with any other cycle of the N cycles of critical conduction mode.
Fahlenkamp teaches (see figures 1-8) each cycle of the N cycles of the critical conduction mode (figures 1A and 4, part each cycle of the N cycles of the critical conduction mode between 40-42) does not share any of the N+1 time durations (figures 1A and 4, part N+1 time durations at 40 and 42) with any other cycle of the N cycles of critical conduction mode (figures 1A and 4, part each cycle of the N cycles of the critical conduction mode between 40-42).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the first switching phase of Colbeck with the first switching phase features as taught by Fahlenkamp and obtain each cycle of the N cycles of the critical conduction mode does not share any of the N time durations with any other cycle of the N cycles of the critical conduction mode; and each cycle of the N cycles of the critical conduction mode does not share any of the N+1 time durations with any other cycle of the N cycles of critical conduction mode, because it reduces switching losses through ZVS in order to obtain more efficient control (column 1; lines 60-63).
Allowable Subject Matter
Claims 9-14 are allowed. Claim 22 is objected, but would be allowable upon overcoming the objection set forth in this action.
The following is an examiner’s statement of reasons for allowance: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 9, the logic controller includes a determination unit configured to: receive a first input signal indicating a first envelope period of a first period of a discontinuous conduction mode; receive a second input signal indicating a first number of cycles of a critical conduction mode for a first switching phase of the first period of the discontinuous conduction mode; determine an average switching frequency for the first period of the discontinuous conduction mode based at least in part on the first input signal and the second input signal; compare the determined average switching frequency for the first period of the discontinuous conduction mode with a predetermined reference frequency value to generate a comparison result; and determine a second number of cycles of the critical conduction mode for a second switching phase of a second period of the discontinuous conduction mode based on at least information associated with the comparison result; wherein: the first switching phase of the first period of the discontinuous conduction mode includes the first number of cycles of the critical conduction mode; and the second switching phase of the second period of the discontinuous conduction mode includes the second number of cycles of the critical conduction mode;
Regarding claims 10-14, these claim are dependent claims of claim 9, therefore these claims are objected by the same reason presented above;
Regarding claim 22, receiving a first input signal indicating a first envelope period of a first period of a discontinuous conduction mode; receiving a second input signal indicating a first number of cycles of a critical conduction mode for a first switching phase of the first period of the discontinuous conduction mode; determining an average switching frequency for the first period of the discontinuous conduction mode based at least in part on the first input signal and the second input signal; comparing the determined average switching frequency for the first period of the discontinuous conduction mode with a predetermined reference frequency value to generate a comparison result; and determining a second number of cycles of the critical conduction mode for a second switching phase of a second period of the discontinuous conduction mode based on at least information associated with the comparison result; wherein: the first switching phase of the first period of the discontinuous conduction mode includes the first number of cycles of the critical conduction mode; and the second switching phase of the second period of the discontinuous conduction mode includes the second number of cycles of the critical conduction mode;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights