Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/7/2024 and 1/30/2025 are in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statements have been considered except as otherwise indicated.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Fig. 4A: character "135T".
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Devices with Villus-Shaped Cells and Split Plate Electrodes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fantini et al. (US11587606B2).
Regarding Claim 1:
Fantini discloses a semiconductor memory device (Fig. 6) comprising:
a plurality of cell blocks (elements 605), each comprising a folding structure (Figs. 5A, paragraphs 66 and 74) in which a plurality of electrode structures (element 480) and a plurality of insulating structures (element 418) are alternately provided, wherein the plurality of electrode structures and the plurality of insulating structures extend in a vertical direction (Figs. 3/5C elements 325 and 306, paragraphs 50-54) and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view (Fig. 5A, paragraph 66), the plurality of electrode structures (element 335) comprise a vertical electrode (element 325) and a switching material layer (elements 310/465), and the plurality of cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction (see annotated fig. attached below); and
a gate stack structure (Fig. 3) comprising a plurality of gate electrodes (elements 315/445) and a plurality of interlayer insulating layers (element 305) that are alternately stacked in the vertical direction along sidewalls of the plurality of electrode structures (paragraphs 52-59),
wherein each of the plurality of gate electrodes (Fig. 5A elements 445) comprises a pad part and a plurality of plate electrodes spaced apart from each other in each of a plurality of layers (see annotated fig. attached below, paragraphs 47 and 66), and
wherein at least one plate electrode (Fig. 5C element 445) among the plurality of plate electrodes is connected to the switching material layer (element 465) of the plurality of electrode structures in each of two of the plurality of cell blocks in the first horizontal direction (elements 500-c) and at least two of the plurality of cell blocks in the second horizontal direction (elements 500-a1 and
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500-a2, paragraph 64).
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Regarding Claim 7:
Fantini discloses a semiconductor memory device according to claim 1, wherein the villus shapes (Fig. 5A element 418) of the folding structure (elements 500) face the second horizontal direction (see annotated fig. attached above).
Regarding Claim 10:
Fantini discloses a semiconductor memory device according to claim 1, wherein the plurality of cell blocks (Fig. 6 elements 605) comprises a first cell block (element C1, see annotated fig. attached above) and a second cell block (element C1) adjacent to each other in the first horizontal direction, and wherein the folding structure (Fig. 5A elements 418) of the first cell block and the folding structure of the second cell block are symmetrically provided with respect to a straight line extending in the second horizontal direction (paragraphs 74-76).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Fantini et al. (US11587606B2) in view of Ikegami et al. (US20240071477A1).
Regarding Claim 2:
Fantini discloses a semiconductor memory device according to claim 1, but does not explicitly disclose wherein each of the plurality of plate electrodes comprises a plurality of sawtooth parts extending from each of the shaft parts into the folded structure.
Ikegami, however, discloses an analogous semiconductor storage device (Figs. 5-6), comprising a gate stack structure (Fig. 7 element 11) with a plurality of gate electrodes (elements SGD/WL), wherein each of the plurality of plate electrodes (elements SGD/11e/11o) comprises: at least two shaft parts (elements 10-0a, 10-0c, 11-0a, 11-0b) extending from a pad part (elements 10-0d, 10-1d, 10-3d, 11-8, 11-9); and a plurality of sawtooth parts extending from each of the at least two shaft parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7), and wherein each of the plurality of sawtooth parts extends into the villus shapes of a folding structure (element SLT2, paragraphs 84 and 88-89) comprising a plurality of electrode structures (elements MP).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Fantini further in view of Ikegami to explicitly include a plurality of sawtooth parts extending from each of the at least two shaft parts – extending from the pad part – wherein each of the sawtooth parts extends into the villus shapes because both are directed to analogous memory devices. Doing so improves the electrical performance and efficiency in memory systems (Ikegami, paragraphs 37 and 224).
Regarding Claim 3:
The combination of Fantini and Ikegami disclose a semiconductor memory device according to claim 2, but Fantini does not explicitly disclose the direction in which the pad part, shaft parts, or sawtooth parts extend.
Ikegami, however, discloses an analogous semiconductor storage device (Figs. 5-6), wherein the pad part (elements 10-0d, 10-1d, 10-3d, 11-8, 11-9) extends in the second horizontal direction (Y-direction), the at least two shaft parts (elements 10-0a, 10-0c, 11-0a, 11-0b) extend in the first horizontal direction (X-direction), and the plurality of sawtooth parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7) extend in the second horizontal direction (Y-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Fantini further in view of Ikegami to explicitly include the direction in which the pad part, two shaft parts, and the plurality of sawtooth parts extend because both are directed to analogous memory devices. Doing so improves the electrical performance and efficiency in memory systems (Ikegami, paragraphs 37 and 224).
Regarding Claim 4:
The combination of Fantini and Ikegami disclose a semiconductor memory device according to claim 2, wherein Fantini further discloses two plate electrodes (Figs. 5 element 445) among the plurality of plate electrodes are connected to the switching material layer (element 465) of the plurality of electrode structures (elements 480/465).
Regarding Claim 5:
The combination of Fantini and Ikegami disclose a semiconductor memory device according to claim 4, wherein Fantini further discloses each of the two plate electrodes (Figs. 5 elements 445) is connected to the switching material layer (element 465) of the plurality of electrode structures (elements 480/465) in two cell blocks among the plurality of cell blocks that are provided in the first horizontal direction (elements 500-c) and two cell blocks among the plurality of cell blocks that are provided in the second horizontal direction (Fig. 5A elements 500-a).
Regarding Claim 6:
The combination of Fantini and Ikegami disclose a semiconductor memory device according to claim 4, wherein Fantini further discloses the two plate electrodes (Figs. 5 elements 445) connected to the switching material layer (elements 465) have comb shapes that are staggered from each other (paragraphs 43, 47-50 and 74).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fantini et al. (US11587606B2) in view of Murooka et al. (US20130187118A1).
Regarding Claim 8:
Fantini discloses a semiconductor memory device according to claim 1, wherein the at least one plate electrode (element 445; see annotated fig. attached above) is connected to the switching material layer (Fig. 5C element 465) but does not explicitly disclose where said plate electrode is connected to at least two cell blocks provided in the second horizontal direction.
Murooka, however, discloses an analogous memory cell array (Fig. 4), comprising a plurality of cell blocks (elements R1) wherein at least one plate electrode (element WLcomb) is connected to electrode structures (Fig. 2 element BL) and at least two of cell blocks provided in the second horizontal direction [First direction], among the plurality of cell blocks (paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Fantini further in view of Murooka to explicitly include where at least one plate electrode is connected to the switching material layer and at least two of the cell blocks provided in the second horizontal direction because both are directed to analogous memory devices. Doing so allows for an improvement in integration efforts and mitigating parasitic influences (Murooka, paragraphs 2, 91-92, and 157-158).
Regarding Claim 9:
Fantini discloses a semiconductor memory device according to claim 1, wherein the plurality of cell blocks (Fig. 6 elements 605) comprises a first cell block (Fig. 5A element 500-a2) and a second cell block (element 500-a1) adjacent each other in the second horizontal direction (see annotated fig. attached above), but Fantini does not explicitly disclose where the folding structure of each cell block are symmetrical with respect to a straight line extending in the first horizontal direction.
Murooka, however, discloses an analogous memory cell array (Fig. 4), comprising a plurality of cell blocks (elements R1) wherein a folding structure (paragraph 31; see annotated figs. attached below) of the first cell block (element C1) and the folding structure of the second cell block (element C2) are symmetrically provided with respect to a straight line extending in the first horizontal direction [Third direction].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Fantini further in view of Murooka to explicitly include where the folding structures of the first and second cell blocks are symmetrically provided with respect to a line extending in the first horizontal direction because both are directed to analogous memory devices. Doing so allows for an improvement in integration efforts and mitigating parasitic influences (Murooka, paragraphs 2, 91-92, and 157-158).
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Claims 11-12, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ikegami et al. (US20240071477A1) in view of Fantini et al. (US11587606B2).
Regarding Claim 11:
Ikegami discloses a semiconductor memory device (Figs. 5-7) comprising:
a substrate (element 13) comprising a plurality of pad regions (1st/2nd connect; Fig. 5) and a plurality of cell regions (memory cell), wherein the plurality of pad regions and the plurality of cell regions are alternately provided in a first horizontal direction (X-direction; paragraph 100);
at least two cell blocks (Figs 26-28 elements BLK0-1) sequentially provided in a second horizontal direction [Y-direction] intersecting the first horizontal direction [X-direction] in each of the plurality of cell regions (elements MP region); and
a gate stack structure (Fig. 7 element 11) comprising a plurality of gate electrodes (elements WL/SGD),
wherein each of the plurality of gate electrodes (Figs. 5-6) comprises, in each of a plurality of layers, a plurality of plate electrodes (elements SDG/11e/11o) spaced apart from each other, each of the plurality of plate electrodes comprises a pad part (elements 10-0d, 10-1d, 10-3d, 11-8, 11-9) provided in one pad region [1st/2nd connect] of the plurality of pad regions, at least two shaft parts (elements 10-0a, 10-0c, 11-0a, 11-0b) extending from the pad part to at least one cell region [memory cell] adjacent to the one pad region, and a plurality of sawtooth parts extending from each of the at least two shaft parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7),
wherein each of the at least two cell blocks (element BLK) provided in each of the plurality of cell regions (memory cell; paragraph 100) comprises, on the substrate (Fig. 7 element 13), a folding structure (paragraphs 84 and 88-89) in which a plurality of electrode structures (elements MP) extending in the vertical direction [Z-direction] and a plurality of insulating structures (element SLT2) extending in the vertical direction are alternately provided and connected with each other (Fig. 11, paragraph 93) so as to have at least two U-shaped structures forming villus shapes in a plan view (Figs. 5-6), wherein the plurality of electrode structures (elements MP0-6) extend in the vertical direction [Z-direction] into the gate stack structure (element 11) and comprise a vertical electrode (Figs. 11-12 element MP), and
wherein each of the plurality of sawtooth parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7) extends into the villus shapes [MP/SLT2 shape] and is connected to the electrode structures (Fig. 12, paragraph 72).
However, Ikegami does not explicitly disclose where the gate stack structure additionally comprises of a plurality of interlayer insulating layers that are alternately stacked with the gate electrodes. Nor does Ikegami disclose a switching material layer included in the plurality of electrode structures.
Fantini discloses an analogous memory array (Fig. 6), comprising a gate stack structure including a plurality of gate electrodes (Fig. 3-5 elements 315/445) and a plurality of interlayer insulating layers (element 305) that are alternately stacked in the vertical direction (paragraphs 52-59). Further comprising a plurality of electrode structures (elements 335/480) extending in the vertical direction into the gate stack structure and comprising a vertical electrode (element 325/480) and a switching material layer (element 465), and wherein each of the plurality of plate electrodes (Fig. 5A elements 445) extends into villus shapes (paragraph 66) and is connected to the switching material layer (paragraph 64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami further in view of Fantini to explicitly include a gate stack structure comprising a plurality of ate electrodes and a plurality of interlayer insulating layers alternately stacked in a vertical direction. Furthermore, where the plurality of electrode structures include a switching material in addition to the vertical electrodes because both are directed to analogous architectures for memory devices. Doing so allows memory devices with higher integration densities while maintaining reliable complex structures (Fantini, paragraphs 11-13).
Regarding Claim 12:
The combination of Ikegami and Fantini discloses a semiconductor memory device according to claim 11, wherein Ikegami further discloses the pad part (Figs. 5-6 elements 10-0d, 10-1d, 10-3d, 11-8, 11-9) extends in the second horizontal direction [Y-direction], the at least two shaft parts (elements 10-0a, 10-0c, 11-0a, 11-0b) extend in the first horizontal direction from the pad part [X-direction], and the plurality of sawtooth parts extend in the second horizontal direction from the at least two shaft parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7).
Regarding Claim 17:
The combination of Ikegami and Fantini discloses a semiconductor memory device according to claim 11, but Ikegami does not explicitly disclose where two of the plurality of plate electrodes are connected to a switching material layer of the plurality of electrode structures.
Fantini discloses an analogous memory array (Fig. 6), wherein two of the plurality of plate electrodes (Figs. 5 element 445) have comb shapes that are staggered from each other (paragraphs 11 and 74) and are connected to a switching material layer (element 465) of the plurality of electrode structures (elements 335/480).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami further in view of Fantini to explicitly include wherein two of the plurality of plate electrodes have comb shapes – that are staggered from each other – and are connected to a switching material layer because both are directed to analogous architectures for memory devices. Doing so allows memory devices with higher integration densities while maintaining reliable complex structures (Fantini, paragraphs 11-13).
Claims 13-16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ikegami et al. (US20240071477A1) and Fantini et al. (US11587606B2) as applied to claim 11 above, and further in view of Murooka et al. (US20130187118A1).
Regarding Claim 13:
The combination of Ikegami and Fantini discloses a semiconductor memory device according to claim 11, but neither Ikegami nor Fantini explicitly disclose where the at least two shaft parts – in at least one of the plurality of plate electrodes – are provided in two adjacent cell regions in the first horizontal direction.
Murooka, however, discloses an analogous memory cell array (Fig. 4), comprising a plurality of cell blocks [R1/C1/C2/C3] wherein in at least one of the plurality of plate electrodes (element R2/WLcomb), the at least two shaft parts (elements WLcomb_a/b) are provided in each of two cell regions (elements R1) adjacent to each other in the first horizontal direction [First direction] among the plurality of cell regions (paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami and Fantini further in view of Murooka to explicitly include where in at least one of the plurality of plate electrodes, the at least two shaft parts are provided in two cell regions adjacent to each other in the first horizontal direction because both are directed to analogous memory devices. Doing so allows for an improvement in integration efforts and mitigating parasitic influences (Murooka, paragraphs 2, 91-92, and 157-158).
Regarding Claim 14:
The combination of Ikegami, Fantini, and Murooka discloses a semiconductor memory device according to claim 13, wherein Ikegami further discloses the at least two shaft parts (Figs. 5-6 elements 10-0a, 10-0c, 11-0a, 11-0b) of the at least one of the plurality of plate electrodes (elements SDG, 11e, 11e) extend to opposite sides in the second horizontal direction [Y-direction] of a corresponding cell block (element BLK).
Regarding Claim 15:
The combination of Ikegami, Fantini, and Murooka discloses a semiconductor memory device according to claim 13, wherein, Ikegami further discloses in at least another of the plurality of plate electrodes (Figs. 5-6 elements SDG, 11e, 11e), the at least two shaft parts (10-0a, 10-0c, 11-0a, 11-0b) extend across only one cell region of the plurality of cell regions [memory cell].
Regarding Claim 16:
The combination of Ikegami and Fantini discloses a semiconductor memory device according to claim 11, but neither explicitly disclose where at least two shaft parts extend across two cell regions.
Murooka, however, discloses an analogous memory cell array (Fig. 4), wherein, in at least two of the plurality of plate electrodes (elements R2/WLcomb), the at least two shaft parts (elements WLcomb_a/b) extend across two cell regions of the plurality of cell regions (elements R1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami and Fantini further in view of Murooka to explicitly include where in at least two of the plurality of plate electrodes, the at least two shafts extend across two cell regions because both are directed to analogous memory devices. Doing so allows for an improvement in integration efforts and mitigating parasitic influences (Murooka, paragraphs 2, 91-92, and 157-158).
Regarding Claim 18:
The combination of Ikegami and Fantini discloses a semiconductor memory device according to claim 11, but neither explicitly disclose where one of the at least two shaft parts corresponding to one of the two cell blocks extends in an opposite direction from one of the at least two shaft parts corresponding to the other one of the two cell blocks.
Murooka, however, discloses an analogous memory cell array (Fig. 4), wherein, in one plate electrode of the plurality of plate electrodes (element WLcomb), one of the at least two shaft parts (element WLcomb_a/b) corresponding to one of the at least two cell blocks [C1/C2/C3] provided in one of the plurality of cell regions (elements R1) and another one of the at least two shaft parts (element WLcomb_a/b) corresponding to another one of the at least two cell blocks [C1/C2/C3] extend to opposite sides in the second horizontal direction of a corresponding cell block [First direction].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami and Fantini further in view of Murooka to explicitly include where in one plate electrode, one of the at least two shaft parts corresponding to one of the at least two cell blocks and another one of the at least two shaft parts corresponding to another one of the at least two cell blocks extend to opposite sides in the second horizontal direction of a corresponding cell block because both are directed to analogous memory devices. Doing so allows for an improvement in integration efforts and mitigating parasitic influences (Murooka, paragraphs 2, 91-92, and 157-158).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikegami et al. in view of Murooka et al. and Fantini et al.
Regarding Claim 19:
Ikegami discloses a semiconductor memory device (Figs. 5-7) comprising:
a substrate (element 13) comprising a plurality of pad regions (1st/2nd connect; Fig. 5) and a plurality of cell regions (memory cell), wherein the plurality of pad regions and the plurality of cell regions are alternately provided in a first horizontal direction (X-direction; paragraph 100),
a plurality of cell blocks comprising at least two cell blocks (Figs 26-28 elements BLK0-1) sequentially provided in a second horizontal direction [Y-direction] intersecting the first horizontal direction [X-direction] in each of the plurality of cell regions (elements MP region), and
a gate stack structure (Fig. 7 element 11) comprising a plurality of gate electrodes (elements WL/SGD),
wherein each of the plurality of gate electrodes (Figs. 5-6) comprises, in each of a plurality of layers, a plurality of plate electrodes spaced apart from each other (elements 11e/11o), each of the plurality of plate electrodes comprising a pad part provided (elements 10-0d, 10-1d, 10-3d, 11-8, 11-9) in one pad region of the plurality of pad regions [1st/2nd connect], and extending in the second horizontal direction [Y-direction], at least two shaft parts (elements 10-0a, 10-0c, 11-0a, 11-0b) extending from the pad part in the first horizontal direction [X-direction] to at least one cell region [memory cell] adjacent to the one pad region of the plurality of cell regions (paragraph 100), and a plurality of sawtooth parts extending from each of the at least two shaft parts in the second horizontal direction (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7),
wherein each of the at least two cell blocks (element BLK) provided in each of the plurality of cell regions (memory cell; paragraph 100) comprises, on the substrate (Fig. 7 element 13), a folding structure (paragraphs 84 and 88-89) in which a plurality of electrode structures (elements MP) extending in the vertical direction [Z-direction] and a plurality of insulating structures (elements SLT2) extending in the vertical direction are alternately provided and connected with each other (Fig. 11, paragraph 93) so as to have at least two U-shaped structures forming villus shapes in a plan view (Figs. 5-6), wherein the plurality of electrode structures (elements MP0-6) extend in the vertical direction [Z-direction] into the plurality of gate electrodes (element 11) and comprise a vertical electrode (Figs. 11-12 element MP),
wherein the villus shapes face the second horizontal direction [MP/SLT2 shape; Y-direction], and each of the plurality of sawtooth parts (elements 10-1a/b, 10-2a/b, 10-3a/b, 11-1-7) extends into the villus shapes of the folding structure and is connected to the electrode structures (Fig. 12, paragraph 72).
However, Ikegami does not explicitly disclose where the gate stack structure further comprises a plurality of interlayer insulating layers nor where one plate electrode is connected to a switching material layer (included in the electrode structures) in at least two cell blocks sequentially provided in the first horizontal direction.
Murooka, however, discloses an analogous memory cell array (Fig. 4), comprising a plurality of cell blocks [R1/C1/C2/C3] comprising at least two cell blocks (see annotated fig. attached above) sequentially provided in the first horizontal direction [First direction] and at least two cell blocks sequentially provided in a second horizontal direction intersecting the first horizontal direction in each of the plurality of cell regions [Third direction], and wherein at least one plate electrode among the plurality of plate electrodes (elements WLcomb_a/b) is connected to the plurality of electrode structures (Fig. 2 elements WL and BL) in the least two cell blocks sequentially provided in the first horizontal direction [First direction].
However, Murooka does not explicitly disclose where the plurality of electrode structures comprises a switching material layer in addition to the vertical electrodes.
Fantini discloses an analogous memory array (Fig. 6), comprising a gate stack structure including a plurality of gate electrodes (Fig. 3-5 elements 315/445) and a plurality of interlayer insulating layers (element 305) that are alternately stacked in the vertical direction (paragraphs 52-59), and wherein each of the plurality of gate electrodes (Fig. 5A elements 445) extends into the villus shapes of the folding structure (paragraph 66) and is connected to the switching material layer (paragraph 64) included in the plurality of electrode structures (elements 335/480).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami further in view of Fantini and Murooka to explicitly include where the gate stack structure additionally includes a plurality of interlayer insulating structures vertically stacked with the plurality of gate electrodes. Furthermore, where the plurality of electrode structures include a switching material layer connected to the sawtooth parts and at least one plate electrode because both are direct to analogous architecture in memory devices. Doing so allows for improvements on integration and electrical performance in memory devices(Fantini, paragraphs 11-13 and Murooka, paragraphs 2, 91-92, and 157-158).
Regarding Claim 20:
The combination of Ikegami, Fantini, and Murooka discloses a semiconductor memory device according to claim 19, but neither Ikegami nor Murooka explicitly disclose where the plurality of sawtooth parts are connected to a switching mater layer of the plurality of electrode structures.
Fantini discloses an analogous memory array (Fig. 6), wherein the plurality of plate electrodes (Figs. 5 element 445) are connected to the switching material layer (element 465) of the plurality of electrode structures (elements 335/480), and have comb shapes that are staggered from each other (paragraphs 11 and 74).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Ikegami and Murooka further in view of Fantini to explicitly include where the plurality of sawtooth parts extending from one of the at least two shaft parts are connected to the switching material layer of the plurality of electrodes. Furthermore, the sawtooth parts have comb shapes that are staggered from each other because both are directed to analogous architectures for memory devices. Doing so allows memory devices with higher integration densities while maintaining reliable complex structures (Fantini, paragraphs 11-13).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sasaki et el. (US 20190273092 A1), Nardi et al. (US 10262730 B1), Naruke et al. (US 20210091108 A1).
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
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