DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6 in the reply filed on 1/21/2026 is acknowledged.
Claims 7-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lea (pub #US 20190066761 A1) further in view of Walker (pub #US 20200159435 A1).
Regarding claim 1, Lea discloses a signal processing circuit comprising: a plurality of first pads assigned to input and output data, commands, and addresses (data and address bus 156, control bus 154, paragraph 35, 36); a second pad (sideband channel, paragraph 157; Lea teaches that the sideband bus is separate from the data/address/control bus, and may be used for special commands and status; paragraph 35-37 details various functions of the sideband channel); and a signal processing logic circuit (controller 140, paragraph 35) configured to identify a received request based a second signal transmitted through the second pad during operation modes other than a data input mode and a data output mode.
Lea does not disclose explicitly using a combination of first and second pads to identify requests. However, Walker discloses requests based on a combination of a first signal set transmitted through the plurality of first pads and second pad (using a combination of data bus, command bus, status bus, and a sideband channel to transmit command information, paragraph 196; to generate new/modified commands, such as commit, evict, other types of non-traditional data commands, paragraphs 201, 202). Furthermore, teachings of Lea and Walker are from the same field of data interfaces.
Therefore, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to combine teachings of Lea with Walker by using a combination of signals from the various links of the bus to transfer commands for the benefit of fully using the bandwidth of the data interface.
Regarding claim 2, the above combination discloses signal processing circuit of claim 1, wherein the signal processing logic circuit includes a command decoder configured to receive and decode the first signal set and the second signal as a command set in a command input mode among the operation modes (decoder circuitry in controller 140, paragraph 51, Lea).
Regarding claim 3, the above combination discloses signal processing circuit of claim 2, wherein the command set includes: a first signal set comprising at least one of a setup command, at least one address, data, and a confirmation command (a first command followed by a second command, paragraph 197, access command and commit commands given as example); and the second signal transmitted through the second pad during a time period when any of the at least one address, the confirmation command is input (commit command, paragraph 201, Walker).
Regarding claim 4, the above combination discloses signal processing circuit of claim 2, wherein the signal processing logic circuit further comprises an address latch configured to receive and store the first signal set and the second signal as the addresses during an address input mode among the operation modes (addresses and corresponding address decoders for memory accesses, paragraph 77, Walker).
Regarding claim 5, the above combination discloses signal processing circuit of claim 1, further comprising a data bus inversion circuit configured to invert and output a signal transmitted through the plurality of first pads in response to a data bus inversion signal transmitted through the second pad during the data input mode (inversion circuits where well-known before the effective filing date of the invention, such as taught in Hobbs, US 20170324606 A1, paragraph 22, for the benefit of eliminating backflow current that may interfere with communications over data bus, and would have been obvious for a person of ordinary skill in the art of data transfer interfaces).
Regarding claim 6, the above combination discloses signal processing circuit of claim 1, wherein the signal processing logic circuit is configured to output status information corresponding to a status information output mode by outputting a third signal set through the plurality of first pads and a fourth signal through the second pad during the status information output mode among the operation modes a status bus, and corresponding manager, paragraph 195, 196; Walker; various command status signals are discussed throughout the reference, such as those shown in figures 6-9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181