DETAILED ACTION
This action is responsive to the communication filed on 9/29/2025. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-7 are objected to because of the following informalities:
In claim 1, line 14, ‘the plurality of block’ should be amended to read as ‘the plurality of [[block]] blocks’
Appropriate correction is required.
Claims 2-7 objected to for being dependent on an objected claim.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With respect to claims 1, 8, and 14, the claims as amended provide for at least one of a plurality of pages in a first block being programmed to a second block, a remainder of the plurality of pages other than said at least one of the plurality of pages being refreshed in place in the first block, and, following the programming and refreshing, at least one of the plurality of pages being stored only in the first block and at least one of the plurality of pages being stored only in the second block. While paragraphs 130-136 of the specification appear to provide pertinent disclosure(s) concerning relocating certain pages of a block and refreshing other pages in place, the specification does not appear to provide, in performing the combination of relocating and refreshing, erasing, in the first block, the pages that have been relocated. Therefore, the disclosure according to the pertinent paragraphs of the specification appears to suggest that said relocated pages may be located in both the first and the second blocks.
Rest of the claims as listed are rejected for being dependent on a rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, claim 1 recites blocks storing data arranged in a plurality of pages, performing a readout of the plurality of pages of data, programming at least one of the plurality of pages of data to a second block, and refreshing a remainder of the plurality of pages other than the at least one of the plurality of pages (claim 1, lines 1-12). However, with respect to the amended limitation(s), line 13 recites ‘after programming the at least one of the pages of data to the second one of the plurality of block…’. While the claim recites a/the ‘plurality of pages’ as shown above, the claim does not appear contain an earlier recitation of the ‘pages’ as used in line 13. Therefore, there is insufficient antecedent basis for the term, and the scope of the related subject matter is unclear as to whether the programming of the at least one of the pages of data to the second block in lines 13-14 is intended correspond to an earlier, similarly recited subject matter in lines 8-9.
In addition, line 16 of claim 1 similarly recites ‘at least one of the pages of data’ being stored only in the first block. There is insufficient antecedent basis for the term for similar reasons as above. In addition, ‘at least one of the pages of data’ in line 16 is unclear as to whether it is intended to correspond to the earlier recitation of ‘the at least one of the pages of data’ in line 13 or not.
Lines 14-15 of claim 1 recite ‘... refreshing the remainder of the plurality of pages other than the one of the plurality of pages in place…’. While the claim contains earlier recitations of a/the ‘at least one of the plurality of pages’, the claim does not appear to contain an earlier recitation of the ‘one of the plurality of pages’ as used in line 15. Therefore, there is insufficient antecedent basis for the term, and the scope of the related subject matter is unclear as to whether abstaining from refreshing the one of the plurality of pages in lines 14-15 is intended to correspond to an earlier, similarly recited subject matter in lines 10-11.
Lines 17-18 of claim 1 recites ‘at least one of the plurality of pages of data’ stored only in the second block. While an identical term is also recited previously in lines 8-9, the claim is unclear as to whether the term as used in lines 17-18 is intended to correspond to the term in lines 8-9, as the recitation in lines 17-18 does not indicate a presence of an antecedent basis.
As per claim 8, where line 7 of the claim recites ‘at least one of the plurality of pages of data,’ the claim comprises subsequent recitations of the term that do not sufficiently indicate an antecedent basis. For example, lines 11-12, 14-15, and 15-16 recite ‘at least one of the plurality of pages data’ without indicating a presence of an antecedent basis. The terms as recited are also additionally unclear as to whether they were intended to refer to the same at least one of the plurality of pages or different instances comprising at least one of the plurality of pages.
Lines 9-10 of the claim recites ‘a remainder of the plurality of pages’, and lines 13-14 again recite ‘a remainder of the plurality of pages’ without sufficiently providing an antecedent basis.
As for claim 14, where line 7 of the claim recites ‘at least one of the plurality of pages of data,’ the claim comprises subsequent recitations of the term that do not sufficiently indicate an antecedent basis. For example, lines 11-12 and 12-13 recite ‘at least one of the plurality of pages of data’ without indicating a presence of an antecedent basis. The terms as recited are also additionally unclear as to whether they were intended to refer to the same at least one of the plurality of pages or different instances comprising at least one of the plurality of pages.
Rest of the claims as listed are rejected for being dependent on a rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20160098216 A1) in view of Song et al. (US 20180068726 A1) in view of Sharifi Tehrani et al. (US 20210319834 A1).
As per claim 1,
1.A memory apparatus, comprising: memory cells each configured to retain a threshold voltage corresponding to one of a plurality of data states and grouped into a plurality of blocks storing data arranged in a plurality of pages; and a control means configured to: [Huang teaches a memory device (memory apparatus) comprising non-volatile memory and a controller controlling operations of the device (para. 63-81; see para. 90 for pages and blocks) and memory cells storing bits of information corresponding to voltage levels/states (para. 36)]
perform a readout of the plurality of pages of the data of a first one of the plurality of blocks of the memory cells, [Huang teaches performing in-place refresh on a memory block, where the in-place refresh maybe involve reading out the pages in the block, error correcting the pages, and performing the refresh by reprogramming the data (para. 42-45, 108, 122, 125-128, 136-137; figs. 8B, 13B, and associated paragraphs; where Huang provides various embodiment specifying certain design/aspects of the refresh process, Huang provides for structural/logical substitutions and changes to the to the embodiments without departing from the scope of the disclosure (para. 136-137))]
Huang does not explicitly disclose, but Song discloses:
program at least one of the plurality of pages of the data to a second one of the plurality of blocks, refresh a remainder of the plurality of pages other than the at least one of the plurality of pages in place in the first one of the plurality of blocks, [Huang as shown above teaches performing in-place refresh (see the rejection above), wherein in-place refresh is performed to address retention and program disturbance problems in lieu of relocating the data to another block (para. 37-42); however, if the in-place refresh is not successful, the block is still relocated to the other block (para. 45); Song teaches separately addressing retention and disturbance problems by selecting a process better suiting the type of error, where a page with retention error is error corrected and reprogrammed in the same page while a page with read disturbance error is error corrected and programmed to a different page, (abstract, para. 4-7, 18-19, 36-47 claim 1)]
Huang in view of Song is analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined disclosures by Huang, directed towards resolving retention and program disturbance issues by reading out pages in a block, performing in-place refresh, and relocating the data to another block if the refresh is not successful, and disclosures by Song, directed towards tailoring error handling processes to the type of error by performing in-place reprogramming with pages having retention errors while reprogramming pages having read disturb error to a different page, to provide for a combination where a plurality of pages of the block are read out for refresh and rewritten to the block, except for pages determined to have disturbance error, which are written to a different block. Doing so would provide for a remediation method using processes best suiting the type of error (para. 45).
Huang in view of Song does not explicitly disclose, but Sharifi Tehrani discloses:
and wherein after programming the at least one of the pages of data to the second one of the plurality of block and refreshing the remainder of the plurality of pages other than the one of the plurality of pages in place in the first one of the plurality of memory blocks, at least one of the pages of data is stored only in the first one of the plurality of blocks and at least one of the plurality of pages of data is stored only in the second one of the plurality of blocks. [Huang in view of Song as shown above teaches rewriting pages of a block to the same block except for pages with read disturbance error, which are written to a different block (see the rejection above; Huang: 42-45, 108, 122, 125-128, 136-137; Song: para. 4-7, 18-19, 36-47); Sharifi Tehrani teaches performing read disturb mitigation by migrating data from a portion of a block to another block, followed by erasing the data stored in the portion (para. 54, 61-66; fig. 3 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Huang in view of Song, where pages of a block are rewritten to the block except for pages having read disturbance, which are written to a different block, and disclosures by Sharifi Tehrani, directed towards migrating data from a portion of a block to another block and erasing the portion for read disturb mitigation, to provide for a combination where pages of a block are rewritten to the block except for pages having read disturbance, which are rewritten to a different block prior to being erased; doing so would provide for improved storage efficiency in association with error handling]
Huang, Song, and Sharifi Tehrani are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang in view of Song and Sharifi Tehrani, to modify the disclosures by Huang in view of Song to include disclosures by Sharifi Tehrani since they both teach data storage, wherein Sharifi Tehrani is directed towards improved memory subsystem performance (para. 19). Therefore, it would be applying a known technique (migrating data from a portion of a block associated with read disturbance, erasing the portion after moving the data) to a known device (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block) ready for improvement to yield predictable results (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block prior and subsequently erased to provide for improved storage efficiency). MPEP 2143
As per claim 2, Huang in view of Song in view of Sharifi Tehrani teaches claim 1 as shown above and further teaches:
2. The memory apparatus as set forth in claim 1, further including an error correction coding engine configured to detect errors in the data and generate a corresponding bit error rate and wherein the control means is further configured to perform the readout and the programming and the refreshing based on the bit error rate. [Where Huang in view of Song teaches refreshing/reprogramming of a block which involves initially reading data from the block, Huang teaches determining whether to refresh the block based on errors in the block determined by an ECC engine and provides examples such as bit error rate and fail bit counts (para. 37-38, 43-45, 99, 109-110, 126-127, 136-137; fig. 9 and associated paragraphs)]
As per claim 8,
8. A controller in communication with a memory apparatus including memory cells each configured to retain a threshold voltage corresponding to one of a plurality of data states and grouped into a plurality of blocks storing data arranged in a plurality of pages, the controller configured to: [Huang teaches a memory device (memory apparatus) comprising non-volatile memory and a controller controlling (performing, instructing) operations of the device (para. 63-81; see para. 90 for pages and blocks) and memory cells storing bits of information corresponding to voltage levels/states (para. 36)]
perform a readout of the plurality of pages of the data of a first one of the plurality of blocks of the memory cells; [Huang teaches performing in-place refresh on a memory block, where the in-place refresh maybe involve reading out the pages in the block, error correcting the pages, and performing the refresh by reprogramming the data (para. 42-45, 108, 122, 125-128, 136-137; figs. 8B, 13B, and associated paragraphs; where Huang provides various embodiment specifying certain design/aspects of the refresh process, Huang provides for structural/logical substitutions and changes to the to the embodiments without departing from the scope of the disclosure (para. 136-137))]
Huang does not explicitly disclose, but Song discloses:
instruct the memory apparatus to program at least one of the plurality of pages of the data to a second one of the plurality of blocks; instruct the memory apparatus to refresh a remainder of the plurality of pages other than the at least one of the plurality of pages in place in the first one of the plurality of blocks; [Huang as shown above teaches performing in-place refresh (see the rejection above), wherein in-place refresh is performed to address retention and program disturbance problems in lieu of relocating the data to another block (para. 37-42); however, if the in-place refresh is not successful, the block is still relocated to the other block (para. 45); Song teaches separately addressing retention and disturbance problems by selecting a process better suiting the type of error, where a page with retention error is error corrected and reprogrammed in the same page while a page with read disturbance error is error corrected and programmed to a different page, (abstract, para. 4-7, 18-19, 36-47 claim 1)]
Huang in view of Song is analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined disclosures by Huang, directed towards resolving retention and program disturbance issues by reading out pages in a block, performing in-place refresh, and relocating the data to another block if the refresh is not successful, and disclosures by Song, directed towards tailoring error handling processes to the type of error by performing in-place reprogramming with pages having retention errors while reprogramming pages having read disturb error to a different page, to provide for a combination where a plurality of pages of the block are read out for refresh and rewritten to the block, except for pages determined to have disturbance error, which are written to a different block. Doing so would provide for a remediation method using processes best suiting the type of error (para. 45).
Huang in view of Song does not explicitly disclose, but Sharifi Tehrani discloses:
and wherein after instructing the memory apparatus to program at least one of the plurality of pages of data to the second one of the plurality of memory blocks and after instructing the memory apparatus to refresh a remainder of the plurality of pages other than the at least one of the plurality of pages in place in the first one of the plurality of blocks, at least one of the plurality of pages of data is stored only in the first one of the plurality of blocks and at least one of the plurality of pages of data is stored only in the second one of the plurality of blocks [Huang in view of Song as shown above teaches rewriting pages of a block to the same block except for pages with read disturbance error, which are written to a different block (see the rejection above; Huang: 42-45, 108, 122, 125-128, 136-137; Song: para. 4-7, 18-19, 36-47); Sharifi Tehrani teaches performing read disturb mitigation by migrating data from a portion of a block to another block, followed by erasing the data stored in the portion (para. 54, 61-66; fig. 3 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Huang in view of Song, where pages of a block are rewritten to the block except for pages having read disturbance, which are written to a different block, and disclosures by Sharifi Tehrani, directed towards migrating data from a portion of a block to another block and erasing the portion for read disturb mitigation, to provide for a combination where pages of a block are rewritten to the block except for pages having read disturbance, which are rewritten to a different block prior to being erased; doing so would provide for improved storage efficiency in association with error handling]
Huang, Song, and Sharifi Tehrani are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang in view of Song and Sharifi Tehrani, to modify the disclosures by Huang in view of Song to include disclosures by Sharifi Tehrani since they both teach data storage, wherein Sharifi Tehrani is directed towards improved memory subsystem performance (para. 19). Therefore, it would be applying a known technique (migrating data from a portion of a block associated with read disturbance, erasing the portion after moving the data) to a known device (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block) ready for improvement to yield predictable results (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block prior and subsequently erased to provide for improved storage efficiency). MPEP 2143
Claim 9 has been rejected for reasons similar to claim 2 above.
As per claim 14,
14. A method of operating a memory apparatus including memory cells each configured to retain a threshold voltage corresponding to one of a plurality of data states and grouped into a plurality of blocks storing data arranged in a plurality of pages, the method comprising the steps of: [Huang teaches a memory device (memory apparatus) comprising non-volatile memory and a controller controlling operations of the device (para. 63-81; see para. 90 for pages and blocks) and memory cells storing bits of information corresponding to voltage levels/states (para. 36)] performing a readout of the plurality of pages of the data of a first one of the plurality of blocks of the memory cells; [Huang teaches performing in-place refresh on a memory block, where the in-place refresh maybe involve reading out the pages in the block, error correcting the pages, and performing the refresh by reprogramming the data (para. 42-45, 108, 122, 125-128, 136-137; figs. 8B, 13B, and associated paragraphs; where Huang provides various embodiment specifying certain design/aspects of the refresh process, Huang provides for structural/logical substitutions and changes to the to the embodiments without departing from the scope of the disclosure (para. 136-137))]
Huang does not explicitly disclose, but Song discloses:
programming at least one of the plurality of pages of the data to a second one of the plurality of blocks; refreshing a remainder of the plurality of pages other than the at least one of the plurality of pages in place in the first one of the plurality of blocks; [Huang as shown above teaches performing in-place refresh (see the rejection above), wherein in-place refresh is performed to address retention and program disturbance problems in lieu of relocating the data to another block (para. 37-42); however, if the in-place refresh is not successful, the block is still relocated to the other block (para. 45); Song teaches separately addressing retention and disturbance problems by selecting a process better suiting the type of error, where a page with retention error is error corrected and reprogrammed in the same page while a page with read disturbance error is error corrected and programmed to a different page, (abstract, para. 4-7, 18-19, 36-47 claim 1)]
Huang in view of Song is analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined disclosures by Huang, directed towards resolving retention and program disturbance issues by reading out pages in a block, performing in-place refresh, and relocating the data to another block if the refresh is not successful, and disclosures by Song, directed towards tailoring error handling processes to the type of error by performing in-place reprogramming with pages having retention errors while reprogramming pages having read disturb error to a different page, to provide for a combination where a plurality of pages of the block are read out for refresh and rewritten to the block, except for pages determined to have disturbance error, which are written to a different block. Doing so would provide for a remediation method using processes best suiting the type of error (para. 45).
Huang in view of Song does not explicitly disclose, but Sharifi Tehrani discloses:
And wherein after the programming and refreshing steps, at least one of the plurality of pages of data is stored only in the first one of the plurality of blocks and at least one of the plurality of pages of data is stored only in the second one of the plurality of blocks. [Huang in view of Song as shown above teaches rewriting pages of a block to the same block except for pages with read disturbance error, which are written to a different block (see the rejection above; Huang: 42-45, 108, 122, 125-128, 136-137; Song: para. 4-7, 18-19, 36-47); Sharifi Tehrani teaches performing read disturb mitigation by migrating data from a portion of a block to another block, followed by erasing the data stored in the portion (para. 54, 61-66; fig. 3 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Huang in view of Song, where pages of a block are rewritten to the block except for pages having read disturbance, which are written to a different block, and disclosures by Sharifi Tehrani, directed towards migrating data from a portion of a block to another block and erasing the portion for read disturb mitigation, to provide for a combination where pages of a block are rewritten to the block except for pages having read disturbance, which are rewritten to a different block prior to being erased; doing so would provide for improved storage efficiency in association with error handling]
Huang, Song, and Sharifi Tehrani are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang in view of Song and Sharifi Tehrani, to modify the disclosures by Huang in view of Song to include disclosures by Sharifi Tehrani since they both teach data storage, wherein Sharifi Tehrani is directed towards improved memory subsystem performance (para. 19). Therefore, it would be applying a known technique (migrating data from a portion of a block associated with read disturbance, erasing the portion after moving the data) to a known device (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block) ready for improvement to yield predictable results (system configured to rewrite pages of data in a block to the same block except for pages having read disturbance, which are written to a different block prior and subsequently erased to provide for improved storage efficiency). MPEP 2143
Claim 15 has been rejected for reasons similar to claim 2 above.
Claims 3, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20160098216 A1) in view of Song et al. (US 20180068726 A1) in view of Sharifi Tehrani et al. (US 20210319834 A1) in view of Hyun et al. (US 20150193299 A1) in view of Muthiah et al. (US 20210081316 A1).
As per claim 3, Huang in view of Song in view of Sharifi Tehrani teaches claim 1 as shown above and further teaches:
3. The memory apparatus as set forth in claim 1, wherein the control means is further configured to: receive a host write request in the first one of the plurality of blocks; program the plurality of pages of the data to the first one of the plurality of blocks; [Huang teaches a host which stores data on the memory device and which sends write command for performing write on the device (para. 43, 66)]
monitor the memory cells of the first one of the plurality of blocks for exposure to data retention stress; periodically determine whether the data retention stress of the memory cells of the first one of the plurality of blocks exceeds a predetermined data retention stress threshold; return to monitor the memory cells of the first one of the plurality of blocks for exposure to data retention stress in response to the data retention stress of the memory cells of the first one of the plurality of blocks not exceeding the predetermined data retention stress threshold; [Huang teaches determining errors (retention stress) in blocks determined to indicate certain characteristic (high age, P/E, etc.), with the controller starting the refresh operation if the error amount exceeds a threshold, but, if the error amount does not exceed the threshold, returning to determining whether the blocks indicate the characteristic triggering the error determination (para. 43-45, 109-110, 125-127; figs. 9, 13B and associated paragraphs)]
perform the readout of the plurality of pages of the data of the first one of the plurality of blocks of the memory cells after finding the second one of the plurality of blocks; program at least one of the plurality of pages of the data to the second one of the plurality of blocks after erasing the second one of the plurality of blocks; refresh the remainder of the plurality of pages other than the at least one of the plurality of pages in place in the first one of the plurality of blocks by reprogramming the remainder of the plurality of pages to the first one of the plurality of blocks; and finish the readout and the programming and the refreshing. [Huang in view of Song in view of Sharifi Tehrani as shown above teaches reading out pages in a block and rewriting the pages of data to the same pages in the block or to a different block depending on whether the page has a disturbance error (see claim 1 above; Huang para. 42-45, 108, 122, 125-128, 136-137; Song: abstract, para. 4-7, 18-19, 36-47; Sharifi Tehrani: para. 54, 61-66)]
Huang in view of Song in view of Sharifi Tehrani does not explicitly disclose, but Hyun discloses:
find the second one of the plurality of blocks in response to the data retention stress of the memory cells of the first one of the plurality of blocks exceeding the predetermined data retention stress threshold;; after finding the second one of the plurality of blocks [Huang in view of Song in view of Sharifi Tehrani as shown above teaches performing a refresh operation responsive to block error (retention stress) exceeding a threshold (see the rejection above, Huang: para. 43-45, 109-110, 125-127; see para. 45 showing controller command for refresh), the refresh operation involving reading out pages from a block, error correcting the pages, and rewriting the pages to the first block and/or the second block (see claim 1 above; see Hyun), it does not explicitly disclose the timing of selecting the second block; Hyun teaches an internal data move operation which involves reading out the pages in a source block, refreshing certain pages read using ECC, and writing the pages to a destination block, where the command for the internal data move provides both the source and destination blocks (para. 101-106, 121, 186-187, 223-224)]
Huang, Song, Sharifi Tehrani, and Hyun are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang in view of Song in view of Sharifi Tehrani and Hyun, to modify the disclosures by Huang in view of Song in view of Sharifi Tehrani to include disclosures by Hyun since they both teach memory access and data storage, wherein Hyun’s disclosure is related to improvements in memory management (para 2). Therefore, it would be applying a known technique (specifying a source and destination blocks in an internal data move command involving reading and error correcting source block data and writing data to the destination block) to a known device (memory device performing refresh operation responsive to the errors of a first block exceeding a threshold, the refresh operation involving reading and error correcting first block’s data and rewriting the data to the first block and/or a second block) ready for improvement to yield predictable results (memory device performing refresh operation responsive to the errors of a first block exceeding a threshold, the refresh operation involving reading and error correcting first block’s data and rewriting the data to the first block and/or a second block, wherein the command for the refresh operation may specify the first and the second block in order to provide for improved operation speed by providing the potential second/destination block upfront). MPEP 2143
Huang in view of Song in view of Sharifi Tehrani in view of Hyun does not explicitly disclose, but Muthiah discloses:
erase the second one of the plurality of blocks in response to the second one of the plurality blocks being full;; after erasing the second one of the plurality of blocks
[Huang in view of Song in view of Sharifi Tehrani in view of Hyun as taught above teaches refreshing data in a first block to the first block and/or a second block (see the rejection above; also see Huang: para. 41 indicating previous erasure of the second/other block receiving the data); Muthiah teaches performing garbage collection on a block that is full, so the full block can be erased after moving valid data and reused (para. 37)]
Huang, Song, Sharifi Tehrani, Hyun, and Muthiah are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang in view of Song in view of Sharifi Tehrani in view of Hyun and Muthiah, to modify the disclosures by Huang in view of Song in view of Sharifi Tehrani in view of Hyun to include disclosures by Muthiah since they both teach memory access and data storage, wherein Muthiah’s disclosure is related to efficiency in garbage collection (para. 57). Therefore, it would be applying a known technique (performing a garbage collection on a full block and thereby moving valid data, erasing the block, and reusing the block) to a known device (memory device refreshing data of a first block into the first and a second block, the second block previously having been erased) ready for improvement to yield predictable results (memory device refreshing data of a first block into the first and a second, previously erased, block, the blocks of the memory device being garbage collected and erased when full to allow the block to be reused; where providing for garbage collection of the full blocks may provide for improved management of storage space by salvaging only valid data and making the block available for reuse). MPEP 2143
Claim 10 is rejected for reasons similar to claim 3 above.
Claim 16 is rejected for reasons similar to claim 3 above.
Claims 4-6, 11-13, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20160098216 A1) in view of Song et al. (US 20180068726 A1) in view of Sharifi Tehrani et al. (US 20210319834 A1) in view of Hyun et al. (US 20150193299 A1) in view of Muthiah et al. (US 20210081316 A1) in view of Kumar et al. (US 20220254416 A1).
As per claim 4, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah discloses claim 3 as shown above. It does not explicitly disclose, but Kumar discloses:
4. The memory apparatus as set forth in claim 3, wherein the data is stored in the memory cells as three bits per each of the memory cells, the plurality of pages includes a lower page and a middle page and an upper page, [Kumar teaches storing data using lower, middle, and upper pages and storing three bits per cell (para. 125; fig. 8A-8B and associated paragraphs)] the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erase state and a first data state and a second data state and a third data state and a fourth data state and a fifth data state and a sixth data state and a seventh data state, [Kumar teaches the data having an erased state and seven states in order (A, B, C, D, E, F, G) (para. 125)] the lower page corresponds with the first data state and the fifth data state [The lower page data can be determined by applying voltages associated with states A and E (first and fifth states) (para. 125)] and the middle page corresponds with the second data state and the fourth data state and the sixth data state [The middle page data can be determined by using read voltages associated with states B, D, and F (second, fourth, sixth states) (para. 127)] and the upper page corresponds with the third data state and the seventh data state, [The upper page data can be determined by using read voltages associated with states C and G (third and seventh states) (para. 128)] and the control means is further configured to: program at least one of the lower page or the middle page of the data to the second one of the plurality of blocks; and refresh at least one of the middle page or the upper page in place in the first one of the plurality of blocks by reprogramming the at least one of the middle page or the upper page to the first one of the plurality of blocks. [Where Kumar as shown above teaches using lower, middle, and upper pages to store data, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah as shown above teaches refreshing pages of a block to the same block and/or a different block based on a page having disturbance error (see claim 1 above; Huang: para. 42-45, 108, 122, 125-128, 136-137; Song: abstract, para. 4-7, 18-19, 36-47 claim 1; also see Hyun: fig. 4 providing lower, middle, upper pages), where, therefore, one or more of the pages (e.g. lower, middle, upper pages) may be respectively refreshed in place or to the different block based on the error associated with the page]
Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar, to modify the disclosures by Huang, Song, Sharifi Tehrani, Hyun, and Muthiah to include disclosures by Kumar since they both teach memory access and data storage, wherein Kumar is directed towards management of voltage shifts in memory (para. 52-57). Therefore, it would be applying a known technique (TLC cells storing data in pages having respective voltages for determining the data of each page) to a known device (memory device refreshing pages of a block to the same block or a different block based on associated error) ready for improvement to yield predictable results (memory device refreshing pages of a block to the same block or a different block based on associated error, where the pages are associated with respective voltages for determining the data of each page to provide for greater modularity in handling read of the pages in event of the pages being refreshed to different blocks). MPEP 2143
As per claim 5, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah in view of Kumar teaches claim 4 as shown above and further teaches:
5. The memory apparatus as set forth in claim 4, wherein the control means is further configured to: program only the lower page of the data to the second one of the plurality of blocks; and refresh the middle page and the upper page in place in the first one of the plurality of blocks by reprogramming the middle page and the upper page to the first one of the plurality of blocks. [Where Kumar as shown above teaches using lower, middle, and upper pages to store data, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah as shown above teaches refreshing pages of a block to the same block and/or a different block based on a page having disturbance error (see claim 1 above; Huang: para. 42-45, 108, 122, 125-128, 136-137; Song: abstract, para. 4-7, 18-19, 36-47 claim 1; also see Hyun: fig. 4 providing lower, middle, upper pages), where, therefore, one or more of the pages (e.g. lower, middle, upper pages) may be respectively refreshed in place or to the different block based on the error associated with the page]
Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar, to modify the disclosures by Huang, Song, Sharifi Tehrani, Hyun, and Muthiah to include disclosures by Kumar since they both teach memory access and data storage, wherein Kumar is directed towards management of voltage shifts in memory (para. 52-57). Therefore, it would be applying a known technique (TLC cells storing data in pages having respective voltages for determining the data of each page) to a known device (memory device refreshing pages of a block to the same block or a different block based on associated error) ready for improvement to yield predictable results (memory device refreshing pages of a block to the same block or a different block based on associated error, where the pages are associated with respective voltages for determining the data of each page to provide for greater modularity in handling read of the pages in event of the pages being refreshed to different blocks). MPEP 2143
As per claim 6, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah in view of Kumar teaches claim 4 as shown above and further teaches:
6. The memory apparatus as set forth in claim 4, wherein the control means is further configured to: program the lower page and the middle page of the data to the second one of the plurality of blocks; and refresh only the upper page in place in the first one of the plurality of blocks by reprogramming the middle page and the upper page to the first one of the plurality of blocks. [Where Kumar as shown above teaches using lower, middle, and upper pages to store data, Huang in view of Song in view of Sharifi Tehrani in view of Hyun in view of Muthiah as shown above teaches refreshing pages of a block to the same block and/or a different block based on a page having disturbance error (see claim 1 above; Huang: para. 42-45, 108, 122, 125-128, 136-137; Song: abstract, para. 4-7, 18-19, 36-47 claim 1; Sharifi Tehrani: para. 54, 61-66; also see Hyun: fig. 4 providing lower, middle, upper pages), where, therefore, one or more of the pages (e.g. lower, middle, upper pages) may be respectively refreshed in place or to the different block based on the error associated with the page]
Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Huang, Song, Sharifi Tehrani, Hyun, Muthiah, and Kumar, to modify the disclosures by Huang, Song, Sharifi Tehrani, Hyun, and Muthiah to include disclosures by Kumar since they both teach memory access and data storage, wherein Kumar is directed towards management of voltage shifts in memory (para. 52-57). Therefore, it would be applying a known technique (TLC cells storing data in pages having respective voltages for determining the data of each page) to a known device (memory device refreshing pages of a block to the same block or a different block based on associated error) ready for improvement to yield predictable results (memory device refreshing pages of a block to the same block or a different block based on associated error, where the pages are associated with respective voltages for determining the data of each page to provide for greater modularity in handling read of the pages in event of the pages being refreshed to different blocks). MPEP 2143
Claim 11 is rejected for reasons similar to claim 4 above.
Claim 12 is rejected for reasons similar to claim 5 above.
Claim 13 is rejected for reasons similar to claim 6 above.
Claim 17 is rejected for reasons similar to claim 4 above.
Claim 18 is rejected for reasons similar to claim 5 above.
Claim 19 is rejected for reasons similar to claim 6 above.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20160098216 A1) in view of Song et al. (US 20180068726 A1) in view of Sharifi Tehrani et al. (US 20210319834 A1) in view of Kumar et al. (US 20220254416 A1).
As per claim 7, Huang in view of Song in view of Sharifi Tehrani discloses claim 1 as shown above and further teaches:
the control means is further configured to select the at least one of the plurality of pages of the data to be programmed to the second one of the plurality of blocks and the remainder of the plurality of pages other than the at least one of the plurality of pages to be refreshed in place in the first one of the plurality of blocks based on a location of the one of the plurality of word lines connected to the memory cells in the stack. [Huang teaches a page formed through memory cells along a word line (para. 90; see para. 58-60 for stacked three dimensional memory; also see Song: para. 29 teaching 3D NAND), the location of a page selected may necessarily correspond to the corresponding word line location]
Huang in view of Song in view of Sharifi Tehrani does not explicitly disclose, but Kumar discloses:
The memory apparatus as set forth in claim 1, wherein the memory cells are each connected to one of a plurality of word lines and are disposed in memory holes, the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, and [Kumar further specifies details of bit cost scalable architecture comprising conductive layers comprising word lines and dielectric layers stacked in an alternating fashion, memory cells formed through a vertical memory hole adjacent to the word lines (para. 4, 104-110; fig. 4 and associated paragraphs)]
The disclosures by Huang, Song, Sharifi Tehrani, and Kumar are analogous because they are in the same field of endeavor of data storage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Huang in view of Song in view of Sharifi Tehrani, and Kumar, to modify the teachings of Huang in view of Song in view of Sharifi Tehrani to include the teaching of Kumar since they both teach three dimensional NAND. Therefore, it would have been a simple substitution of one type of non-volatile memory (3D NAND architecture specifically requiring memory holes used to form cells and alternating dielectric layers) for another non-volatile memory ready for improvement to provide predictable results (use of a three dimension NAND design providing reduced interference between word line layers by using dielectric layers). MPEP 2143
Claim 20 is rejected for reasons similar to claim 7 above.
Response to Arguments
The rejections pursuant to 35 U.S.C. §112(b) indicated in the most recent previous office action are withdrawn in view of amendments to the claims.
Applicant’s arguments with respect to the rejection of claims 1, 8, 14, and claims
depending therefrom under 35 U.S.C §103 have been fully considered. While the examiner respectfully submits that a combination of Huang and Song may provide for data in respective pages of a first block being rewritten to the same first block and a second block (please see the rejections of the limitations in claims 1, 8, and 14 pertaining to Huang and Song above; Huang: 42-45, 108, 122, 125-128, 136-137; Song: para. 4-7, 18-19, 36-47), the examiner agrees that the amended independent claims indicating certain of the pages being stored only in the one of the first and other pages being stored only in the second block overcome the combination of Huang and Song. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground of rejection is made in view of amendments to the claims and newly found prior arts.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lasser (US 20150058535 A1) teaches reducing accumulation of read disturb effect by relocating data of a page to another block (para. 31).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135