DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 10/09/2024 and 01/10/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 9-13, 15-16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Egi et al. (US 2016/0292101 A1) in view of Dube et al. (US 2015/0100972 A1).
Regarding claim 1, Egi teaches a method, wherein the method is performed by a server [system], the server comprises a first-type processor and a second-type processor, performance of the second-type processor is better than that of the first-type processor ([0002] Hardware based acceleration systems are used for offloading all or part of an application's processing requirements from the CPU to some other device, such as a field-programmable gate array (FPGA), graphics processing unit (GPU), or digital signal processor (DSP). These special “acceleration devices” have some common characteristics, such as a high number of cores, fast memory, and high degree of parallelization that enables particular workloads to be executed on them at a much higher speed than on general-purposes CPUs.; [0021] a system for offloading computations from a CPU directly to an accelerator engine is described), and the method comprises:
obtaining, by the first-type processor, a first message requesting a first service ([0024] an exemplary database query… The database query may be an SQL query, for example. An exemplary sequence of computer implemented steps performed by system 100 for offloading a computation from the CPU to the accelerator Engine; [0025] Controller 102 interacts with an application to identify the function or functions, such as a DB query execution plan, that may be offloaded to Accelerator Engine 105 (step 401); wherein controller is within CPU 101, see Fig. 2);
parsing, by the first-type processor, the first message, and writing data needed by the first service into a direct memory access (DMA) space, wherein the DMA space is a storage space provided by a memory of the server [system] based on a DMA technology (Abstract: determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine; [0025] Controller 102 interacts with an application to identify the function or functions, such as a DB query execution plan, that may be offloaded to Accelerator Engine 105 (step 401) and the name of the file or files that hold the data and potentially the location, such as a block number or an offset, for these functions (step 402). In addition, once the file names (and offsets, in some situations) are known, Controller 102 retrieves the metadata associated with the files, such as inode structure, identifies whether there are dirty pages in the page cache and constructs a scatter-gather list to program DMA engine 111 and 112 for data transfer from hard disk drive 109 to Accelerator Engine 105.; [0028] With reference to Data Path 204, when the most up-to-date version of the files are on the secondary storage device, such as hard disk drive 109, Controller 102 is operable to program DMA engines 111 and 112 that will move a copy of the files on the secondary storage nodes to the Accelerator Engine 105 (step 404). To this end, CPU 101 programs the following three sets of information into the DMA controllers: See (1-3); [0029] With reference to Data Path 205, when the DMA controller has been programmed with the necessary information for the data transfer and the DMA controller is ready for transfer, the DMA controller begins its operation and moves all the data that it has been instructed with to Accelerator Engine 105.); and
reading, by the second-type processor, the data from the DMA space, and outputting a processing result of the first service (Abstract: programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic.; [0030] With reference to Data Path 206, the data transferred to Accelerator Engine 105 using DMA is processed by Accelerator Engine 105 (step 405)… The result of the computation performed on the accelerator device may be stored in Internal Memory 113 of Accelerator Engine 105 or External Memory 106 attached to Accelerator Engine 105; [0031] With reference to Data Path 207, once computation is completed by Accelerator Device 105, the results of the computation are moved to CPU 101 using a DMA operation performed by a DMA controller such as DMA engine 110 of Accelerator Device 105 or via a programmed I/O operation initiated by CPU 101. Depending on the application and what functionality has been offloaded to the accelerator device, the results may be post-processed or assembled/combined with other results created by the application running on CPU 101 before being presented or stored.).
Egi teaches a system comprising a processor and an accelerator but does not explicitly teach the system being a server.
However, Dube teaches a server ([0003] Hybrid systems are composed of different software and hardware system elements which together create the operational environment for the workloads. A hybrid system may include a main processor that is a general-purpose processing unit and one or more special hardware processing units that provide increase in computational power (referred to as accelerators). To exploit full potentials of hybrid systems one needs to appropriately run the workload on one or more of system elements within the hybrid system so as to optimize the overall performance. For example, compute intensive sections of a workload running on a processing power constrained system can potentially be offloaded to a multicore system thereby scaling the throughput. [0036] different servers (e.g., host, accelerator, database))
Regarding claim 2, Dube teaches wherein the obtaining, by the first-type processor, the first message comprises:
reading, by the first-type processor, the first message from a network adapter of the server; or receiving, by the first-type processor, the first message sent by a network adapter ([0033] FIG. 3 shows a network attached JAVA.TM. accelerator as an example in one embodiment of the present disclosure. As an example, the portion of JAVA.TM. workload that executes in the JVM space (e.g., FIG. 2 at 204) may be offloaded from a host system 302 to a network attached system called an accelerator system 304, for example providing network attach acceleration capacity.).
Regarding claim 3, Egi teaches wherein the method further comprises:
initializing, by the first-type processor, the memory, and determining the DMA space ([0025-29]); or initializing, by the second-type processor, the memory, and determining the DMA space ([0025-29]).
Regarding claim 5, Egi teaches wherein the data needed by the first service comprises service data of the first service and a function for processing the service data, and wherein:
the parsing, by the first-type processor, the first message, and the writing the data needed by the first service into DMA space comprises:
determining, by the first-type processor, a function identifier based on the first message, wherein the function identifier indicates a function list needed for executing the first service, and the function list comprises one or more functions and writing, by the first-type processor, the function list and the service data into the DMA space ([0023] Controller 102 interacts with one or more applications in order to identify the function or functions to be offloaded and the files that hold the data needed to perform those functions. Controller 102 communicates with the kernel to retrieve relevant information about the files. Information retrieved by Controller 102 may include inode number, file status, or location on disk, for example. Controller 102 may also interact with the kernel and/or a device driver for programming one or more DMA engines of Storage Controller 108 and Accelerator Engine 105. For example, Controller 102 may obtain an addresses of a DMA and/or an interrupt. An interrupt may be a Message Signaled Interrupt (“MSI”) or MSI-X.; [0025] Controller 102 interacts with an application to identify the function or functions, such as a DB query execution plan, that may be offloaded to Accelerator Engine 105 (step 401) and the name of the file or files that hold the data and potentially the location, such as a block number or an offset, for these functions (step 402). In addition, once the file names (and offsets, in some situations) are known, Controller 102 retrieves the metadata associated with the files, such as inode structure, identifies whether there are dirty pages in the page cache and constructs a scatter-gather list to program DMA engine 111 and 112 for data transfer from hard disk drive 109 to Accelerator Engine 105.; [0029-30]).
Regarding claim 6, Egi teaches wherein the second-type processor comprises one or more processors (Processing Modules 115), and wherein:
the writing, by the first-type processor, the function list and the service data into the DMA space ([0023] Controller 102 interacts with one or more applications in order to identify the function or functions to be offloaded and the files that hold the data needed to perform those functions. Controller 102 communicates with the kernel to retrieve relevant information about the files. Information retrieved by Controller 102 may include inode number, file status, or location on disk, for example. Controller 102 may also interact with the kernel and/or a device driver for programming one or more DMA engines of Storage Controller 108 and Accelerator Engine 105.; [0028] With reference to Data Path 204, when the most up-to-date version of the files are on the secondary storage device, such as hard disk drive 109, Controller 102 is operable to program DMA engines 111 and 112 that will move a copy of the files on the secondary storage nodes to the Accelerator Engine 105 (step 404).) comprises:
determining, by the first-type processor, one or more available processors in the second-type processor, wherein the one or more available processors meet a scheduling requirement ([0020] One embodiment includes determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic. [0026] With reference to Data Path 202 depicted in FIG. 2, Controller 102 prepares Accelerator Engine 105 for function execution by programming a logic of Accelerator Engine 105 using a partial or full reconfiguration (step 403)); and
writing, by the first-type processor, the function list and the service data into a ready queue (ReadyQ) in the DMA space, wherein one ReadyQ is associated with one available processor of the one or more available processors, and the one ReadyQ stores information about a to-be-processed task of the one available processor ([0030] With reference to Data Path 206, the data transferred to Accelerator Engine 105 using DMA is processed by Accelerator Engine 105 (step 405). According to some embodiments, the data to be processed by Accelerator Engine 105 may first be placed in a queue, such as first-in, first-out (FIFO), and subsequently processed. The result of the computation performed on the accelerator device may be stored in Internal Memory 113 of Accelerator Engine 105 or External Memory 106 attached to Accelerator Engine 105.).
Regarding claim 9, Egi teaches wherein the data needed by the first service comprises service data of the first service and a function for processing the service data, wherein: the reading (Fig. 3, Data Acquisition 303), by the second-type processor, the data from the DMA space, and the outputting the processing result of the first service (Fig. 3, Output data Generation 305) comprises: determining, by the second-type processor, a scheduling plan of the first service according to a user-mode thread scheduling policy in the DMA space, wherein the user-mode thread scheduling policy indicates an execution sequence of a plurality of functions and a storage resource threshold provided by the DMA space for any processor in the second-type processor, and scheduling, by the second-type processor according to the scheduling plan, the function for processing the service data, processing the service data, and outputting the processing result of the first service ([0025] Controller 102 interacts with an application to identify the function or functions, such as a DB query execution plan, that may be offloaded to Accelerator Engine 105 (step 401) and the name of the file or files that hold the data and potentially the location, such as a block number or an offset, for these functions (step 402).; [0032] With reference now to FIG. 3, an exemplary application acceleration function chain is depicted. The sequence begins at step 301, where a function call or query, such as is initiated that will be partially or fully accelerated. After the function to be accelerated has been called to the CPU, additional pre-processing, such as logical or physical plans for execution, different forms of optimization, or transformation of some data types within the function may optionally be applied to the function before the function is handed to the accelerator engine at step 302. Once the function is sent to the accelerator engine, the data to be processed is made available for processing modules 115 used for acceleration inside an accelerator engine at step 303. Once the data is available for processing modules 115, it is processed by the accelerator engine at step 304, and the output data is constructed at step 305 and moved (using direct memory access) to the CPU as a result of the function that was previously called at step 307. Before the results are returned to the function at step 307, optional post-processing functions, such as decryption may be applied at step 306.).
Regarding claim 10, it is a system type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above.
Regarding claim 11, it is a system type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 12, it is a system type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 13, it is a system type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 15, it is a system type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale above.
Regarding claim 16, it is a system type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 19, it is a system type claim having similar limitations as claim 9 above. Therefore, it is rejected under the same rationale above.
Regarding claim 20, it is a media/product type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Egi and Dube, in further view of Hunt (US 2019/0188055 A1).
Regarding claim 4, Egi teaches wherein: the first service comprises one or more tasks ([0024] an exemplary database query… The database query may be an SQL query, for example. An exemplary sequence of computer implemented steps performed by system 100 for offloading a computation from the CPU to the accelerator Engine).
Egi and Dube do not explicitly teach a semaphore up thread and a semaphore down thread of a task are mounted to a same processor in the second-type processor.
However, Hunt teaches a semaphore up thread and a semaphore down thread of a task are mounted to a same processor in the second-type processor ([0029] FIG. 3 illustrates a flow diagram of a method 300 for suppressing speculative store instructions that access semaphores in accordance with some embodiments. The method 300 is described with respect to an example implementation at the processor system 100 of FIG. 1. The method 300 begins at block 302 where the first core 104 running the first thread 114 issues a speculative store instruction 124 directed to the semaphore A 130. At block 304, the thread 114 determines whether the count X 206 of the number of flushed speculative instructions 124 in the suppression counter 108 exceeds the specified threshold value as set by the processor 102. If the count X 206 exceeds the threshold, the method 300 continues to block 308, where the suppression control module 110 prevents the thread 114 from issuing any speculative store instructions 124 until all of the older instructions have completed their execution, thus suppressing further speculative store instructions 124. If, at decision block 304, the thread 114 determines that the count X of flushed speculative store instructions 124 is not greater than the threshold, the thread 114 is allowed to issue the speculative store instruction 124 at block 306. Next, the method 300 continues at decision block 310, with the thread 114 determining whether the semaphore A 130 has been set to a value of “1”. If the semaphore A 130 has not been set, the method 300 continues to block 314, where the thread 114 completes the store instruction 124, sets the value of the semaphore A 130 to “1”, and the method 300 flow returns to block 302. On the other hand, if at block 310, the method 300 determines that the semaphore A 130 has already been set to “1”, then the method 300 continues to block 312 where the speculative store instruction is flushed and the suppression counter 108 increments the count X. Afterwards, the method 300 returns the flow to the beginning at block 302.).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Hunt with the teachings of Egi and Dube to utilize a semaphore value to determine the status of the assigned tasks in multiprocessor of different types (See at least [0012-13]). The modification would have been motivated by the desire of combining known methods to yield predictable results.
Regarding claim 14, it is a system type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Egi and Dube, in further view of Gedik et al. (US 2014/0101668 A1).
Regarding claim 7, Egi nor Dube explicitly teach wherein the server stores status information, and the status information indicates a thread identifier (ID) of the one or more processors and a quantity of idle user-mode threads mounted to the one or more processors; and
the scheduling requirement indicates that the thread ID of the one or more processors is not null, and the quantity of idle user-mode threads mounted to the one or more processors reaches a first threshold.
However, Gedik teaches wherein the server stores status information, and the status information indicates a thread identifier (ID) of the one or more processors and a quantity of idle user-mode threads mounted to the one or more processors ([0044] server; [0016] An embodiment of the invention works based on a four step control process executed at run-time. This process consists of profiling, evaluation, optimization, and thread injection. At run-time, the stream processing application is profiled to understand what threads are being used and how much work they are performing on different parts of the data flow graph. As part of the profiling step, the performance of the application can also be measured to see if the last optimization step (if there was one) helped by improving performance.; [0017]; [0026]); and
the scheduling requirement indicates that the thread ID of the one or more processors is not null, and the quantity of idle user-mode threads mounted to the one or more processors reaches a first threshold ([0017] During the optimization step, the profiling information is used to locate one or more locations in the data flow graph where the addition of additional threads is expected to improve the performance. In one embodiment, the following guiding principles are used to achieve this: threads that are highly utilized are selected to offload some of their work to the newly added thread(s). For each highly utilized thread, there can be one new thread that takes work away from it, even though a newly created thread can take away work from multiple existing threads. In at least one embodiment, the work offloading is performed such that the highly loaded threads offload half of their work as much as possible, so as to rate-match the workflows across the old and the newly created thread(s).; [0026] The processor identifies the operator(s) to add additional threads to based on the monitoring of the stream processing application during the runtime. In at least one embodiment, this includes identifying thread(s) on the identified operator that have a runtime workload above a threshold workload. For example, as illustrated in FIG. 4, both the thread T0 and T1 execute the operator 3 or the operator 4 fifty percent of the time. Both the thread T0 and T1 execute the operator 4 twenty percent of the time. If fifty percent is above a predetermined threshold workload (e.g., 49%), then the processor determines that one or more additional threads should be added to the operator 3.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gedik with the teachings of Egi and Dube to determine based on the status of a thread, whether to increase the amount of processing threads. The modification would have been motivated by the desire of efficiently profile threads executing in data flow graphs, as well as techniques to efficiently perform thread-injection on a running stream processing application. (See at least [0017])
Regarding claim 8, Gedik teaches wherein the method further comprises: determining, by the first-type processor, a quantity of available processors in the second-type processor; and based on that the quantity of the available processors is less than or equal to a second threshold, enabling, by the first-type processor, one or more processors in the second-type processor other than the available processors ([0026] The processor identifies the operator(s) to add additional threads to based on the monitoring of the stream processing application during the runtime. In at least one embodiment, this includes identifying thread(s) on the identified operator that have a runtime workload above a threshold workload. For example, as illustrated in FIG. 4, both the thread T0 and T1 execute the operator 3 or the operator 4 fifty percent of the time. Both the thread T0 and T1 execute the operator 4 twenty percent of the time. If fifty percent is above a predetermined threshold workload (e.g., 49%), then the processor determines that one or more additional threads should be added to the operator 3.; [0027]).
Regarding claim 17, it is a system type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 18, it is a system type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Narayanan et al. (US 2019/0243571 A1) See at least [0048].
Singh et al. (US 2020/0081850 A1) See at least [0082].
Lee et al. (US 2021/0263870 A1) See at least Abstract.
De (US 2017/0147516 A1) See at least [0031], [0036] and [0038-42].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE A CHU JOY-DAVILA whose telephone number is (571)270-0692. The examiner can normally be reached Monday-Friday, 6:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J Li can be reached at (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JORGE A CHU JOY-DAVILA/Primary Examiner, Art Unit 2195
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