DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted 6/7/2024 has been considered by the examiner.
Claim Objections
Claims 14 and 16-17 are objected to because of the following informalities: in claim 14, line 7, “D2connected” should be ‘connected’.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-16 and 18-19 are rejected under 35 U.S.C. 102a1 as being anticipated by Adragna (US 2021/0067046).
Examiner notes in the following rejections, the first set of rejections are made under a first embodiment depicted in Figures 4 and 6, and the second set of rejections are made under the second embodiment depicted in Figures 5 and 7.
With respect to claim 11, Adragna discloses in a first embodiment a device, comprising: a driver circuit (Fig. 2 210) including: a first terminal (Fig. 2 terminal to gate signal of SW1) configured to output a high-side gate drive signal; a second terminal (Fig. 2 terminal to gate signal of SW2) configured to output a low-side gate drive signal; a third terminal (Fig. 2 terminal to 222 ) configured to receive a resonant current signal indicative of a resonant current (Fig. 2 IS) external to the driver circuit; a fourth terminal (Fig. 2 terminal to 218) configured to receive a feedback signal based on an output signal external to the driver circuit; an integrator circuit (Fig. 4 2114,2116,2100-2104,CT) to generate a triangular integration signal (Fig. 4 VCT) based on the feedback signal (Fig. 4 IC); and a control circuit (Fig. 4 2106) configured to receive the integration signal and the resonant current signal (Fig. 4 VS) and to generate the high-side gate drive signal (Fig. 6 HSGD) and the low-side gate drive signal (Fig. 6 LSGD) based on the integration signal and the resonant current signal.
With respect to claim 12, Adragna discloses the device of claim 11, comprising an electronic converter, the electronic converter including: a positive input terminal (Fig. 2 200a) and a negative input terminal (Fig. 2 200b); two output terminals (Fig. 2 202a,202b) for providing the output signal, wherein the output signal is either an output voltage (Fig. 2 Vout) or output current; at least one half-bridge (Fig. 2 SW1,SW2) including a high-side electronic switch (Fig. 2 SW1) and a low-side electronic switch (Fig. 2 SW2) connected in series between the positive input terminal and the negative input terminals, wherein an intermediate node (Fig. 1 HB) between the high-side and the low-side electronic switch is a switching node, wherein the high-side electronic switch includes a gate terminal (Fig. 2 gate of SW1) that receives the high-side gate drive signal, wherein the low-side electronic switch includes a gate terminal (Fig. 2 gate of SW2) that receives the low-side gate drive signal.
With respect to claim 13, Adragna discloses the device of claim 12, wherein the electronic converter includes: a resonant tank (Fig. 2 204), rectifier (Fig. 1 Da,Db) and filter circuit (Fig. 1 Cout) connected between the switching node and the two output terminals, wherein the resonant current (Fig. 2 IS) flows from the switching node to the resonant tank, rectifier and filter circuit; a current sensor (Fig. 2 222) configured to generate the resonant current signal (Fig. 4 VS) proportional to the resonant current (Fig. 2 ); a feedback circuit (Fig. 2 212,214,216,218) configured to generate the feedback signal (Fig. 4 IC) as a function of the output signal (Fig. 2 Vout).
With respect to claim 14, Adragna discloses the device of claim 13, wherein the resonant tank, rectifier and filter circuit comprises: a transformer (Fig. 1 T) comprising a primary winding (Fig. 1 T1) and a secondary winding (Fig. 1 T2a,T2b); a capacitor (Fig. 1 Cr) and a first inductance (Fig. 1 Ls) connected in series with the primary winding between the switching node (Fig. 1 HB) and the positive or the negative input terminal (Fig. 1 200b); a second inductance (Fig. 1 Lp) connected in parallel with the primary winding; and a rectifier circuit (Fig. 1 Da,Db) connected between the secondary winding (Fig. 1 T2a,T2b) and the two output terminals (Fig. 1 202a,202b).
With respect to claim 15, Adragna discloses the device of claim 12, wherein the control circuit includes: an analog zero current comparator (Fig. 4 2108) configured to generate a first control signal (Fig. 4 S3) indicating when the resonant current changes sign (Fig. 6 edges of CO1) as a function of the signal (Fig. 6 Vs) received at the third terminal; and a comparison circuit (Fig. 4 2110) configured to generate a second control signal (Fig. 4 S4) indicating whether the triangular signal reaches a reference threshold (Fig. 6 Vp or Vv), wherein the control circuit is configured to generate the high-side gate drive signal (Fig. 4 HSGD) and the low-side gate drive signal (Fig. 4 LSGD) based on (Fig. 4 2112) the first control signal and the second control signal.
With respect to claim 11, Adragna alternately discloses in a second embodiment a device, comprising: a driver circuit (Fig. 2 210) including: a first terminal (Fig. 2 terminal to gate signal of SW1) configured to output a high-side gate drive signal; a second terminal (Fig. 2 terminal to gate signal of SW2) configured to output a low-side gate drive signal; a third terminal (Fig. 2 terminal to 222 ) configured to receive a resonant current signal indicative of a resonant current (Fig. 2 IS) external to the driver circuit; a fourth terminal (Fig. 2 terminal to 218) configured to receive a feedback signal based on an output signal external to the driver circuit; an integrator circuit (Fig. 5 2114,2118,2100-2102,CT) to generate a triangular integration signal (Fig. 5 VCT) based on the feedback signal (Fig. 5 IC); and a control circuit (Fig. 5 2106) configured to receive the integration signal and the resonant current signal (Fig. 5 VS) and to generate the high-side gate drive signal (Fig. 5 HSGD) and the low-side gate drive signal (Fig. 5 LSGD) based on the integration signal and the resonant current signal.
With respect to claim 12, Adragna discloses the device of claim 11, comprising an electronic converter, the electronic converter including: a positive input terminal (Fig. 2 200a) and a negative input terminal (Fig. 2 200b); two output terminals (Fig. 2 202a,202b) for providing the output signal, wherein the output signal is either an output voltage (Fig. 2 Vout) or output current; at least one half-bridge (Fig. 2 SW1,SW2) including a high-side electronic switch (Fig. 2 SW1) and a low-side electronic switch (Fig. 2 SW2) connected in series between the positive input terminal and the negative input terminals, wherein an intermediate node (Fig. 1 HB) between the high-side and the low-side electronic switch is a switching node, wherein the high-side electronic switch includes a gate terminal (Fig. 2 gate of SW1) that receives the high-side gate drive signal, wherein the low-side electronic switch includes a gate terminal (Fig. 2 gate of SW2) that receives the low-side gate drive signal.
With respect to claim 13, Adragna discloses the device of claim 12, wherein the electronic converter includes: a resonant tank (Fig. 2 204), rectifier (Fig. 1 Da,Db) and filter circuit (Fig. 1 Cout) connected between the switching node and the two output terminals, wherein the resonant current (Fig. 2 IS) flows from the switching node to the resonant tank, rectifier and filter circuit; a current sensor (Fig. 2 222) configured to generate the resonant current signal (Fig. 5 VS) proportional to the resonant current (Fig. 2 ); a feedback circuit (Fig. 2 212,214,216,218) configured to generate the feedback signal (Fig. 5 IC) as a function of the output signal (Fig. 2 Vout).
With respect to claim 14, Adragna discloses the device of claim 13, wherein the resonant tank, rectifier and filter circuit comprises: a transformer (Fig. 1 T) comprising a primary winding (Fig. 1 T1) and a secondary winding (Fig. 1 T2a,T2b); a capacitor (Fig. 1 Cr) and a first inductance (Fig. 1 Ls) connected in series with the primary winding between the switching node (Fig. 1 HB) and the positive or the negative input terminal (Fig. 1 200b); a second inductance (Fig. 1 Lp) connected in parallel with the primary winding; and a rectifier circuit (Fig. 1 Da,Db) connected between the secondary winding (Fig. 1 T2a,T2b) and the two output terminals (Fig. 1 202a,202b).
With respect to claim 15, Adragna discloses the device of claim 12, wherein the control circuit includes: an analog zero current comparator (Fig. 5 2108) configured to generate a first control signal (Fig. 5 S3) indicating when the resonant current changes sign (Fig. 6 edges of CO1) as a function of the signal (Fig. 7 Vs) received at the third terminal; and a comparison circuit (Fig. 5 2110) configured to generate a second control signal (Fig. 5 S4) indicating whether the triangular signal reaches a reference threshold (Fig. 7 Vp), wherein the control circuit is configured to generate the high-side gate drive signal (Fig. 5 HSGD) and the low-side gate drive signal (Fig. 5 LSGD) based on (Fig. 5 2112) the first control signal and the second control signal.
With respect to claim 16, Adragna discloses the device of claim 14, wherein the driver circuit is configured to: drive the high-side and the low-side electronic switch via the high-side and low-side gate drive signals during a first (Fig. 7 Δt4,Δt1) and a second (Fig. 7 Δt2,Δt3) consecutive switching semi-period, wherein each of the first and the second switching semi-period ends when the comparison circuit indicates that the triangular signal (Fig 7 V(CT)) has reached the reference threshold (Fig. 7 VP); once the first switching semi-period is started (Fig 7 beginning of Δt4), open the low-side electronic switch (Fig. 7 LSGD low), and close the high-side electronic switch after a first delay (Fig. 7 Δt4); and once the second switching semi-period is started (Fig. 7 start of Δt2), open the high-side electronic switch (Fig. 7 HSGD low), and close the low-side electronic switch after a second delay (Fig. 7 Δt2).
With respect to claim 18, Adragna discloses a method, comprising: driving, with a driver circuit (Fig. 2 210) of a resonant converter (Fig. 2 20), a high-side switch (Fig. 2 SW1) of the resonant converter with a high-side gate drive signal (Fig. 5 HSGD); driving, with the driver circuit, a low-side switch (Fig. 2 SW2) of the resonant converter with a low-side gate drive signal (Fig. 2 LSGD); receiving, with the driver circuit, a resonant current signal (Fig. 5 Vs) indicative of a resonant current (Fig. 2 Is) in a primary side of the resonant converter; receiving, with the driver circuit, a feedback signal (Fig. 5 Ic) based on an output signal (Fig. 2 Vout) of the resonant converter; generating, with an integrator circuit (Fig. 5 2100-2102,2114,2118,CT) of the driver circuit, a triangular integration signal (Fig. 5 VCT) based on the feedback signal; and generating (Fig. 5 2112), with the driver circuit, the high-side gate drive signal and the low-side gate drive signal based on the integration signal and the resonant current signal.
With respect to claim 19, Adragna discloses the method of claim 18, comprising: driving the high-side and the low-side electronic switch via the drive signals during a first (Fig. 7 Δt4,Δt1) and a second (Fig. 7 Δt2,Δt3) consecutive switching semi-period, wherein each of the first and the second switching semi-period ends when the triangular integration signal has reached a reference threshold (Fig.7 Vp); once the first switching semi-period is started, opening the low-side electronic switch (Fig. 7 LSGD low), and closing (Fig. 7 HSGD high) the high-side electronic switch after a first delay (Fig. 7 Δt4); and once the second switching semi-period is started, opening the high-side electronic switch (Fig. 7 HSGD low), and closing (Fig. 7 LSGD high) the low-side electronic switch after a second delay (Fig. 7 Δt2).
Allowable Subject Matter
Claims 1-10 are allowed while Claims 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the relevant claim objections stated above were overcome. The following is an examiner’s statement of reasons for allowance:
The invention provides an improvement over the prior art reference of Adragna (US 2021/0067046) which discloses a driver circuit (Fig. 1 210) for a resonant converter (Fig. 1 20), comprising: a first terminal (Fig. 1 HSGD) configured to output a high-side gate drive signal to a high-side electronic switch (Fig. 1 SW1) of the resonant converter; a second terminal (Fig. 1 LSGD) configured to output a low-side gate drive signal to a low-side electronic switch (Fig. 1 SW2)of the resonant converter; a third terminal (Fig. 2 terminal connected to 222) configured to receive a signal (Fig. 5 Vs) proportional to a resonant current (Fig. 2 Is) flowing in a primary side of the resonant converter; a fourth terminal (Fig. 2 terminal connected to 218) configured to receive a feedback signal (Fig. 5 Ic) based on an output voltage (Fig. 2 Vout) or an output current of the resonant converter; an analog zero current comparator (Fig. 5 2108) configured to generate a first control signal (Fig. 5 S3) indicating when the resonant current changes sign as a function of the signal (Fig. 5 Vs) received at the third terminal, a triangular wave generator circuit (Fig. 5 2100,2102,2114,2118,CT) configured to provide a triangular signal (Fig. 5 VCT); and a comparison circuit (Fig. 5 2110) configured to generate a second control signal (Fig. 5 S4) indicating whether the triangular signal reaches a reference threshold (Fig. 5 Vp); wherein the driver circuit is configured to: drive the high-side and the low-side electronic switch via the high-side and low-side gate drive signals during a first (Fig. 7 Δt4,Δt1) and a second (Fig. 7 Δt2,Δt3) consecutive switching semi-period, wherein each of the first and the second switching semi-period ends when the comparison circuit indicates that the triangular signal has reached the reference threshold (Fig. 7 Vp), once the first switching semi-period is started, open the low-side electronic switch (Fig. 7 LSGD low), and close (Fig. 7 HSGD high) the high-side electronic switch after a first delay (Fig. 7 Δt4), and once the second switching semi-period is started, open (Fig. 7 HSGD low) the high-side electronic switch, and close (Fig. 7 LSGD high) the low-side electronic switch after a second delay (Fig. 7 Δt2), but the prior art does not disclose
wherein the triangular wave generator circuit is configured to generate the triangular signal in each of the first and the second switching semi-period by: in a first interval starting at the instant when the respective semi-period starts and ending at the instant when the first control signal indicates that the resonant current has changed sign, increasing the triangular signal with a first slope, and in a second interval starting at the instant when the first control signal indicates that the resonant current has changed sign and ending at the instant when the second control signal indicates that the triangular signal has reached the reference threshold, decreasing the triangular signal with a second slope; wherein the first slope has a positive value obtained by summing a negative first value to a positive second value, and the second slope has a negative value corresponding to the first negative value, wherein the absolute value of the first value is smaller than the absolute value of the second value and the first value is proportional to the feedback signal.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 17, the prior art does not disclose wherein the integrator circuit is configured to generate the triangular integration signal in each of the first and the second switching semi-period by: in a first interval starting at the instant when the respective semi-period starts and ending at the instant when the first control signal indicates that the resonant current has changed sign, increasing the triangular signal with a first slope; and in a second interval starting at the instant when the first control signal indicates that the resonant current has changed sign and ending at the instant when the second control signal indicates that the triangular signal has reached the reference threshold, decreasing the triangular signal with a second slope; wherein the first slope has a positive value obtained by summing a negative first value to a positive second value, and the second slope has a negative value corresponding to the first negative value, wherein the absolute value of the first value is smaller than the absolute value of the second value and the first value is proportional to the feedback signal.
With respect to claim 20, the prior art does not disclose generating the triangular integration signal in each of the first and the second switching semi-period by: in a first interval starting at the instant when the respective semi-period starts and ending at the instant when the resonant current has changed sign, increasing the triangular integration signal with a first slope; and in a second interval starting at the instant when the resonant current has changed sign and ending at the instant when the triangular integration signal has reached the reference threshold, decreasing the triangular signal with a second slope; wherein the first slope has a positive value obtained by summing a negative first value to a positive second value, and the second slope has a negative value corresponding to the first negative value, wherein the absolute value of the first value is smaller than the absolute value of the second value and the first value is proportional to the feedback signal.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838