DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are pending in this application. Claims 1-6 are amended.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 06/08/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The replacement drawings received 06/22/26 are sufficient to overcome the drawing objection of the previous office action dated 03/27/26, accordingly, the drawing objections are withdrawn. The amendment to claim 6 is sufficient to overcome the claim objection of the previous office action, accordingly, the objection is withdrawn. Claim 1 has been amended to add new limitations and claim 5 has been amended to be in independent form, see rejections below.
Response to Arguments
Applicant's arguments filed 06/22/26 have been fully considered. Regarding claim 1, applicant argues on page 6 of remarks, “DATAIN 132 and DATAIN 140 appear to originate from some system external to the Nuttgens compensation circuit. Further, Nuttgens does not disclose that DATAIN 132 and DATAIN 140 come from within the compensation circuit. Therefore, Nuttgens could not possibly disclose all the features of Applicant's invention as recited in claim 1 including at least, "the dynamic decoupling capacitor being in communication with the logic circuitry via an internal activity signal of the logic circuitry at a gate or cell level," as amended herein.”. This argument is not persuasive and does not overcome the previous indicated prior art. As far as can be understood from the disclosure of Nuttgen, the dynamic decoupling/compensation network 150 injects a targeted total-charge amount I_COMP from a power source rail V_A into the regulated supply rail V_REG at node 130. This injected charge directly matches the dynamic charge I_SUP consumed by the inverter chains 134 and 146 during signal transitions. The switched-capacitor network 150 is controlled directly by the high-speed data inputs DATA_IN 132 and DATA_IN 140, which represent the internal cell-level activity signals driving the logic paths. Every time a transition happens in the digital path, a synchronous charge dump is executed by capacitors 158 and 166. By matching the total-charge injected with the total-charge drawn by the load, the instantaneous voltage droop on the internal regulated rail V_REG is effectively neutralized. This maintains a highly accurate, noise-free supply line for the sensitive high-speed digital path. There is no reference to the data_in being external to the circuit, therefore it is internal. The abstract discloses that the DATA_IN is “CMOS signal path coupled for receiving a data signal… The replica CMOS signal path receives an operating potential from the voltage regulator” and col 3 lines 15-18 describe DATA_IN as operating potential data “DATA IN propagates through successively larger series-coupled inverters or buffers 134, which receive positive operating potential from V.sub.REG and ground operating potential from power supply conductor or rail 138”. Therefore, the examiner does believe that the amended limitation of claim 1, “the dynamic decoupling capacitor being in communication with the logic circuitry via an internal activity signal of the logic circuitry at a gate or cell level," is taught in Nuttgen.
Regarding claim 5, applicant further argues on page 7 of Remarks “the rejection of Claim 5 is in error because Nuttgens fails to disclose … "discharging the dynamic decoupling capacitor to zero and simultaneously charging the logic circuitry," as amended”. This argument is persuasive. Therefore the rejection of the previous office action is withdrawn and allowable subject matter is described below.
Drawings
The drawings were received on 06/22/26. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Nuttgens (US 10790809 B1).
Regarding claim 1, Nuttgens discloses a circuitry system (fig 2, CMOS IC), comprising: a reservoir power rail (fig 2, power rail within charge pump circuit 150 providing I.sub.COMP to node 130 power supply rail); a regulated power rail (fig 2, power supply rail at node 130; col 3 lines 10-12 “node 130 to maintain a regulated output voltage V.sub.REG on node 130, operating as a power supply rail for inverters 134 and 146”); a logic circuitry connected to the regulated power rail (fig 2, CMOS signal path 100 including inverters 134 and 146 with connection to power supply rail at node 130); wherein each of the reservoir power rail, regulated power rail and logic circuitry is connected to respective voltage supply source (fig 2, see power supply conductor 128 operating at a positive potential V.sub.DD coupled to node 130 to maintain a regulated output voltage V.sub.REG on node 130; see power supply conductor 152 operating at a positive potential V.sub.A; CMOS signal path 100 including inverters 134 and 146 with connection to power supply rail at node 130 receive V.sub.REG); and a dynamic decoupling capacitor (fig 2, charge pump circuit capacitors 158 and 166 and decoupling capacitor 149) connecting the reservoir power rail to the regulated power rail (fig 2, see node 130, V.sub.REG, I.sub.COMP, and I.sub.SUP connection between power rail in charge pump circuit 150 and power supply rail at node 130), the dynamic decoupling capacitor being in communication with the logic circuitry (fig 2, see DATA_IN 132 and 140; col 3 lines 15-18) via an internal activity signal of the logic circuitry at a gate or cell level (fig 2, switched-capacitor network 150 is controlled directly by the high-speed data inputs DATA_IN 132 and DATA_IN 140, which represent the internal cell-level activity signals driving the logic paths where at a transition in the digital path, a synchronous charge dump is executed by capacitors 158 and 166); wherein the dynamic decoupling capacitor is configured to match a total-charge of injected-current, Idecap, from the reservoir power rail with a total-charge of load-current, Iload, supplying to the logic circuitry (col 4 lines 40+ the packet of charge introduced should be approximately equal to the charge Q consumed by CMOS signal path 100 to logic 134 and 146; col 5 line 40+ -col 6 line 4; charge pump 150 delivers a defined quantity of charge, current pulse I.sub.COMP, onto supply rail 130 at each transition of DATA IN and its complement; values of capacitor 158 and capacitor 166, as well as V.sub.A, are chosen such that the compensation packet of charge ΔQ, as delivered by charge pump 150, is approximately equal to the charge consumed from supply rail 130 by CMOS signal path 100 at each data transition I.sub.SUP delivered to logic).
Regarding claim 2, Nuttgens discloses the circuitry system as claimed in claim 1, wherein the dynamic decoupling capacitor comprises a charge-pump based architecture (fig 2, charge pump circuit 150 has charge pump architecture).
Regarding claim 3, Nuttgens discloses the circuitry system as claimed in claim 1, wherein the dynamic decoupling capacitor is scalable with the logic circuitry (col 5 lines 55+ to col 6 line 4, I.sub.COMP is scalable to equal I.sub.SUP to the logic 134 and 146; another implementation in fig 4 and explained col 7 lines 9-20 shows series inverters 236 and 240, with their load capacitances 238 and 242, represent a scaled-down replica of the CMOS signal path 100).
Regarding claim 4, Nuttgens discloses the circuitry system as claimed in claim 1, wherein the logic circuitry is a complementary metal oxide semiconductor logic circuitry (fig 2, logic 134 and 146; col 1 lines 12-16 “CMOS logic-style circuit elements”).
Allowable Subject Matter
Claims 5-6 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, Nuttgens discloses a method for regulating voltage in a circuitry system using a dynamic decoupling capacitor (see claim 1 above for relevant components in prior art Nuttgen) including a reservoir power rail; a regulated power rail; a logic circuitry connected to the regulated power rail; wherein each of the reservoir power rail, regulated power rail and logic circuitry is connected to respective voltage supply source; and a dynamic decoupling capacitor connecting the reservoir power rail to the regulated power rail, and in communication with the logic circuitry, wherein the dynamic decoupling capacitor is configured to match a total-charge of injected- current, Idecap from the reservoir power rail with a total-charge of load-current, load, supplying to the logic circuitry, the method comprising: detecting an incoming switching in logic circuitry (col 2 lines 51-56 “signal processing…data analysis or activity detection”); charging the dynamic decoupling capacitor from the reservoir power rail (fig 2, see Vsub.A input to charge pump circuit 150 including capacitors 158 and 166 and outputting I.sub.COMP to charge capacitor 149) and discharging the primary load of a logic circuitry (fig 2, see effective load capacitance 137 on output terminal 136, and effective load capacitance 148 on output terminal 144 from the logics 134 and 146); wherein the load-current’s charge-of-I.sub.load is identical to the charge-of-I.sub.decap (col 5 lines 55-59 I.sub.COMP is approximately equal to I.sub.SUP); wherein the charge-of- I.sub.load and charge-of- I.sub.decap refer to the integration of respective currents over time (fig 2, I.sub.COMP is injected onto the power rail at node 130 to compensate for each transition of the data signal over time, integrating I.sub.COMP with I.sub.SUP in CMOS signal path 100).
Nuttgen fails to disclose “discharging the dynamic decoupling capacitor to zero and simultaneously charging the logic circuitry”.
Nuttgen and Oh et al. (US 9153572 B1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “discharging the dynamic decoupling capacitor to zero and simultaneously charging the logic circuitry”.
Claim 6 is allowable for its dependency on allowable claim 5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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