DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 06/08/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 06/08/24.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
Fig 4 (a) should be labelled with components consistent with labeling in 4 (b) of elements VSS 16, VCCR 14, VCCS 12
Fig 4 (a) and (b) label 18 is missing from block with high-speed CMOS logic
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 line 3 “regulated supply source (14)” appears it should be replaced with “regulated supply source (16)” support for this change comes from fig 1 where respective voltage supply sources are all labelled VSS 16
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Nuttgens (US 10790809 B1).
Regarding claim 1, Nuttgens discloses a circuitry system (1) (fig 2, CMOS IC), comprising: a reservoir power rail (12) (fig 2, power rail within charge pump circuit 150 providing I.sub.COMP to node 130 power supply rail); a regulated power rail (14) (fig 2, power supply rail at node 130; col 3 lines 10-12 “node 130 to maintain a regulated output voltage V.sub.REG on node 130, operating as a power supply rail for inverters 134 and 146”); a logic circuitry (18) connected to the regulated power rail (14) (fig 2, CMOS signal path 100 including inverters 134 and 146 with connection to power supply rail at node 130); wherein each of the reservoir power rail (12), regulated power rail (14) and logic circuitry (18) is connected to respective voltage supply source (16) (fig 2, see power supply conductor 128 operating at a positive potential V.sub.DD coupled to node 130 to maintain a regulated output voltage V.sub.REG on node 130; see power supply conductor 152 operating at a positive potential V.sub.A; CMOS signal path 100 including inverters 134 and 146 with connection to power supply rail at node 130 receive V.sub.REG); characterized by a dynamic decoupling capacitor (10) (fig 2, charge pump circuit capacitors 158 and 166 and decoupling capacitor 149) connecting the reservoir power rail (12) to the regulated power rail (14) (fig 2, see node 130, V.sub.REG, I.sub.COMP, and I.sub.SUP connection between power rail in charge pump circuit 150 and power supply rail at node 130), and in communication with the logic circuitry (18) (fig 2, see DATA_IN 132 and 140); wherein the dynamic decoupling capacitor (10) is configured to match a total-charge of injected-current, Idecap, from the reservoir power rail (12) with a total-charge of load-current, Iload, supplying to the logic circuitry (18) (col 4 lines 40+ the packet of charge introduced should be approximately equal to the charge Q consumed by CMOS signal path 100 to logic 134 and 146; col 5 line 40+ -col 6 line 4; charge pump 150 delivers a defined quantity of charge, current pulse I.sub.COMP, onto supply rail 130 at each transition of DATA IN and its complement; values of capacitor 158 and capacitor 166, as well as V.sub.A, are chosen such that the compensation packet of charge ΔQ, as delivered by charge pump 150, is approximately equal to the charge consumed from supply rail 130 by CMOS signal path 100 at each data transition I.sub.SUP delivered to logic).
Regarding claim 2, Nuttgens discloses the circuitry system (1) as claimed in claim 1, wherein the dynamic decoupling capacitor (10) comprises a charge-pump based architecture (fig 2, charge pump circuit 150 has charge pump architecture).
Regarding claim 3, Nuttgens discloses the circuitry system (1) as claimed in claim 1, wherein the dynamic decoupling capacitor (10) is scalable with the logic circuitry (18) (col 5 lines 55+ to col 6 line 4, I.sub.COMP is scalable to equal I.sub.SUP to the logic 134 and 146; another implementation in fig 4 and explained col 7 lines 9-20 shows series inverters 236 and 240, with their load capacitances 238 and 242, represent a scaled-down replica of the CMOS signal path 100).
Regarding claim 4, Nuttgens discloses the circuitry system (1) as claimed in claim 1, wherein the logic circuitry (18) is a complementary metal oxide semiconductor logic circuitry (fig 2, logic 134 and 146; col 1 lines 12-16 “CMOS logic-style circuit elements”).
Regarding claim 5, Nuttgens discloses a method for regulating voltage in a circuitry system (1) using a dynamic decoupling capacitor (10) as claimed in claim 1, the method comprising the steps of: detecting an incoming switching in logic circuitry (18) (col 2 lines 51-56 “signal processing…data analysis or activity detection”); charging the dynamic decoupling capacitor (10) from the reservoir power rail (12) (fig 2, see Vsub.A input to charge pump circuit 150 including capacitors 158 and 166 and outputting I.sub.COMP to charge capacitor 149) and discharging the primary load of a logic circuitry (18) (fig 2, see effective load capacitance 137 on output terminal 136, and effective load capacitance 148 on output terminal 144 from the logics 134 and 146); and discharging the dynamic decoupling capacitor (10) to zero and simultaneously charging the logic circuitry (18) (col 4 lines 17-30 discharging capacitor 149 to provide supply current I.sub.SUP to logic via cmos signal path 100); wherein the load-current’s charge-of-I.sub.load is identical to the charge-of-I.sub.decap (col 5 lines 55-59 I.sub.COMP is approximately equal to I.sub.SUP); wherein the charge-of- I.sub.load and charge-of- I.sub.decap refer to the integration of respective currents over time (fig 2, I.sub.COMP is injected onto the power rail at node 130 to compensate for each transition of the data signal over time, integrating I.sub.COMP with I.sub.SUP in CMOS signal path 100).
Regarding claim 6, Nuttgens discloses the method as claimed in claim 5, wherein charging the dynamic decoupling capacitor (10) from a reservoir voltage supply source (16), which is separated from the regulated supply source (16) (see fig 2, V.sub.A 152 supply is separate from V.sub.DD supply 128).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838