DETAILED ACTION
1. Claims 1, 3-5, 8-18 and 21-22 are pending in this application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §102 and §103 (or as subject to pre-AIA 35 U.S.C. §102 and §103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
3. This office action is in response to applicant’s arguments filed on 02/10/2026 in response to the non-final rejection mailed on 11/10/2025. Claims 1 and 10 have been amended. Claims 3-5, 11-15, 17-18 and 21-22 have been previously presented. Claims 8-9 and 16 have been kept original. Claims 2, 6-7 and 19-20 have been cancelled. Amendment has been entered.
Response to Arguments
4. Applicant’s arguments, filed on 02/10/2026, with respect to the 35 U.S.C. § 101 Abstract Idea (Mental Process) rejection of claims 1, 3-5, 8-18 and 21-22 have been fully considered and are not persuasive (Applicant arguments, pages 10-12).
The rejection is based on 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG).
The Applicant argued that “These operations are tied to data storage buffers, buffer update timing, and circuitry, and therefore cannot be practically performed by a human mind.” The Examiner respectfully disagrees. A human is capable of observing, judging, or comparing strings; there is nothing inherently complex about these actions. It is also noted that the courts do not distinguish between claims that recite mental processes performed by humans and claims that recite mental processes performed on a computer. See MPEP 2106.04(a)(2)(III) – Mental Processes.
For those reasons, the U.S.C. § 101 Abstract Idea (Mental Process) rejection is upheld.
Applicant's arguments, filed on 02/10/2026, with respect to the rejection of claims 1, 3-5, 8-18 and 21-22 under 35 U.S.C. §103 (Applicant’s arguments, pages 12-17), have been fully considered and are but are moot because the independent claims are amended and introduce new limitations that were not previously presented newly found prior art has been applied.
Claim Rejections - 35 USC § 101
5. 35 U.S.C. §101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-5, 8-18 and 21-22 are rejected under 35 U.S.C. §101 because the claimed invention is directed to an abstract idea (Mental Process) without significantly more. The claims similarly recite steps to filter data.
The following is an analysis based on 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG).
Step 1, Statutory Category?
Claims 1, 3-5, 8-18 and 21-22 are directed to a string filter device (i.e. a system).
Therefore, claims 1, 3-5, 8-18 and 21-22 fall into at least one of the four statutory categories.
Step 2A, Prong I: Judicial Exception Recited?
The examiner submits that the foregoing claim limitations constitute a “Mental Process”, as the claims cover performance of the limitations in the human mind, given the broadest reasonable interpretation.
As per independent claim 1, the claim recites the limitations of:
“a string comparator group comprising a plurality of string comparators implemented in hardware architecture, wherein each of the plurality of string comparators compares, in parallel, each of the plurality of sub-string group data segments with query data, wherein the input storage buffer group including the data storage buffers includes: a data buffer group configured to store the plurality of string group data segments;” A human can visually inspect and compare different data segments to identify patterns, trends, and discrepancies. The string comparator group, hardware architecture and data buffer group are merely a component used to implement the abstract idea. There is nothing so complex in the limitation that could not be doing in the human mind.
“a data processing synchronizer configured to compare a number of string data segments remaining in the data buffer group when target data is extracted from the data buffer group and a number of offset data segments remaining in the offset buffer group when the target data is extracted from the offset buffer group, in a first cycle of the reference cycle, and to control a timing of update of the data buffer group and the offset buffer group, based on a comparison result to adjust synchronization between the data buffer group and the offset buffer group by selectively updating at least one of the data buffer group and the offset buffer group;” A human can observe data and compare them to determine changes to the data based on simple judgments of the observed data. A human can observe data, make judgments, and compare the data with other data to identify differences. A human can observe a data point that was determined to be new and mentally decide whether or not to update the previous data. A human can mentally visualize two strings, decide to update one in a few seconds, and then, a few seconds later, update the other one. The number of string data segments remaining when target data is extracted from the data buffer group and the number of offset data segments remaining when the target data is extracted from the offset buffer group in a first cycle of the reference cycle are merely components or tools used to facilitate the mental processes described above. There is nothing so complex in the limitation that could not be doing in the human mind.
As per dependent claim 8, the claim recites the additional limitation of:
“wherein the first size is determined based on a bandwidth of a channel through which the string group data segments are received.” A human can observe the bandwidth of the channel through which the string group data segments are transmitted and determine their sizes. There is nothing so complex in the limitation that could not be doing in the human mind.
As per dependent claim 9, the claim recites the additional limitation of:
“wherein the second size is determined based on a maximum query data size which the string comparator group can process.” A human can observe the maximum query data size that the string comparator group can handle and determine the sizes of the data segments. There is nothing so complex in the limitation that could not be doing in the human mind.
As per independent claim 10, the claim recites the limitations of:
“a data processing synchronizer configured to compare a number of string data segments remaining in the data storage buffer group when target data is extracted from the data storage buffer group and a number of offset data segments remaining in the offset storage buffer group when the target data is extracted from the offset storage buffer group, in a first cycle of the reference cycle, and to determine whether to update each of the data storage buffer group and the offset storage buffer group, based on a comparison result to adjust synchronization between the data storage buffer group and the offset storage buffer group;” A human can observe data and compare them to determine changes to the data based on simple judgments of the observed data. A human can observe data, make judgments, and compare the data with other data to identify differences. A human can observe a data point that was determined to be new and mentally decide whether or not to update the previous data. The number of string data segments remaining when target data is extracted from the data buffer group and the number of offset data segments remaining when the target data is extracted from the offset buffer group in a first cycle of the reference cycle are merely components or tools used to facilitate the mental processes described above. There is nothing so complex in the limitation that could not be doing in the human mind.
“a string comparator group comprising a plurality of string comparators implemented in hardware architecture, which is configured to receive, from the data storage buffer group, a plurality of sub-string group data segments extracted from the plurality of string group data segments, and generate each comparison result to compare whether each of the plurality of sub-string group data segments comprises query data;” A human can visually inspect and compare different data segments to identify patterns, trends, and discrepancies. The string comparator group, plurality of string comparators, hardware architecture, data storage buffer group, and plurality of sub-string group data segments are merely a component used to implement the abstract idea. There is nothing so complex in the limitation that could not be doing in the human mind.
As per dependent claim 16, the claim recites the additional limitation of:
“wherein the fixed size is determined based on a bandwidth of a channel through which the string group data is received to be synchronized with the reference cycle.” A human can observe the bandwidth of the channel through which the string group data segments are transmitted and determine their sizes. There is nothing so complex in the limitation that could not be doing in the human mind.
As per dependent claim 18, the claim recites the additional limitation of:
“wherein the offset buffer storage group determines a number of the plurality of offset data segments received to be synchronized with the reference cycle, based on the fixed size of the string group data and the predetermined size of the plurality of offset data segments.” A human can manually examine the data and count the distinct segments within it. There is nothing so complex in the limitation that could not be doing in the human mind.
As per dependent claims 21 and 22, the claims recite the additional limitation of:
“wherein the validity data includes a bit value determined based on a comparison between previous offset data and current offset data.” A human can observe data, make judgments, and compare the data with other data to validate it. There is nothing so complex in the limitation that could not be doing in the human mind.
Accordingly, claims 1, 3-5, 8-18 and 21-22 recite at least one abstract idea.
Step 2A, Prong II: Integrated into a Practical Application?
The claims recite the following additional limitations/elements:
As per independent claims 1 and 10, the claims recite the additional limitations of:
“a string comparator group comprising a plurality of string comparators implemented in hardware architecture” The hardware architecture, as stated in the limitation, is used to implement the abstract ideas identified in the claims. This element “hardware architecture” is example of mere instruction to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea (see MPEP § 2106.05(f)). Specifically, the additional elements of the limitations invoke computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general-purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) do not provide improvements to the functioning of a computer or to any other technology or technical field; and do not integrate a judicial exception into a practical application.
As per claim 1, the claim recites the additional limitations of:
“an input storage buffer group including data storage buffers configured to store a plurality of string group data segments, each of the plurality of string group data segments having a first size and including a plurality of string data segments having a variable size, and to output a plurality of sub-string group data segments having a second size formed by shifting characters on a character-by-character in each of the plurality of the string group data segments;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering, without any further processing or analysis.
The input buffer group, the plurality of string group data segments having a first size, and the plurality of string data segments having a variable size are merely components or tools used to facilitate the mental processes described above.
“a data buffer group configured to store the plurality of string group data segments;” Herein considering the element store the plurality of string group data segments of the whole limitation. This element is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering, without any further processing or analysis.
“an offset buffer group configured to receive and output offset data indicating a start position of the plurality of string data segments;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering, without any further processing or analysis.
The offset buffer group, input storage buffer group, data storage buffers and start position of the plurality of string data segments are merely component or tools used to facilitate the mental processes described above.
“a result processor comprising circuitry configured to output target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The result processor is a merely component or tools used to facilitate the mental processes described above.
As per dependent claim 3, the claim recites the additional limitations of:
“wherein the data buffer group includes: a first data buffer configured to receive the plurality of string group data segments to be synchronized with a reference cycle, and output a portion of string group data segments of a first cycle and string group data segments of a second cycle during the reference cycle;;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The first data buffer, and reference cycle are merely components or tools used to facilitate the mental processes described above.
“a second data buffer configured to output a plurality of sub-string group data segments having the second size to shift character by character from the portion of string group data segments of the first cycle and string group data segments of the second cycle during the reference cycle.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The second data buffer, portion of string group data segments of a first cycle, and string group data segments of a second cycle during the reference cycle are merely components or tools used to facilitate the mental processes described above.
As per dependent claim 4, the claim recites the additional limitations of:
“wherein the offset buffer group includes: a first offset buffer configured to receive the offset data to be synchronized with a reference cycle, and output a portion of offset data segments of a first cycle during the reference cycle and offset data segments of a second cycle during the reference cycle;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The first offset buffer, and reference cycle are merely components or tools used to facilitate the mental processes described above.
“a second offset buffer configured to output data comprising the portion of offset data segments of the first cycle and offset data segments of the second cycle during one cycle.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The second offset buffer, portion of offset data segments of a first cycle and offset data segments of a second cycle during the reference cycle are merely components or tools used to facilitate the mental processes described above.
As per dependent claim 5, the claim recites the additional limitations of:
“wherein the validity buffer group includes: a first validity buffer configured to receive the validity data to be synchronized with a reference cycle, and output the validity data;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The first validity buffer, and reference cycle are merely components or tools used to facilitate the mental processes described above.
“a second validity buffer configured to receive the validity data from the first validity buffer, and output the validity data divided into smaller units to be matched one-to-one to the offset data for each cycle.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The second validity buffer is a merely components or tools used to facilitate the mental processes described above.
As per claim 10, the claim recites the additional limitations of:
“a data storage buffer group including data storage buffers configured to receive and output a plurality of string group data segments having a fixed size to be synchronized with a reference cycle, each of the plurality of string group data segments including a plurality of string data segments having a variable size;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The input buffer group, plurality of string group data segments having a fixed size, reference cycle, and plurality of string data segments having a variable size are merely components or tools used to facilitate the mental processes described above.
“an offset storage buffer group including offset storage buffers configured to receive and output a plurality of offset data segments indicating a start position of each of the plurality of string data segments to be synchronized with the reference cycle;” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The offset buffer group, plurality of offset data segments, and start position of each of the plurality of string data segments are merely components or tools used to facilitate the mental processes described above.
“a string comparator group comprising a plurality of string comparators implemented in hardware architecture, which is configured to receive, from the data storage buffer group, a plurality of sub-string group data segments extracted from the plurality of string group data segments, and generate each comparison result to compare whether each of the plurality of sub-string group data segments comprises query data;” Considering the element “receive …” of the limitation this is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
“a result processor comprising circuitry configured to output target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The result processor is a merely component or tools used to facilitate the mental processes described above.
As per dependent claim 11, the claim recites the additional limitations of:
“further comprising: wherein offset data used when the target data is extracted among the plurality of offset data segments and string data corresponding to the offset data segments used when the target data is extracted are output from the data storage buffer group and the offset storage buffer group in the first cycle.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claim 12, the claim recites the additional limitations of:
“wherein the synchronizer updates at least one of the data storage buffer group and the offset storage buffer group, based on the comparison result of the number of remaining string data segments and the number of remaining offset data segments, and wherein, in the updated at least one of the data storage buffer group, data of a second cycle as a next cycle of the first cycle is used when the target data is extracted.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claim 13, the claim recites the additional limitations of:
“wherein the synchronizer updates the data storage buffer group when the number of remaining string data segments is less than the number of remaining offset data segments.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claim 14, the claim recites the additional limitations of:
“wherein the synchronizer updates the data storage buffer group and the offset storage buffer group when the number of remaining string data segments is equal to the number of remaining offset data segments.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claim 15, the claim recites the additional limitations of:
“wherein the synchronizer updates the offset storage buffer group when the number of remaining string data segments is greater than the number of remaining offset data segments.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claim 17, the claim recites the additional limitations of:
“wherein the offset storage buffer group receives and outputs stores the plurality of offset data segments equally having a predetermined size to be synchronized with the reference cycle.” This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
As per dependent claims 21 and 22, the claims recite the additional limitation of:
“wherein the input storage buffer group further includes a validity buffer group configured to receive and output validity data indicating validity of the offset data.” The elements' reception and output of validity data based on the specification is nothing more than the reception and transmission of that data. This limitation is example of adding insignificant extra-solution activity to the judicial exception (see MPEP § 2106.05(g)). Specifically, the additional limitation exemplifies mere data gathering and transmission, without any further processing or analysis.
The validity buffer group, and plurality of validity data segments are merely components or tools used to facilitate the mental processes described above.
Therefore, claims 1, 3-5, 8-18 and 21-22 do not integrate the recited abstract ideas into a practical application.
Step 2B: Claim provides an Inventive Concept?
With respect to the limitations identified as insignificant extra-solution activity above the conclusions are carried over, and both the “store …; extract …; receive …; and output ….” are well-understood, routine, and conventional operations.
For support as being well-understood, routine, and conventional for “ store …; extract …; receive …; and output ….” as noted by the courts is well understood routine and conventional, see MPEP 2106.05(d)(ii) “i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); … buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);” and/or MPEP 2106.05(d)(ii) “iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;”, and/or MPEP 2106.05(d)(II) “iii. Ultramercial, 772 F.3d at 716, 112 USPQ2d at 1755 (updating an activity log);” See also [Display Interface - an overview | ScienceDirect Topics, Introducing ASP.NET Web Pages - Displaying Data | Microsoft Docs, Execute DBCC PAGE command to Display Contents of Data Pages in SQL Server (kodyaz.com) and Load and display paged data | Android Developers].
Looking at the limitations in combination and the claim as a whole does not change this conclusion and the claim is ineligible.
Therefore, the claims 1, 3-5, 8-18 and 21-22 are not patent eligible.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. § 102 and § 103 (or as subject to pre-AIA 35 U.S.C. § 102 and § 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section § 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. § 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 3-5, 9-14 and 21-22 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim et al. (US 20110055130 A1) in view of Chemparathy et al. (US 10672098 B1) in further view of Chandhoke (US 20130080661 A1).
As per claim 1, Kim teaches a string filter device (i.e. “a string matching device”; fig. 1, para. [0040]) comprising:
an input storage buffer group including data storage buffers configured to (i.e. “an input buffer 101”; fig. 1, para. [0040]. Further, i.e. Referring to FIG. 2, the respective columns of Phase 1, Phase 2, and Phase 3 represent output data of the input buffer 101, and input data and output data of the distributor 103 in the corresponding stage.”; fig. 2, para. [0060]-[0061]; Examiner note: the input storage buffer group is interpreted as the input buffer 101. The data storage buffers are considered as the respective columns of Phase 1, Phase 2, and Phase 3 which forms a buffer group)
store a plurality of string group data segments (i.e. “the memory 104 divides the corresponding string into sub-strings with the size that is less than N and stores them.”; para. [0052]. Further, i.e. “when the data stream input to the input buffer 101 is “XYABCDEFGHMNQROP ...,” the comparator 105 can detect the fourth strings corresponding to the sub-strings “ABCD,” “EFGH,” “GHMN,” and “QR”.”; para. [0058], [0066]; Examiner note: the plurality of string group data segments is interrupted as the “XYABCDEFGHMNQROP ...”),
each of the plurality of string group data segments having a first size (i.e. “when the size of the string to be detected is L and L is greater than the size of the first string that is N, the memory 104 divides the corresponding string into sub-strings with the size that is less than N and stores them.”; para. [0047], [0052]); Examiner note: the first size is interpreted as the size of the string to be detected is L)
and including a plurality of string data segments having a variable size (i.e. “the target strings are "ABCDEFGHMNS," "EFGHMNOP," and "GHMNQR," the size N of the first string output by the input buffer 101 is 4”; para. [0058]; Examiner note: the plurality of string data segments is interpreted as the “ABCDEFGHMNS,” “EFGHMNOP,” and “GHMNQR,”; Examiner note: the variable size is interpreted as the size N of the first string output by the input buffer 101 is 4; where N is the variable and 4 is the size of N),
and to output a plurality of sub-string group data segments (i.e. “plurality of the fourth strings output by distributor 103 correspond to the at least one sub-string stored in the memory 104”; figs. 4, para. [0054]-[0055])
having a second size (i.e. “when the size of the string to be detected is L and L is greater than the size of the first string that is N, the memory 104 divides the corresponding string into sub-strings with the size that is less than N and stores them.”; fig. 4, para. [0052], [0058], [0064]; Examiner note: the second size is interpreted as the L is greater than the size of the first string that is N)
formed by shifting characters on a character-by-character in each of the plurality of the string group data segments (i.e. “Accordingly, the distributor 103 shifts the offset by each character in the third string, and extracts the fourth string. Hence, the fourth string may share at least one character with another fourth string.”; Abstract, fig. 7, para. [0051]);
a string comparator group comprising a plurality of string comparators (i.e. “the string matching device 100 includes an input buffer 101, a delay buffer 102, a distributor 103, a memory 104, a comparator”; fig.1, para. [0040]. Further, i.e. “plurality of comparators 2002-1, 2002-2, . . ., 2002-N.”; fig.6, para. [0086])
implemented in hardware architecture (i.e. “Referring to FIG. 9, the string matching device 300 includes an input buffer 301, a delay buffer 302, a distributor 303, a memory 304, a first comparator 305, an offset controller 306, an offset selector 307, a second comparator 308, a concatenation circuit 309, and an encoding circuit 310.”; fig. 9, para. [0114]-[0119]; Examiner note: the hardware architecture is interpreted as the architecture string matching device illustrated in fig. 9),
wherein each of the plurality of string comparators compares (i.e. “a first comparator 305 and a second comparator 308”; figs. 6, 9, para. [0086], [0116]),
in parallel, each of the plurality of sub-string group data segments with query data (i.e. “The entries 204-1, 204-2, ..., 204-P simultaneously compare the sub-string stored in the corresponding memory 2001 and a plurality of fourth strings by using the comparators 2002-1, 2002-2, ... , 2002-N that are classified by the offset, and when the fourth string corresponds to the sub-string, the same output detection signals for indicating that a corresponding sub-string is detected (S205).”; figs. 6, 8-9, 12-13, para. [0086], [0111], [0119], [0123]),
wherein the input storage buffer group including the data storage buffers includes (i.e. “Referring to FIG. 2, the respective columns of Phase 1, Phase 2, and Phase 3 represent output data of the input buffer 101, and input data and output data of the distributor 103 in the corresponding stage.”; figs. 2, 16, para. [0060]-[0061]):
a data buffer group configured to store the plurality of string group data segments (i.e. “an input buffer 101”; fig. 1, para. [0040]. Further, i.e. Referring to FIG. 2, the respective columns of Phase 1, Phase 2, and Phase 3 represent output data of the input buffer 101, and input data and output data of the distributor 103 in the corresponding stage.”; fig. 2, para. [0060]-[0061]; Examiner note: the data buffer group is interpreted as the respective columns of Phase 1, Phase 2, and Phase 3);
an offset buffer group configured to receive and output offset data indicating a start position of the plurality of string data segments (i.e. “the distributor 103 generates and outputs the fourth strings “XYAB,” “YABC,” “ABCD,” and “BCDE” from the third string “XYABCDEF” with different offsets. Here, ”XYAB” is positioned on the offset 0, ”YABC” on the offset 1, ”ABCD” on the offset 2, and ”BCDE” on the offset 3.”; fig. 2, para. [0060], [0064], [0067]; Examiner note: the offset buffer group is interpreted as the offsets; the start position of the plurality of string data segments is interpreted as the "XYAB" is positioned on the offset 0. Further, i.e. “upon receiving the sub-string index 1 from the sub-string processor 606, the state transition processor 608 outputs the corresponding next state value (P+1) as a state variable”; para. [0303]; Examiner note: The receive and output offset data is interpreted as the receiving the sub-string index 1 from the sub-string processor 606, the state transition processor 608 outputs);
a result processor comprising circuitry (i.e. “the encoding circuit 107 outputs a string ID that corresponds to “GHMNQR.”; fig. 5, para. [0068]-[0069])
configured to output the target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments (i.e. “when the string ID's 1, 2, and 3 are given to “ABCDEFGHMNS,” “EFGHMNOP,” and “GHMNQR,” respectively, the encoding circuit 107 outputs 3 which is the string ID of “GHMNQR.”; para. [0068]-[0070]; Examiner note: the output target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments is interpreted as the encoding circuit 107 outputs 3 which is the string ID of “GHMNQR.”).
However, it is noted that the prior art of Kim does not explicitly teach “a data processing synchronizer configured to compare a number of string data segments remaining in the data buffer group when target data is extracted from the data buffer group and a number of offset data segments remaining in the offset buffer group when the target data is extracted from the offset buffer group, in a first cycle of the reference cycle, and to control a timing of update of the data buffer group and the offset buffer group, based on a comparison result to adjust synchronization between the data buffer group and the offset buffer group by selectively updating at least one of the data buffer group and the offset buffer group;”
On the other hand, in the same field of endeavor, Chemparathy teaches a data processing synchronizer (i.e. “synchronizer 110”; figs. 1-2, Col. 10, Lines 1-6; Examiner note: the data processing synchronizer is interpreted as the synchronizer 110)
configured to compare a number of string data segments remaining in the data buffer group when target data is extracted from the data buffer group and a number of offset data segments remaining in the offset buffer group when the target data is extracted from the offset buffer group in a first cycle of the reference cycle (i.e. “At 204, synchronizer 110 may compare the current extent of buffered video information or data buffered in a frame buffer 114 with the subset amount to be extracted at a time for a read cycle by a consumer device, such as encoder circuit 106, to determine a difference.”; fig. 2, Col. 10, Lines 33-42; Examiner notes: the number of string data segments remaining is interpreted as the current extent of buffered video information; the number of offset data segments remaining is interpreted as the data buffered in a frame buffer; the first cycle of the reference cycle is interpreted as the read cycle);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC into Kim that teaches string matching. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation for doing so would be to share a buffer between users' devices because it can avoid pipelines and improve performance (Chemparathy, Column 13, Lines 29-56).
However, it is noted that the prior art of Kim and Chemparathy does not explicitly teach “to control a timing of update of the data buffer group and the offset buffer group, based on a comparison result to adjust synchronization between the data buffer group and the offset buffer group by selectively updating at least one of the data buffer group and the offset buffer group;”
On the other hand, in the same field of endeavor, Chandhoke teaches to control a timing of update of the data buffer group and the offset buffer group (i.e. “configuring buffers with timing information”; fig.2, para. [0011]. Further, i.e. “The time offset may specify the precise “relative time” within the period when the data transfer is triggered. As mentioned before, this time period may allow for coordination of reading and writing the data to ensure minimum age as well as flexible scheduling options.”; para. [0080]; Examiner note: the control a timing is interpreted as the specify the precise “relative time” within the period. The update is interpreted as the configuring),
based on a comparison result to adjust synchronization between the data buffer group and the offset buffer group (i.e. “this common time base or clock may allow the producer target and the consumer target to synchronize their application loops based on period and time offset specified on the buffer. Global time synchronization can be achieved by many means using signal based or time based clock synchronization.”; para. [0078]; Examiner note: the based on a comparison result is the based on period and time offset specified on the buffer. The adjust synchronization in interpreted as the synchronization can be achieved)
by selectively updating at least one of the data buffer group and the offset buffer group (i.e. “In the example of FIG. 3, the two time sensitive buffers are configured with pre-defined fixed size of a heterogeneous set of data (specified from the nodes “Isoc Output” and “Isoc Input” to the respective “data” terminals of the buffers)”; fig.3, para. [0080]; Examiner note: the selectively updating at least one of the data buffer group and the offset buffer group is interpreted as the two time sensitive buffers are configured with pre-defined fixed size of a heterogeneous set of data);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chandhoke that teaches configuring buffers with timing information into the combination of the prior arts of Kim that teaches string matching, and Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation for doing so would be to control the loop cycle in the buffer, as it improves the application program's consumption of isochronous data (Chandhoke, para. [0003]).
As per claim 3, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 1 above.
Additionally, Kim teaches wherein the data buffer group includes: a first data buffer (i.e. “the input buffer 101 arranges the input data stream of Phase 1 by 4 bytes and sequentially outputs the first string.”; fig. 2, para. [0061]; Examiner note: the first data buffer is interpreted as the input data stream of Phase 1)
configured to receive the plurality of string group data segments to be synchronized with a reference cycle (i.e. “The delay buffer 102 delays the first string output by the input buffer 101 by 1 clock signal, and outputs the second string. Therefore, the first string and the second string are input to the distributor 103 by 8 bytes in a like manner of Phase 2, and are used to generate the third string.”; fig. 2, para. [0061]; Examiner note: the reference cycle is interpreted as the1 clock signal; the first and second strings are data of the Phases, see fig. 2), and
output a portion of string group data segments of a first cycle and string group data segments of a second cycle during the reference cycle (i.e. “when the input buffer 101 outputs the first string "CDEF," the delay buffer 102 outputs "XYAB" output by the input buffer 101 by 1 clock signal in advance as the second string.”; fig. 2, para. [0062]; Examiner note: the portion of string group data segments of the first cycle is interpreted as the "CDEF,"); and
a second data buffer (i.e. “Therefore, the first string and the second string are input to the distributor 103 by 8 bytes in a like manner of Phase 2, and are used to generate the third string.”; fig. 2, para. [0061]; Examiner note: the second data buffer is interpreted as the Phase 2, see fig. 2) configured to
output a plurality of sub-string group data segments (i.e. “plurality of the fourth strings output by distributor 103 correspond to the at least one sub-string stored in the memory 104”; para. [0054]
having the second size (i.e. “when the size of the string /o be detected is L and L is greater than the size of the first string that is N, the memory 104 divides the corresponding string into sub-strings with the size that is less than N and stores them.”; para. [0052]; Examiner note: the second size is interpreted as the L is greater than the size of the first string that is N),
to shift character by character from the portion of string group data segments of the first cycle (i.e. “Accordingly, the distributor 103 shifts the offset by each character in the third string, and extracts the fourth string. Hence, the fourth string may share at least one character with another fourth string.”; para. [0051]); and
string group data segments of the second cycle during the reference cycle (i.e. “when the input buffer 101 outputs the first string "CDEF," the delay buffer 102 outputs "XYAB" output by the input buffer 101 by 1 clock signal in advance as the second string.”; fig. 2, para. [0062]; Examiner note: the string group data segments of the second cycle is interpreted as the "XYAB" output, see fig. 2).
As per claim 4, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 1 above.
Additionally, Kim teaches wherein the offset buffer group includes: a first offset buffer (i.e. “the input buffer 101 arranges the input data stream of Phase 1 by 4 bytes and sequentially outputs the first string.”; fig. 2, para. [0061]; Examiner note: the first data buffer is interpreted as the input data stream of Phase 1)
configured to receive the offset data to be synchronized with a reference cycle (i.e. “The delay buffer 102 delays the first string output by the input buffer 101 by 1 clock signal, and outputs the second string.”; fig. 2, para. [0061]; Examiner note: the reference cycle is interpreted as the1 clock signal; the outputs in each Phase correspond strings stored in the offset(s), see fig. 2), and
output a portion of offset data segments of a first cycle during the reference cycle and offset data segments of a second cycle during the reference cycle (i.e. “when the input buffer 101 outputs the first string "CDEF," the delay buffer 102 outputs "XYAB" output by the input buffer 101 by 1 clock signal in advance as the second string.”; fig. 2, para. [0062]; Examiner note: the portion of string group data segments of the first cycle is interpreted as the "CDEF,"); and
a second offset buffer configured to (i.e. “Therefore, the first string and the second string are input to the distributor 103 by 8 bytes in a like manner of Phase 2, and are used to generate the third string.”; fig. 2, para. [0061]; Examiner note: the second data buffer is interpreted as the Phase 2, see fig. 2)
output data comprising the portion of offset data segments of the first cycle and offset data segments of the second cycle during one cycle (i.e. “when the input buffer 101 outputs the first string "CDEF," the delay buffer 102 outputs "XYAB" output by the input buffer 101 by 1 clock signal in advance as the second string.”; fig. 2, para. [0062]; Examiner note: the portion of offset data segments of a first cycle and offset data segments of a second cycle during the reference cycle is interpreted as the "XYAB", see fig. 2).
As per claim 5, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 21 above.
Additionally, Kim teaches wherein the validity buffer group includes: a first validity buffer configured to receive the validity data to be synchronized with a reference cycle, and output the validity data (i.e. “when en.sub.1 is "1" in the second multiplexer 1004-1 of the first stage, the signal output by the flipflop 1002-1 of the first stage is input to the AND gate 1001-2 of the second stage.”; fig. 3, para. [0071]-[0073]; Examiner note: the first validity buffer is interpreted as the when en.sub.1 is "1"; the reference cycle is interpreted as the first stage; the store the validity data is interpreted as the signal output by the flipflop 1002-1 of the first stage is input to the AND gate 1001-2 of the second stage); and
a second validity buffer configured to receive the validity data from the first validity buffer (i.e. “On the contrary, when en.sub.1 is "0," the signal output by the flipflop 1002-1 of the first stage is not transmitted to the AND gate 1001-2 of the second stage.”; para. [0073]-[0077]; Examiner note: the second validity buffer is interpreted as the when en.sub.1 is "0,"), and
output the validity data divided into smaller units to be matched one-to-one to the offset data for each cycle (i.e. “Therefore, the concatenation circuit 106 is divided into a plurality of sub-concatenation circuits or is connected to be operable by the control signals en.sub.1, en.sub.2, . . . , en.sub.M.”; fig. 3, para. [0073]-[0077]; Examiner note: the store the validity data divided to be matched one-to-one to the offset data is interpreted as the concatenation circuit 106 is divided into a plurality of sub-concatenation circuits or is connected to be operable by the control signals en.sub.1, en.sub.2, . . . , en.sub.M).
As per claim 9, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 1 above.
Additionally, Kim teaches wherein the second size is determined based on a maximum query data size which the string comparator group can process (i.e. “when the size of the string included in the string stream is N, the input buffer 101 generates a string stream from the input data stream, temporarily stores the same, and outputs a string with the size N for each clock signal.”; para. [0042], [0078]; Examiner note: the maximum query data size which the string comparator group can process is interpreted as the string stream is N).
As per claim 10, Kim teaches a string filter device (i.e. “a string matching device”; fig. 1, para. [0040]) comprising:
a data storage buffer group including data storage buffers configured to (i.e. “an input buffer 101”; fig. 1, para. [0040]. Further, i.e. Referring to FIG. 2, the respective columns of Phase 1, Phase 2, and Phase 3 represent output data of the input buffer 101, and input data and output data of the distributor 103 in the corresponding stage.”; fig. 2, para. [0060]-[0061]; Examiner note: the input storage buffer group is interpreted as the input buffer 101. The data storage buffers are considered as the respective columns of Phase 1, Phase 2, and Phase 3 which forms a buffer group)
receive and output a plurality of string group data segments (i.e. “when the data stream input to the input buffer 101 is “XYABCDEFGHMNQROP . . .,” the comparator 105 can detect the fourth strings corresponding to the sub-strings “ABCD,” “EFGH,” “GHMN,” and “QR”.”; para. [0058], [0066]; Examiner note: the plurality of string group data segments is interrupted as the “XYABCDEFGHMNQROP . . .,”)
having a fixed size (i.e. “when the length of the target string is L and the size of the first string output by the input buffer 201 is N”; fig. 6, para. [0047], [0087])
to be synchronized with a reference cycle (i.e. “The delay buffer 102 delays the first string output by the input buffer 101 by 1 clock signal, and outputs the second string. Therefore, the first string and the second string are input to the distributor 103 by 8 bytes in a like manner of Phase 2, and are used to generate the third string.”; fig. 2, para. [0061]; Examiner note: the reference cycle is interpreted as the1 clock signal),
each of the plurality of string group data segments including a plurality of string data segments having a variable size (i.e. “the target strings are "ABCDEFGHMNS," "EFGHMNOP," and "GHMNQR," the size N of the first string output by the input buffer 101 is 4”; para. [0058]; Examiner note: the plurality of string data segments is interpreted as the "ABCDEFGHMNS," "EFGHMNOP," and "GHMNQR,"; the variable size is interpreted as the size N of the first string output by the input buffer 101 is 4; where N is the variable and 4 is the size of N);
an offset storage buffer group including offset storage buffers configured to receive and output a plurality of offset data segments (i.e. “Here, "XYAB" is positioned on the offset 0, "YABC" on the offset 1, "ABCD" on the offset 2, and "BCDE" on the offset 3.”; fig. 2, para. [0060], [0064], [0067]; Examiner note: the offset storage buffer group is interpreted as the offsets)
indicating a start position of each of the plurality of string data segments to be synchronized with the reference cycle (i.e. “Here, "XYAB" is positioned on the offset 0, "YABC" on the offset 1, "ABCD" on the offset 2, and "BCDE" on the offset 3.”; fig. 2, para. [0060], [0064], [0067]; Examiner note: the start position of each of the plurality of string data segments to be synchronized with the reference cycle is interpreted as the "XYAB" is positioned on the offset 0);
a string comparator group comprising a plurality of string comparators (i.e. “the string matching device 100 includes an input buffer 101, a delay buffer 102, a distributor 103, a memory 104, a comparator”; fig.1, para. [0040]. Further, i.e. “plurality of comparators 2002-1, 2002-2, . . ., 2002-N.”; fig.6, para. [0086])
implemented in hardware architecture (i.e. “Referring to FIG. 9, the string matching device 300 includes an input buffer 301, a delay buffer 302, a distributor 303, a memory 304, a first comparator 305, an offset controller 306, an offset selector 307, a second comparator 308, a concatenation circuit 309, and an encoding circuit 310.”; fig. 9, para. [0114]-[0119]; Examiner note: the hardware architecture is interpreted as the architecture string matching device illustrated in fig. 9),
which is configured to receive (i.e. “The state transition processor 408 receives the index 1 from the path selector 407, and outputs the next state value 1 corresponding to the index 1 as the state variable.”; figs. 4, 6, para. [0189]-[0190]),
from the data storage buffer group (i.e. “Referring /o FIG. 2, the respective columns of Phase 1, Phase 2, and Phase 3 represent output data of the input buffer 101, and input data and output data of the distributor 103 in the corresponding stage.”; fig. 2, para. [0060]-[0061]; Examiner note: the data storage buffer group is interpreted as the respective columns of Phase 1, Phase 2, and Phase 3),
a plurality of sub-string group data segments extracted from the plurality of string group data segments (i.e. “when the string to be detected is “ABCDEFGHMNS,” the string is divided into “ABCD,” “EFGH,” and “MNS,” which are stored in the memory 104.”; para. [0053]; Examiner note: the extract a plurality of sub-string group data segments is interpreted as the string is divided into “ABCD,” “EFGH,” and “MNS,”), and
generate each comparison result to compare whether each of the plurality of sub-string group data segments comprises query data (i.e. “The fourth strings “XYAB,” “YABC,” “ABCD,” and “BCDE” are simultaneously compared to the sub-strings “ABCD,” “EFGH,” . . ., “QR” stored in the memory 104 by the comparator 105. Each time a sub-string is detected from among the fourth string, the comparator 105 outputs a detection signal for indicating detection of a sub-string.”; figs. 4-6, para. [0065]); and
a result processor comprising circuitry (i.e. “the encoding circuit 107 outputs a string ID that corresponds to “GHMNQR.”; fig. 5, para. [0068]-[0069])
configured to output the target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments (i.e. “when the string ID's 1, 2, and 3 are given to “ABCDEFGHMNS,” “EFGHMNOP,” and “GHMNQR,” respectively, the encoding circuit 107 outputs 3 which is the string ID of “GHMNQR.”; para. [0068]-[0070]; Examiner note: the output target data matched to the query data, based on the comparison result received from the string comparator group and the plurality of offset data segments is interpreted as the encoding circuit 107 outputs 3 which is the string ID of “GHMNQR.”).
However, it is noted that the prior art of Kim does not explicitly teach “a data processing synchronizer configured to compare a number of string data segments remaining in the data storage buffer group when target data is extracted from the data storage buffer group and a number of offset data segments remaining in the offset storage buffer group when the target data is extracted from the offset storage buffer group, in a first cycle of the reference cycle, and to control a timing of update of the data storage buffer group and the offset storage buffer group, based on a comparison result to adjust synchronization between the data storage buffer group and the offset storage buffer group by selectively updating at least one of the data storage buffer group and the offset storage buffer group;”
On the other hand, in the same field of endeavor, Chemparathy teaches a data processing synchronizer (i.e. “synchronizer 110”; figs. 1-2, Col. 10, Lines 1-6; Examiner note: the data processing synchronizer is interpreted as the synchronizer 110)
configured to compare a number of string data segments remaining in the data storage buffer group when target data is extracted from the data storage buffer group and a number of offset data segments remaining in the offset storage buffer group when the target data is extracted from the offset storage buffer group, in a first cycle of the reference cycle (i.e. “At 204, synchronizer 110 may compare the current extent of buffered video information or data buffered in a frame buffer 114 with the subset amount to be extracted at a time for a read cycle by a consumer device, such as encoder circuit 106, to determine a difference.”; fig. 2, Col. 10, Lines 33-42; Examiner notes: the number of string data segments remaining is interpreted as the current extent of buffered video information; the number of offset data segments remaining is interpreted as the data buffered in a frame buffer; the first cycle of the reference cycle is interpreted as the read cycle);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC into Kim that teaches string matching. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation for doing so would be to share a buffer between users' devices because it can avoid pipelines and improve performance (Chemparathy, Column 13, Lines 29-56).
However, it is noted that the prior art of Kim and Chemparathy does not explicitly teach “to control a timing of update of the data storage buffer group and the offset storage buffer group, based on a comparison result to adjust synchronization between the data storage buffer group and the offset storage buffer group by selectively updating at least one of the data storage buffer group and the offset storage buffer group;”
On the other hand, in the same field of endeavor, Chandhoke teaches to control a timing of update of the data storage buffer group and the offset storage buffer group (i.e. “configuring buffers with timing information”; fig.2, para. [0011]. Further, i.e. “The time offset may specify the precise “relative time” within the period when the data transfer is triggered. As mentioned before, this time period may allow for coordination of reading and writing the data to ensure minimum age as well as flexible scheduling options.”; para. [0080]; Examiner note: the control a timing is interpreted as the specify the precise “relative time” within the period. The update is interpreted as the configuring),
based on a comparison result to adjust synchronization between the data storage buffer group and the offset storage buffer group (i.e. “this common time base or clock may allow the producer target and the consumer target to synchronize their application loops based on period and time offset specified on the buffer. Global time synchronization can be achieved by many means using signal based or time based clock synchronization.”; para. [0078]; Examiner note: the based on a comparison result is the based on period and time offset specified on the buffer. The adjust synchronization in interpreted as the synchronization can be achieved)
by selectively updating at least one of the data storage buffer group and the offset storage buffer group (i.e. “In the example of FIG. 3, the two time sensitive buffers are configured with pre-defined fixed size of a heterogeneous set of data (specified from the nodes “Isoc Output” and “Isoc Input” to the respective “data” terminals of the buffers)”; fig.3, para. [0080]; Examiner note: the selectively updating at least one of the data storage buffer group and the offset storage buffer group is interpreted as the two time sensitive buffers are configured with pre-defined fixed size of a heterogeneous set of data);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chandhoke that teaches configuring buffers with timing information into the combination of the prior arts of Kim that teaches string matching, and Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation for doing so would be to control the loop cycle in the buffer, as it improves the application program's consumption of isochronous data (Chandhoke, para. [0003]).
As per claim 11, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 10 above.
Additionally, Kim teaches wherein offset data used when the target data is extracted among the plurality of offset data segments and string data corresponding to the offset data segments used when the target data is extracted are output from the data storage buffer group and the offset storage buffer group in the first cycle (i.e. “the concatenation circuit 106 outputs a detection signal for indicating that the target string "GHMNQR" configured with "GHMN" and "QR" corresponding to the same offset is detected.”; para. [0068]-[0070]; Examiner note: the target string herein belong to offsets 1 and 2 and is within the Phases 1-3 herein interpreted as data buffer group and the offset buffer group in the first cycle).
As per claim 12, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 10 above.
Additionally, Kim teaches wherein the synchronizer updates at least one of the data storage buffer group and the offset storage buffer group, based on the comparison result of the number of remaining string data segments and the number of remaining offset data segments, and wherein, in the updated at least one of the data storage buffer group, data of a second cycle as a next cycle of the first cycle is used when the target data is extracted (i.e. “Accordingly, the first comparator 305 outputs a detection signal for indicating that the prefix "ABCD" of the target string "ABCDEFGHMNS" is detected. Further, since the detection signal corresponds to the offset 2, the offset controller 306 outputs an offset control signal for selecting the fourth string corresponding to the offset 2 in the next stage.”; para. [0129]-[0131], [0184]; Examiner note: the next cycle of the first cycle is used when the target data is extracted is interpreted as the next stage).
As per claim 13, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 12 above.
Additionally, Kim teaches wherein the synchronizer updates the data storage buffer group when the number of remaining string data segments is less than the number of remaining offset data segments (i.e. “when the size of the sub-string to be compared is less than the first string, the comparator 4042 combines the bytes that are "don't care" terms of the corresponding sub-string, updates them to be the same size of the first string, and compares them."”; para. [0052], [0170]).
As per claim 14, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 12 above.
Additionally, Kim teaches wherein the synchronizer updates the data storage buffer group and the offset storage buffer group when the number of remaining string data segments is equal to the number of remaining offset data segments (i.e. “in the case of comparing the prefix and the fourth string, the comparators 4012-1, 4012-2, . . . , 4012-N combine the bytes of the "don't care" term and the corresponding prefix, updates them to be the same size of the first string " … ”; para. [0090]-[0093], [0161]).
As per claim 21, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 1 above.
Additionally, Kim teaches wherein the input storage buffer group further includes a validity buffer group configured to receive and output validity data indicating validity of the offset data (i.e. “the input buffer 101 generates a string stream from the input data stream, temporarily stores the same”; para. [0042]. Further, i.e. “when the input buffer 101 outputs the first string “CDEF,” the delay buffer 102 outputs “XYAB” output by the input buffer 101 by 1 clock signal in advance as the second string.”; para. [0050], [0061]-[0062]; Examiner note: the validity buffer group is interpreted as the delay buffer 102 outputs),
wherein the validity data includes a bit value determined based on a comparison between previous offset data and current offset data (i.e. “the second string that is output after the first string that is output by the input buffer 101 at the previous clock signal is delayed by the delay buffer 102 to generate a third string (S103), and generates a plurality of fourth strings with different offsets from the third string (S104).”; para. [0079]. Further, i.e. “The delay buffer 102 temporarily stores the string output by the input buffer 101, delays it by 1 clock signal,”; para. [0044]; Examiner note: the bit value is interpreted as the 1 clock signal. The previous offset data is interpreted as the third string (S1014). The current offset data are interpreted as the plurality of fourth strings with different offsets).
As per claim 22, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 10 above.
Additionally, Kim teaches further includes a validity storage buffer group configured to receive and output validity data indicating validity of the offset data (i.e. “when the input buffer 101 outputs the first string “CDEF,” the delay buffer 102 outputs “XYAB” output by the input buffer 101 by 1 clock signal in advance as the second string.”; para. [0050], [0061]-[0062]; Examiner note: the validity buffer group is interpreted as the delay buffer 102 outputs),
wherein the validity data includes a bit value determined based on a comparison between previous offset data and current offset data (i.e. “the second string that is output after the first string that is output by the input buffer 101 at the previous clock signal is delayed by the delay buffer 102 to generate a third string (S103), and generates a plurality of fourth strings with different offsets from the third string (S104).”; para. [0079]. Further, i.e. “The delay buffer 102 temporarily stores the string output by the input buffer 101, delays it by 1 clock signal,”; para. [0044]; Examiner note: the bit value is interpreted as the 1 clock signal. The previous offset data is interpreted as the third string (S1014). The current offset data are interpreted as the plurality of fourth strings with different offsets).
8. Claims 8 and 16-18 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim et al. (US 20110055130 A1) in view of Chemparathy et al. (US 10672098 B1) in further view of Chandhoke (US 20130080661 A1) still in further view of Sathe et al. (US 20160335296 A1).
As per claim 8, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 10 above.
However, it is noted that the combination of the prior arts of Kim, Chemparathy and Chandhoke do not explicitly teach “wherein the first size is determined based on a bandwidth of a channel through which the string group data segments are received.”
On the other hand, in the same field of endeavor, Sathe teaches wherein the first size is determined based on a bandwidth of a channel through which the string group data segments are received (i.e. “When a high performance search is to be performed on a large rule table it is important to achieve the performance requirements with the least amount of memory overhead. The highest bandwidth that can be achieved is limited by the clock frequency at which the memory can be accessed.”; para. [0128]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Sathe that teaches optimize memory searching into the combination of Kim that teaches string matching, Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC, and Chandhoke that teaches configuring buffers with timing information. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation is to employ a hierarchical tree for high-performance searches, enhancing memory utilization, search efficiency, and table update speed (Sathe, para. [0091], [0128]).
As per claim 16, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 10 above.
However, it is noted that the combination of the prior arts of Kim, Chemparathy and Chandhoke do not explicitly teach “wherein the fixed size is determined based on a bandwidth of a channel through which the string group data is received to be synchronized with the reference cycle.”
On the other hand, in the same field of endeavor, Sathe teaches wherein the fixed size is determined based on a bandwidth of a channel through which the string group data is received to be synchronized with the reference cycle (i.e. “When a high performance search is to be performed on a large rule table it is important to achieve the performance requirements with the least amount of memory overhead. The highest bandwidth that can be achieved is limited by the clock frequency at which the memory can be accessed.”; para. [0128]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Sathe that teaches optimize memory searching into the combination of Kim that teaches string matching, Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC, and Chandhoke that teaches configuring buffers with timing information. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation is to employ a hierarchical tree for high-performance searches, enhancing memory utilization, search efficiency, and table update speed (Sathe, para. [0091], [0128]).
As per claim 17, Kim, Chemparathy, Chandhoke and Sathe teach all the limitations as discussed in claim 16 above.
Additionally, Kim teaches wherein the offset storage buffer group receives and outputs stores the plurality of offset data segments equally having a predetermined size to be synchronized with the reference cycle (i.e. “The input buffer 101 arranges an input data stream in a predetermined size to generate a string stream, and sequentially outputs a plurality of strings included in the string stream.”; para. [0042]-[0043]).
As per claim 18, Kim, Chemparathy, Chandhoke and Sathe teach all the limitations as discussed in claim 17 above.
Additionally, Kim teaches wherein the offset storage buffer group determines a number of the plurality of offset data segments received to be synchronized with the reference cycle, based on the fixed size of the string group data and the predetermined size of the plurality of offset data segments (i.e. “the input buffer 101 arranges the input data stream of Phase 1 by 4 bytes and sequentially outputs the first string. The delay buffer 102 delays the first string output by the input buffer 101 by 1 clock signal, and outputs the second string. Therefore, the first string and the second string are input to the distributor 103 by 8 bytes in a like manner of Phase 2, and are used to generate the third string.”; para. [0061]).
9. Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over Kim et al. (US 20110055130 A1) in view of Chemparathy et al. (US 10672098 B1) in further view of Chandhoke (US 20130080661 A1) still in further view of Lu et al. (US 20120089653 A1).
As per claim 15, Kim, Chemparathy and Chandhoke teach all the limitations as discussed in claim 12 above.
However, it is noted that the combination of the prior arts of Kim and Chemparathy do not explicitly teach “wherein the synchronizer updates the offset storage buffer group when the number of remaining string data segments is greater than the number of remaining offset data segments.”
On the other hand, in the same field of endeavor, Lu teaches wherein the synchronizer updates the offset storage buffer group when the number of remaining string data segments is greater than the number of remaining offset data segments (i.e. “determining whether the offset is larger than the length of the data string is converting the obtained offset to decimal number, and comparing size of the decimal number with that of the data string to be converted, if the offset is larger than that of the data string to be converted, it determines the offset overflow.”; para. [0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lu that teaches a data converting into the combination of Kim that teaches string matching, Chemparathy that teaches synchronizing access to buffered data in a shared buffer for an IC, and Chandhoke that teaches configuring buffers with timing information. Additionally, this enables the transmission of packets at high speeds through a network.
The motivation is to simplify the process of obtaining a predetermined bits of data, because it can improve the efficiency and accuracy of obtaining data (Lu, para. [0086]).
Prior Art of Record
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 20230236970 A1), teaches a memory module is operable in a computer system having a memory controller.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CAIA DO whose telephone number is (469)295-9251. The examiner can normally be reached on Monday - Friday / 06:30 to 16:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ng, Amy can be reached on (571) 270-1698. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTONIO J CAIA DO/
Examiner, Art Unit 2164
/AMY NG/Supervisory Patent Examiner, Art Unit 2164