DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show, a sub-word line driver block (SWD) and a sense amplifier block (S/A) in the printed circuit assembly (PCA), as described in the specification (para. 0019). Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0003 reads "...and the protrusion protrude in a second horizontal direction..." and should read "...and the protrusion protrudes in a second horizontal direction...".
Paragraph 0004 reads “…a plurality of upper conductive line positioned on the plurality of channel structures…” should read “…a plurality of upper conductive lines positioned on the plurality of channel structures…”. Appropriate correction is required.
Claim Objections
Claims objected to because of the following informalities:
Claim 1; and “a first gate dielectric layer at least partially surround a surface of the channel structure” should read “a first gate dielectric layer at least partially surrounding a surface of the channel structure”.
Claim 14 recites the limitation “...a plurality of upper conductive line positioned on the plurality of channel structures…” and should recite “…a plurality of upper conductive lines positioned on the plurality of channel structures…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-15, 17, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryu et al. (US 20220223732 A1) hereinafter referred to as "Ryu".
Regarding claim 1, Ryu discloses in figs. 1-10, a semiconductor device comprising:
a mold insulating pattern (fig. 1, element 112; para. 0032) (a first interlayer insulating layer which defines a channel trench is functionally indistinguishable from the mold insulating pattern) positioned on a substrate (fig. 2, element 100; para. 0029);
an upper conductive line (fig. 2, element 150A and element 150B) extending in a first horizontal direction (fig. 1, Y-direction) on the substrate 100 (para. 0045, 0046);
a channel structure (fig. 3, element 130) including a vertical channel portion (fig. 3, vertical portion of “U” shape; para. 0036) that faces a side surface of the upper conductive line 150A and 150B, and is in contact with a first side wall (fig. 2, element 112t1; para. 0032) of the mold insulating pattern 112, wherein the vertical channel portion extends in a vertical direction (fig. 2, Z-direction);
a first gate dielectric layer (fig. 8, element 142) at least partially surrounding a surface of the channel structure 130 (para. 0083); and
a second gate dielectric layer (fig. 8, element 144) positioned between the upper conductive line 150A and 150B, and the first gate dielectric layer 142 on the channel structure 130 (para. 0083),
wherein the mold insulating pattern 112 includes a body and protrusion (see annotated fig. 1 below; para. 0034), wherein the body extends in the first horizontal direction (Y-direction), and the protrusion protrude in a second horizontal direction (fig. 1, X-direction) that intersects with the first horizontal direction (Y-direction).
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Regarding claim 2, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the channel structure 130 includes an oxide semiconductor layer (para. 0039 and 0041).
Regarding claim 3, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein a side wall (fig. 1, element 112t1) of the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 corresponds to the first side wall 112t1 of the mold insulating pattern 112 (para. 0036).
Regarding claim 5, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 has a rectangular shape (see annotated fig. 1 above; para. 0037, a plurality of channel structures 130 are arranged in a rectangular array therefore the surrounding mold insulating pattern 112, including the protrusion, will also be rectangular).
Regarding claim 6, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 is in a mirror-symmetric shape with respect to the body of the mold insulating pattern (in annotated fig. 1 above, protrusions on either side of the body of the mold insulating pattern form a mirror-symmetric shape).
Regarding claim 7, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein a side wall of the body of the mold insulating pattern 112, on which no protrusion is positioned (see annotated fig. 1 above and fig. 8, element 112t2), faces the upper conductive line 150A and 150B with the second gate dielectric layer (fig. 8, element 144) disposed therebetween.
Regarding claim 8, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the mold insulating pattern 112 includes a low-k material having a smaller dielectric constant than each of a dielectric constant of the first gate dielectric layer 142 and a dielectric constant of the second gate dielectric layer 144 (para. 0035, the mold insulating pattern has a lower dielectric constant than silicon oxide; para. 0085, dielectric layer 142 and dielectric layer 144 have a higher dielectric constant than silicon oxide).
Regarding claim 9, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the vertical channel portion of the channel structure 130 is spaced apart from the body of the mold insulating pattern 112 (see annotated fig. 1 above, the protrusion of the mold insulating pattern spaces apart the body of the mold insulating pattern from the channel structure).
Regarding claim 10, Ryu discloses the semiconductor device of claim 1. Ryu further discloses wherein the channel structure 130 is a multi-layer structure including two or more layers (fig. 3, element 132 and element 134; para. 0041).
Regarding claim 11, Ryu discloses the semiconductor device of claim 1. Ryu also discloses the semiconductor device further comprising a lower conductive line (fig. 8, element 120) positioned between the substrate 100 and the channel structure 130, wherein the lower conductive line 120 is spaced apart from the upper conductive line 150A and 150B with the channel structure 130, the first gate dielectric layer 142, and the second gate dielectric layer 144 disposed therebetween, wherein an upper surface of the lower conductive line 120 is in contact with a horizontal channel portion of the channel structure 130, and the lower conductive line 120 extends in the second horizontal direction (fig 8, X-direction; para. 0036 ).
Regarding claim 12, Ryu discloses the semiconductor device of claim 1. Ryu also discloses the semiconductor device further comprising a conductive contact pattern (fig. 2, element 160A and element 160B) connected to the channel structure 130 (para. 0059-0060, landing pads that electrically connect the channel structure to capacitor structures are functionally indistinguishable from conductive contact patterns).
Regarding claim 13, Ryu discloses the semiconductor device of claim 12. Ryu also discloses the semiconductor device further comprising a capacitor structure (fig. 2, element 170A and element 170B) connected to the conductive contact pattern 160A and 160B (para. 0060).
Regarding claim 14, Ryu discloses in fig. 1-8, a semiconductor device comprising:
a plurality of lower conductive lines (fig. 1 and fig. 4, element 120; para. 0030) positioned on a substrate (fig. 4, element 100; para. 0029) and arranged in parallel to each other (fig. 1 and fig. 4);
a mold insulating pattern (fig. 1 and fig. 4, element 112) positioned on the plurality of lower conductive lines 120, and extending in a first horizontal direction (fig. 1, Y-direction), wherein the mold insulating pattern 112 defines a transistor region (fig. 3; para. 0032, 0033);
a plurality of channel structures (fig. 1, element 130; para. 0036) arranged along the first horizontal direction (fig. 1, Y-direction) in the transistor region (fig. 3), wherein each of the plurality of channel structures 130 includes a vertical channel portion (fig. 3, vertical portion of “U” shape; para. 0036) that faces a side wall (fig. 1 and fig. 3, element 112t1) of the mold insulating pattern 112;
a first gate dielectric layer (fig. 8, element 142; para. 0083) overlapping a side wall 112t1 of the plurality of channel structures 130 (para. 0083);
a plurality of upper conductive line (fig. 1 and fig. 3, element 150A and element 150B) positioned on the plurality of channel structures 130 in the transistor region (fig. 3), and including a side wall that faces the vertical channel portion of each of the plurality of channel structures 130, wherein the plurality of upper conductive lines 150A and 150B extend in the first horizontal direction (fig. 1 and fig. 3, Y-direction; para. 0045, 0046);
a second gate dielectric layer (fig. 8, element 144; para. 0083) positioned between the plurality of channel structures 130 and the plurality of upper conductive lines 150A and 150B; and
a plurality of conductive contact patterns (fig. 3, element 160A and element 160B; para. 0038), each of which is connected to the vertical channel portion of each of the plurality of channel structures 130,
wherein a width (fig. 2, element W11) in a second horizontal direction (fig. 1, X-direction) of a first portion, of the mold insulating pattern 112, that faces the vertical channel 130 portion is greater than a width (fig. 2, element W12) in the second horizontal direction (X-direction) of a second portion, of the mold insulating pattern (112), that does not face the vertical channel 130 portion (para. 0034), wherein the second horizontal direction (X-direction) intersects with the first horizontal direction (Y-direction).
Regarding claim 15, Ryu discloses the semiconductor device of claim 14. Ryu further discloses wherein the plurality of channel structures 130 includes an oxide semiconductor layer (para. 0039 and 0041).
Regarding claim 17, Ryu discloses the semiconductor device of claim 14. Ryu further discloses wherein a plurality of transistors (fig. 1 and fig. 2, A—A) including the plurality of channel structures (fig. 1 and fig. 2, element 130) are positioned in the transistor region (fig. 3), the plurality of transistors include two transistors facing each other, and the two transistors share a channel structure of the plurality of channel structures 130 (para. 0045).
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Regarding claim 18, Ryu discloses a semiconductor device comprising:
a printed circuit region (see annotated fig. 6 above) positioned on a substrate (fig. 6, element 100) and including a plurality of printed circuits (fig. 6, element PT; para. 0070, 0071, 0072);
a lower conductive line (fig. 6, element 120) positioned on the printed circuit region (see annotated fig. 6 above) and connected to the plurality of printed circuits PT (para. 0073, 0074);
a mold insulating pattern (fig. 3 and fig. 6, element 112) positioned on the lower conductive line 120 and including a side wall (fig. 3, element 112t1) that defines a transistor region (fig. 3; para. 0032, 0033);
a channel structure (fig. 3, element 130) positioned in the transistor region (fig. 3, A—A), and including a lower surface and a vertical portion (fig. 3, vertical portion of “U” shape; para. 0036), wherein the lower surface of the channel structure is in contact with an upper surface of the lower conductive line 120, and the vertical channel portion of the channel structure 130 faces the side wall 112t1 of the mold insulating pattern 112 (para. 0036);
a first gate dielectric layer (fig. 8, element 142) and a second gate dielectric layer (fig. 8, element 144) covering the channel structure 130 in the transistor region (fig. 8, A—A; para 0083);
an upper conductive line (fig. 8, element 150A and element 150B) positioned on the first gate dielectric layer 142 and the second gate dielectric layer 144 in the transistor region (fig. 8, A—A), and including a side wall that faces the vertical channel portion of the channel structure 130 (para. 0047); and
a conductive contact pattern (fig. 8, element 160A and element 160B) connected to the vertical channel portion of the channel structure 130 (upper portion of “U” shape channel layer is equivalent to vertical channel portion of channel structure, para. 0036, 0038),
wherein the channel structure 130 includes an oxide semiconductor layer (para. 0039 and 0041), and
the mold insulating pattern 112 includes a protrusion (see annotated fig. 1 above) that protrudes in a direction (fig. 1, X-direction) that intersects with a direction (fig. 1, Y-direction) in which the mold insulating pattern 112 extends, wherein the protrusion of the mold insulating pattern 112 has a preset thickness (para. 0034, a difference in widths of a first portion of the mold insulating pattern that faces the vertical channel portion W11 and a second portion of the mold insulating pattern that does not face the vertical channel portion W12, defines the protrusion of the mold insulating pattern, and is created by the etching of the preset separation trench 130t, therefore the thickness of the protrusion of the mold insulating pattern is preset) and is in contact with the vertical channel 130 portion (fig. 3, vertical portion of “U” shape; para. 0036).
Regarding claim 20, Ryu discloses the semiconductor device of claim 18. Ryu further discloses wherein the protrusion (see annotated fig. 1 above) is mirror-symmetrical with respect to a body of the mold insulating pattern 112 and has a rectangular shape (in annotated fig. 1 above, protrusions on either side of the body of the mold insulating pattern 112 form a mirror-symmetric shape; para. 0037, a plurality of channel structures 130 are arranged in a rectangular array, therefore the surrounding mold insulating pattern 112, including the protrusion, will also be rectangular).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu.
Regarding claim 4, Ryu discloses the semiconductor device of claim 1.
Ryu does not expressly disclose wherein the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 protrudes from the body of the mold insulating pattern 112 by a preset distance that is greater than or equal to a thickness of the second gate dielectric layer 144.
Ryu discloses that the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 protrudes from the body of the mold insulating pattern by a preset distance, created by an etching of a preset separation trench (fig. 20, element 130t; para. 0034), that is equal to the difference of a width (fig. 2, element W11) of the mold insulating pattern 112 defined by a first channel trench (fig. 2, element 112t1) and a width (fig. 2, element W12) of the mold insulating pattern 112 defined by a second channel trench (fig. 2, element 112t2).
In other words, the preset distance, D = W11 — W12. Ryu discloses width W11 is greater than W12 (para. 0034).
It is evident that Ryu recognizes that optimization of the preset distance D is a result effective variable since varying it affects separation distance between channel regions of adjacent transistors. The more the preset distance D the higher the separation distance, and this will provide better isolation between channel regions of adjacent transistors. When W11 is further increased, the preset distance D becomes greater than or equal to a thickness of the second gate dielectric layer 144.
It would therefore have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the preset distance D relative to a thickness of the second gate dielectric layer 144, as taught by Ryu, to maintain better isolation between channel regions of adjacent transistors. One would have been motivated to do so as Ryu recognizes that optimization of the preset distance D is a known result effective variable as explained above.
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Regarding claim 16, Ryu discloses the semiconductor device of claim 14.
Ryu does not expressly disclose wherein a difference between the width W11 in the second horizontal direction of the first portion, of the mold insulating pattern 112, that faces the vertical channel 130 portion and the width W12 in the second horizontal direction of the second portion, of the mold insulating pattern 112, that does not face the vertical channel 130 portion is twice or more a thickness of the second gate dielectric layer 144.
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Ryu discloses that a difference between the width W11 in the second horizontal direction (X-direction) of the first portion, of the mold insulating pattern 112, that faces the vertical channel 130 portion and the width W12 in the second horizontal direction (X-direction) of the second portion, of the mold insulating pattern 112, that does not face the vertical channel 130 portion is a preset distance, created by an etching of a preset separation trench (fig. 20, element 130t; para. 0034).
In other words, the preset distance, D = W11 — W12. Ryu discloses width W11 is greater than W12 (para. 0034).
It is evident that Ryu recognizes that optimization of the preset distance D is a result effective variable since varying it affects separation distance between channel regions of adjacent transistors. The more the preset distance D the higher the separation distance, and this will provide better isolation between channel regions of adjacent transistors. When W11 is further increased, the preset distance D becomes twice or more a thickness of the second gate dielectric layer 144.
It would therefore have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the preset distance D relative to a thickness of the second gate dielectric layer 144, as taught by Ryu, to maintain better isolation between channel regions of adjacent transistors. One would have been motivated to do so as Ryu recognizes that optimization of the preset distance D is a known result effective variable as explained above.
Regarding claim 19, Ryu discloses the semiconductor device of claim 18.
Ryu does not expressly disclose wherein the preset thickness is greater than or equal to a thickness of the second gate dielectric layer 144.
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Ryu discloses the protrusion (see annotated fig. 1 above) of the mold insulating pattern 112 protrudes from the body of the mold insulating pattern by a preset distance, created by an etching of a preset separation trench (fig. 20, element 130t; para. 0034), that is equal to the difference of a width (fig. 2, element W11) of the mold insulating pattern 112 defined by a first channel trench (fig. 2, element 112t1) and a width (fig. 2, element W12) of the mold insulating pattern 112 defined by a second channel trench (fig. 2, element 112t2).
In other words, the preset distance, D = W11 — W12. Ryu discloses width W11 is greater than W12 (para. 0034).
It is evident that Ryu recognizes that optimization of the preset distance D is a result effective variable since varying it affects separation distance between channel regions of adjacent transistors. The more the preset distance D the higher the separation distance, and this will provide better isolation between channel regions of adjacent transistors. When W11 is further increased, the preset distance D becomes greater than or equal to a thickness of the second gate dielectric layer 144.
It would therefore have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the preset distance D relative to a thickness of the second gate dielectric layer 144, as taught by Ryu, to maintain better isolation between channel regions of adjacent transistors. One would have been motivated to do so as Ryu recognizes that optimization of the preset distance D is a known result effective variable as explained above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al. (US 20220384661 A1) and Lee et al. (US 20230096214 A1) are cited to teach a semiconductor device, relevant to claims 1-20 of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN MICHAEL DAVIS whose telephone number is (571)270-5775. The examiner can normally be reached M-F: 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SMD/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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