Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The Amendment filed November 6, 2025 has been entered.
Claims 7-8 and 12-17 are rejected over the previously applied reference(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2002/0196061 to Atyunin et al. (“Atyunin”).
With respect to claim 7, Atyunin discloses in Fig. 1 an integrated circuit comprising:
a main delay line (e.g., 5) comprising first delay elements (e.g., 7(1)-7(N)) coupled in series and coupled to a control node (e.g., Bias), the main delay line (e.g., 5) being responsive to generate a delayed version (e.g., Tap7(1)) of an input clock signal (e.g., Input); and
a replica load (e.g., 1) coupled to the control node (e.g., Bias), the replica load (e.g., 1) being responsive to a replica clock signal (e.g., Ref.Clock), wherein a signal on the control node (e.g., Bias) determines a duration (e.g., Para. 36) of a delay of each element of the first delay elements (e.g., 7(1)-7(N)). As to the feature that the input clock signal is based on a system clock signal and the replica clock signal is based on a replica of the system clock signal, such a feature is considered to be a recitation of the intended use of the claimed invention: a clock generator for the input clock signal and a clock generator for the system clock signal are not positively recited as elements of the claimed invention. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the Fig. 1 circuit of Atyunin is capable of the recited use (e.g., in Fig. 1, receiving Input based on a system clock from a clock generator and receiving Ref.Clock based on a replica of the system clock signal from a clock generator).
With respect to claim 15, the replica load (e.g., 1) comprises a replica delay line (e.g., 1) having second delay elements (e.g., 4(1)-4(M)) coupled in series and coupled to the control node (e.g., Bias).
With respect to claim 16, while second delay elements (e.g., 4(1)-4(M)) and the first delay elements 7(1)-7(N)) are the same in number in Fig. 1 example (e.g., Para. 30), Atyunin infers that the numbers may also be different (e.g., Para. 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 12-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Atyunin.
With respect to claim 8, Atyunin discloses in Fig. 1 an input clock signal (e.g., Input) but fails to disclose that Input is generated using a clock gating circuit configured to provide the input clock signal based on a system clock signal and in response to a first value of a control signal. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention to generate a clock signal using a clock gating circuit configured to provide the input clock signal based on a system clock signal and in response to a first value of a control signal. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to generate the input clock signal (e.g., Input) in Fig. 1 of Atyunin using the notoriously well-known method of generating an input clock signal based on a system clock signal and in response to a first value of a control signal because the generation of the input clock signal (e.g., Input) in Fig. 1 of Atyunin requires a specific implementation in fabrication and the notoriously well-known example provides such a specific implementation.
With respect to claim 12, Atyunin discloses in Fig. 1 using the delayed version of the input clock signal selected (e.g., 6) from a plurality of signals on a plurality of taps (e.g., Tap7(1)-Tap7(N)) of the main delay line. Atyunin fails to disclose a serial interface circuit configured to sample received data using the delayed version of an input clock signal. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention to conduct data sampling using a delayed version of an input clock signal. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use, for the notoriously well-known data sampling with a delayed version of an input clock signal, the delayed input clock signal generator in Fig. 1 of Atyunin because the notoriously well-known method of data sampling with a delayed version of an input clock signal requires a specific implementation in fabrication of the generator of a delayed version of an input clock signal and the delayed input clock signal generator in Fig. 1 of Atyunin provides such a specific implementation.
With respect to claim 13, the plurality of taps (e.g., Tap7(1)-Tap7(N)) provide a plurality of non-overlapping delayed versions of the input clock signal (e.g., the delayed versions of Input produced at Tap7(1) in series do not overlap with themselves).
With respect to claim 14, the setting/changing of the control signal may be done after setting loading the control node (e.g., Bias) with a replica (e.g., 1) of a load of the main delay line (e.g., 5).
With respect to claim 17, Atyunin fails to disclose a buffer configured to provide a control voltage on the control node (e.g., Bias). However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that unity gain amplifier operating as a buffer, with feedback, may be used to buffer an output voltage. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Bias in Fig. of Atyunin using the notoriously well-known unity gain amplifier/buffer, with feedback, because such a modification allows buffering.
Response to Arguments
Applicant's arguments filed March 10, 2026 have not been found persuasive. For example, Applicant argues that Atyunin does not disclose that the input clock signal is based on a system clock signal and the replica clock signal is based on a replica of the system clock signal as recited in claim 7. However, as stated above in the main body of the rejection, such features are disclosed in Atyunin.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Allowable Subject Matter
Claims 9-11 and 21-29 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842