DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 7-10, 13-14 and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Chua-Eoan et al. (US 2010/0097101 and Chua hereinafter) in view of Chen et al. (US 2017/0346485 and Chen hereinafter).
Regarding claim 1, Chua discloses a chip [100, fig. 4], comprising: a circuit block [101, fig. 6]; globally distributed switches [128-130, par. 0066] physically located in the circuit block; and micro switches [131-139, fig. 6] distributed between at least two of the globally distributed switches [128 and 129, see fig. 6] in the circuit block. Chua does not explicitly disclose wherein the micro switches are distributed nonuniformly among the standard cells, each of the micro switches being physically located between a respective pair of the standard cells.
However, Chen discloses [see fig. 6] wherein switch cells [6401/6402/6404] are distributed nonuniformly [staggered, par. 0028] among the standard cells, each of the micro switches being physically located between a respective pair of the standard cells [standard cells (not shown in the figure) are placed between the intervals of the switch cells, par. 0028]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Chua by incorporating the placement of the switches as taught in Chen in order to reduces area impact on the IC because fewer switch cells are placed on the IC [par. 0028].
Regarding claim 5, Chua in view of Chen discloses further comprising an enable path [145/142, figs. 6], wherein the globally distributed switches are coupled to the enable path, the enable path includes buffers [123 in fig. 5, par, 0064], and the micro switches are coupled to the enable path between the at least two of the globally distributed switches [see fig. 6].
Regarding claim 7, Chua in view of Chen discloses wherein the micro switches are coupled to the enable path in a daisy chain configuration [fig. 9; par. 0064, 0069, 0076].
Regarding claim 8, Chua in view of Chen discloses wherein each of the buffers comprises one or more inverters coupled in series [126 and 127, fig. 5, par. 0043].
Regarding claim 9, Chua in view of Chen discloses further comprising a switch controller [110, fig. 6] coupled to the enable path, wherein the switch controller is configured to output an enable signal [EN2] to the enable path to turn on the globally distributed switches and the micro switches.
Regarding claim 10, Chua in view of Chen discloses wherein the enable signal sequentially turns on the globally distributed switches as the enable signal propagates through the enable path [fig. 6, par. 0064].
Regarding claim 13, Chua in view of Chen discloses wherein the micro switches are coupled to the second enable path in a daisy chain configuration [par. 0064, 0069, 0076].
Regarding claim 14, Chua in view of Chen discloses further comprising a switch controller [110, fig. 6] coupled to the first enable path and the second enable, wherein the switch controller is configured to: output a first enable signal [EN2] to the first enable path to turn on the high-resistance switches; and after a time delay from outputting the first enable signal [par. 0070], output a second enable signal [EN1, fig. 6] to the second enable path to turn on the low-resistance switches and the micro switches.
Regarding claim 17, Chua in view of Chen discloses further comprising: block switches [switch in 102, figs. 4 and 13-15, par. 0071] arranged along at least part of a periphery of the circuit block; and a gated network [gate enable EN2/EN1, fig. 11-12 and 15] coupled to the block switches and the circuit block.
Regarding claim 18, Chua in view of Chen discloses [fig. 6] further comprising a hybrid switch controller [110] coupled to the block switches and the globally distributed switches, wherein the hybrid switch controller is configured to turn on the block switches and the globally distributed switches sequentially or turn on the block switches and the globally distributed switches concurrently [par. 0051 and 0064].
Regarding claim 19, Chua in view of Chen discloses [fig. 6] further comprising a hybrid switch controller [110] coupled to the block switches and the globally distributed switches, wherein the hybrid switch controller is configured to turn on the block switches, and turn on the globally distributed switches after a time delay from turning on the block switches [par. 0043, 0054 and 0064-0065].
Regarding claim 20, Chua in view of Chen discloses [fig. 6] further comprising: block switches [switches in 102, fig. 4] arranged along at least part of a periphery of the circuit block; a first gated network [gate enable EN2, fig. 11-12 and 15] coupled to the block switches and the circuit block; and a second gated network [gate enable EN1, fig. 11-12 and 15] coupled to the globally distributed switches and the circuit block.
Regarding claim 21, Chua in view of Chen discloses wherein the micro switches have varying sizes [par. 0026].
Claims 4, 6, 11-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chua-Eoan et al. in view of Chen et al.
Regarding claims 4 and 16, Chua in view of Chen discloses all the features with respect to claims 1 and 16 as outlined above. Chua in view of Chen further discloses SCSC standard cell has a smaller N-channel pulldown transistor than the other SCSC standard cell [par. 0068]. Chua in view of Chen does not explicitly disclose wherein each of the micro switches is at least two times smaller than each of the globally distributed switches. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claims 6 and 12, Chua in view of Chen discloses all the features with respect to claims 5 and 11 as outlined above. Chua in view of Chen does not explicitly disclose wherein the micro switches are coupled to the enable path in a star configuration. In cases like the present, where patentability is said to be based upon particular chosen configuration as a design alternative to other alternative to other known configuration (e.g., daisy chain), applicant must show that the chosen star configuration is critical. The selection of a star configuration from among number of predictable option does not appear to yield any unexpected results or critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553, 555, 188 USPQ 7, 9 (CCPA 1975).
Regarding claim 11, Chua in view of Chen discloses all the features with respect to claim 1 as outlined above. Chua in view of Chen further discloses [see figs. 6, 11-12, 15, 17], wherein the globally distributed switches, and the chip further comprises: a first enable path [EN2, 145, par. 0064], wherein the high-resistance switches are coupled to the first enable path, and the first enable path includes first buffers; and a second enable path [EN1, figs. 6, 12], wherein the low-resistance switches are coupled to the second enable path [par. 0068], the second enable path includes second buffers, and the micro switches are coupled to the second enable path between at least two of the low-resistance switches. Chua in view of Chen does not explicitly disclose the globally distributed switches includes low-resistance switches and high-resistance switches, each of the high-resistance switches having a higher on resistance than each of the low-resistance switches, although Chua in view of Chen does teach One SCSC standard cell has a smaller N-channel pulldown transistor than the other SCSC standard cell [fig. 12, par. 0068]. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842