DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), and Sutardja (US 7,173,486).
In regard to Claim 1:
Oswal discloses, in Figure 1, an electrical circuit, comprising:
a first operational amplifier (110); and a first output, a second operational amplifier (120), including at least one second non-inverting input (120 input, paragraph 15 line 5) and a second output (120 output); a third operational amplifier(130) including at least one third inverting input (-gm3, 130 input) and third output (130 output); a feedback path (150) including a series circuit including a second resistor (Rm2) and a second capacitor (Cm2); wherein the feedback path (150) is arranged between the third output (130 output) and at least one third inverting input (150 is connected between the 130 input and output) and a first feedback path (160) including a first series circuit including a first resistor (Rm1) and a first capacitor (Cm1) wherein the first feedback path (160) is arranged between a node (150 and 160 connection node) and at least one second non-inverting input (120 input).
Oswal does not disclose the first non-inverting input and first inverting input, a second resistor, and the node being arranged between the resistor and the second resistor.
Lumsden discloses, in Figure 5, the inverting and non-inverting input (VA, VB).
It would have been obvious to one having ordinary skill in the art, at the time of the effective filing date of the application, to use an inverting and non-inverting inputs to the operational amplifier as taught by Lumsden with the operational amplifier taught by Oswal, instead of a single inverting/non-inverting input as it leads to better common mode rejection which leads to better performance without altering the disclosed invention and leads to the same predictable results of the disclosed invention.
Oswal and Lumsden do not disclose the node being arranged between the resistor and the second resistor.
Sutardja discloses, in Figure 24, a second resistor (2410) and the node (514 and 2410 connection node) being arranged between the resistor (2410) and the second resistor (514).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to add the resistor (2410) taught by Sutardja with the feedback paths taught by Oswal and Lumsden in order to achieve higher values of gain or bandwidth (or both) (Sutardja Column 4: lines 64-65).
In regard to Claim 7:
Oswal discloses, in Figure 1, a single-ended amplifier, comprising: an electrical circuit, comprising:
a first operational amplifier (110); and a first output, a second operational amplifier (120), including at least one second non-inverting input (120 input, paragraph 15 line 5) and a second output (120 output); a third operational amplifier(130) including at least one third inverting input (-gm3, 130 input) and third output (130 output); a feedback path (150) including a series circuit including a second resistor (Rm2) and a second capacitor (Cm2); wherein the feedback path (150) is arranged between the third output (130 output) and at least one third inverting input (150 is connected between the 130 input and output) and a first feedback path (160) including a first series circuit including a first resistor (Rm1) and a first capacitor (Cm1) wherein the first feedback path (160) is arranged between a node (150 and 160 connection node) and at least one second non-inverting input (120 input).
Oswal does not disclose the first non-inverting input and first inverting input, a second resistor, and the node being arranged between the resistor and the second resistor.
Lumsden discloses, in Figure 5, the inverting and non-inverting input (VA, VB).
It would have been obvious to one having ordinary skill in the art, at the time of the effective filing date of the application, to use an inverting and non-inverting inputs to the operational amplifier as taught by Lumsden with the operational amplifier taught by Oswal, instead of a single inverting/non-inverting input as it leads to better common mode rejection which leads to better performance without altering the disclosed invention and leads to the same predictable results of the disclosed invention.
Oswal and Lumsden do not disclose the node being arranged between the resistor and the second resistor.
Sutardja discloses, in Figure 24, a second resistor (2410) and the node (514 and 2410 connection node) being arranged between the resistor (2410) and the second resistor (514).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to add the resistor (2410) taught by Sutardja with the feedback paths taught by Oswal and Lumsden in order to achieve higher values of gain or bandwidth (or both) (Sutardja Column 4: lines 64-65).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), and Sutardja (US 7,173,486) as applied to claims 1 and 7 above, and further in view of Chibana (US 3,715,675).
In regard to Claim 3:
Oswal, Lumsden, and Sutardja disclose electrical circuit according to claim 1, but do not teach wherein the resistor, the first resistor, and the second resistor is a transistor in which a gate-source voltage is greater than a threshold voltage of the transistor and a gate-drain volage is greater than or equal to the threshold voltage of the transistor.
Chibana discloses, in Figure 1, wherein each of the resistor, the first resistor, and the second resistor is a transistor (a transistor FET used as a resistor operating in the triode region) in which a gate-source voltage is greater than the threshold voltage of the transistor and a gate-drain voltage is greater than or equal to the threshold voltage of the transistor (Column 1: lines 18-45).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the transistor taught by Chibana with the resistors taught by Oswal, Lumsden, and Sutardja, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), and Sutardja (US 7,173,486) as applied to claims 1 and 7 above, and further in view of Wu (US 2022/0278661).
In regard to Claim 4:
Oswal, Lumsden, and Sutardja disclose the electrical circuit according to claim 1, but do not teach wherein the first operational amplifier includes a differential amplifier with a first transistor and a second transistor, a first current mirror, with a fifth transistor, a sixth transistor, a seventh transistor, and an eight transistor, and a cascode circuit with a ninth transistor and a tenth transistor.
Wu discloses, in Figure 3, wherein the first operational amplifier (figure 3) includes a differential amplifier (figure 3) with a first transistor (M3) and a second transistor (M4), a first current mirror (M7-M10, figure 3), with a fifth transistor (M7), a sixth transistor (M8), a seventh transistor (M9), and an eight transistor (M10), and a cascode circuit with a ninth transistor (M12) and a tenth transistor (M13).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the transistors taught by Wu with the operational amplifier taught by Oswal, Lumsden, and Sutardja, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), and Sutardja (US 7,173,486) as applied to claims 1 and 7 above, and further in view of Kusuda (US 2022/0360725).
In regard to Claim 5:
Oswal, Lumsden, Sutardja disclose the electrical circuit according to claim 1, but do not teach wherein the second operational amplifier, includes a thirteenth transistor, a fourteenth transistor and a second current mirror with a fifteenth transistor and a sixteenth transistor.
Kusuda discloses, in Figure 4, wherein the second operational amplifier (figure 4), includes a thirteenth transistor (MN1), a fourteenth transistor (MN2) and a second current mirror with a fifteenth transistor (MP1) and a sixteenth transistor (MP2).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the transistors taught by Wu with the operational amplifier taught by Oswal, Lumsden, and Sutardja, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), and Sutardja (US 7,173,486) as applied to claim 1 above, and further in view of Griffith (US 2012/0293263).
In regard to Claim 6:
Oswal, Lumsden, and Sutardja disclose electrical circuit according to claim 1, but do not teach wherein the third operational amplifier includes a seventeenth transistor and an eighteenth transistor.
Griffith discloses, in Figure 2, an electrical circuit according to claim 1, wherein the third operational amplifier (figure 2) includes a seventeenth transistor (Q1) and an eighteenth transistor (Q2).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the transistors taught by Wu with the operational amplifier taught by Oswal, Lumsden, and Sutardja, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oswal (US 2005/0174171), Lumsden (US 5,481,225), Sutardja (US 7,173,486), and Scuderi (US 9,160,376).
In regard to Claim 8:
Oswal discloses, in Figure 1, an electrical circuit, comprising:
a first operational amplifier (110); and a first output, a second operational amplifier (120), including at least one second non-inverting input (120 input, paragraph 15 line 5) and a second output (120 output); a third operational amplifier(130) including at least one third inverting input (-gm3, 130 input) and third output (130 output); a feedback path (150) including a series circuit including a second resistor (Rm2) and a second capacitor (Cm2); wherein the feedback path (150) is arranged between the third output (130 output) and at least one third inverting input (150 is connected between the 130 input and output) and a first feedback path (160) including a first series circuit including a first resistor (Rm1) and a first capacitor (Cm1) wherein the first feedback path (160) is arranged between a node (150 and 160 connection node) and at least one second non-inverting input (120 input).
Oswal does not disclose the first non-inverting input and first inverting input, a second resistor, and the node being arranged between the resistor and the second resistor.
Lumsden discloses, in Figure 5, the inverting and non-inverting input (VA, VB).
It would have been obvious to one having ordinary skill in the art, at the time of the effective filing date of the application, to use an inverting and non-inverting inputs to the operational amplifier as taught by Lumsden with the operational amplifier taught by Oswal, instead of a single inverting/non-inverting input as it leads to better common mode rejection which leads to better performance without altering the disclosed invention and leads to the same predictable results of the disclosed invention.
Oswal and Lumsden do not disclose the node being arranged between the resistor and the second resistor.
Sutardja discloses, in Figure 24, a second resistor (2410) and the node (514 and 2410 connection node) being arranged between the resistor (2410) and the second resistor (514).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to add the resistor (2410) taught by Sutardja with the feedback paths taught by Oswal and Lumsden in order to achieve higher values of gain or bandwidth (or both) (Sutardja Column 4: lines 64-65).
Oswal, Lumsden, and Sutardja do not disclose the method comprising: operating the electrical circuit in a first operating mode, which delivers a high stability; and operating the electrical circuit in a second operating mode, which delivers a low consumption.
Scuderi discloses the method comprising: operating the electrical circuit in a first operating mode, which delivers a high stability (Column 3: lines 36-44, where the stability is improved in the APT mode); and operating the electrical circuit in a second operating mode, which delivers a low consumption (Column 3: lines 30-36, where in the ET mode the power supply voltage varies to an envelope of the input signal; Column 4: lines 25-28).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the operation method taught by Scuderi with the circuit taught by Oswal, Lumsden, and Sutardja, in order to dynamically stabilize the amplifier under changing operating condictions (Scuderi Abstract).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 2:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the third operational amplifier has a third transconductance gm3, and the resistor has a value which is substantially inversely proportional to the third transconductance gm3, and a sum of the value of resistor and a value of the second resistor is greater than 1/gm3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN W POOS/Primary Examiner, Art Unit 2843
Prosecution Insights