DETAILED ACTION
Claims 1-21 are presented for examination, of which, claims 18-21 are withdrawn from further consideration pursuant to 35 CFR 1.142(b) as being drawn to a nonelected election. Election was made without traverse during the response filed on 04-02-2026.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1 are independent claims. Claims 2-17 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 09-10-2024.
Priority
This application is a continuation in part (CIP), that contains some subject matter disclosed in Application with S/N 17/357,861, while at the same time, also adds new subject matter that not presented in the prior application. Because of this, a priority date of June 10, 2024 for at least the following expressions directed to: a controller configured to provide one or more driving signals adapted to operate a converter circuit to charge a plurality of sets of storage capacitors during the normal operation and to provide the bus voltage from energy stored in at least one operational set of storage capacitors of the plurality of sets of storage capacitors in the event of power loss.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09-10-2024 is in compliance with the provisions of 37 CFR 1.97
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2 as being anticipated by) unpatentable over U.S. Publication No. 2018/0323699 (hereinafter, “Carpenter JR.”).
As per claim 1, Carpenter JR. discloses an integrated circuit (IC) chip for providing power loss protection, the IC chip comprising:
an input pin adapted to be configured to receive an input voltage from a power source; (Fig 2A illustrates an AC-to-DC adapter 3 to receive power from AC source 32. It would be apparent to a person having ordinary skill that AC-to-DC power adapter is plugged into a wall outlet having at least 2 pins)
an output pin adapted to be configured to provide a bus voltage; (Fig. 2A further illustrates how the AC-to-DC adapter 3 is outputting 19.5 VDC to the SSD device 2 by plugging its plug portion 30 and 31 into the socket portion 12 and 13 of the SSD device)
a disconnect circuit (efuse; Fig 1 ) coupled between the input pin and the output pin (Fig 1 illustrates an efuse that is coupled between Vin 203 and VOUT to voltage regulator 207.boost 205) and configured to connect the input voltage at the input pin to the output pin in a normal operation when the power source provides the input voltage, (during normal operation, for example, when power cord is not disconnected Vin is provided to rest of the circuits; Fig 1) and to disconnect the input pin from the output pin in an event of power loss when the power source no longer provides the input voltage; and (Fig. 1 further illustrates that when VIN at input 203 is then suddenly lost, for example, due to a condition like a power brown out condition or a power cord disconnection event, then the eFuse turns off immediately and the fault signal is asserted that causes the second switch SW2 202 responds by turning on. Because of that, switch SW1 is turned to an open state during this power loss event )
a controller configured to provide one or more driving signals (power failure detection circuit to provide enable (EN) signal to boost 205) adapted to operate a converter circuit to charge a plurality of sets of storage capacitors during the normal operation (Fig 1 illustrates Vin power is provided to boost 205 to power capacitors 206) and to provide the bus voltage from energy stored in at least one operational set of storage capacitors of the plurality of sets of storage capacitors in the event of power loss. (¶ [0003] discloses “the capacitance of the capacitors must be large enough that the energy stored in the capacitors can sustain system power long enough to allow the device to complete a safe power-off sequence involving backup of configuration information and status after a loss of VIN is detected” )
As per claim 2, Carpenter JR. discloses an IC chip wherein the controller is configured to provide a first driving signal that is adapted to control a first transistor of the converter circuit, and a second driving signal that is adapted to control a second transistor of the converter circuit. (Fig. 1 illustrates a power detection circuits that is responsible for driving SW1 and SW2 to ON/OFF states)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2018/0323699 (hereinafter, “Carpenter JR.”) in view of U.S. Patent No. 11,824,345 (hereinafter, “Ramadass”).
As per claim 3, Carpenter JR. does not distinctly disclose an IC chip wherein the disconnect circuit comprises a third transistor having a first terminal that is connected to the input pin and a second terminal that is connected to the output pin.
However, Ramadass explicitly discloses wherein the disconnect circuit comprises a third transistor having a first terminal that is connected to the input pin and a second terminal that is connected to the output pin. (Fig. 1 illustrates a protection devices having 4 transistors for controlling Vin and Vout)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Carpenter JR. and Ramadass because both references are in the same field of endeavor. Ramadass’s teaching of 3 or more transistors would enhance Carpenter JR. 's system by limiting current and voltages to safe levels for loads, thus improving circuit protection.
As per claim 4, Carpenter JR. as modified discloses an IC chip the disconnect circuit further comprises a fourth transistor having a first terminal that is connected to the output pin and a second terminal, and wherein the second terminal of the third transistor is connected to the second terminal of the fourth transistor instead of the output pin. (Fig. 1 illustrates a protection devices having 4 transistors for controlling Vin and Vout)
Claims 5-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2018/0323699 (hereinafter, “Carpenter JR.”) in view of U.S. Publication No. 2018/0308527 (hereinafter, “Narayanan”).
As per claim 5, Carpenter JR. discloses an IC chip urther comprising a node that is configured to be connected to the converter circuit, and that is further adapted to be coupled to the plurality of sets of storage capacitors via a plurality of blocking circuits, wherein each blocking circuit of the plurality of blocking circuits and a corresponding set of storage capacitors of the plurality of sets of storage capacitors. (SW2 and SW1 for controlling the groups of capacitors 206)
Carpenter JR. does not disclose where each of the plurality of blocking circuits, wherein each blocking circuit of the plurality of blocking circuits is coupled between the node and a corresponding set of storage capacitors of the plurality of sets of storage capacitors.
However, Narayanan explicitly discloses where each of the plurality of blocking circuits, wherein each blocking circuit of the plurality of blocking circuits is coupled between the node and a corresponding set of storage capacitors of the plurality of sets of storage capacitors. (Fig 2 illustrates a controller controlling switches 228 to a plurality of capacitors independently )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Carpenter JR. and Narayanan because both references are in the same field of endeavor. Narayanan’s teaching of controlling independently each capacitor would enhance Carpenter JR. 's system by controlling the amount of backup power in a more fined tuned manner.
As per claim 6, Carpenter JR. as modified discloses an IC chip wherein each blocking circuit of the plurality of blocking circuits connects the corresponding set of storage capacitors to the node while the corresponding set of storage capacitors remains operational and disconnects the corresponding set of storage capacitors from the node in an event of a failure of the corresponding set of storage capacitors. (Narayanan: Fig 2 illustrates a controller controlling switches 228 to a plurality of capacitors independently )
As per claim 7, Carpenter JR. as modified discloses an IC chip wherein the node is inside the IC chip, and wherein the IC chip further includes the plurality of blocking circuits. (Narayanan: Fig 2 illustrates a controller controlling switches 228 to a plurality of capacitors independently )
As per claim 8, Carpenter JR. as modified discloses an IC chip further comprising: a plurality of storage pins, each blocking circuit of the plurality of blocking circuits is coupled between the node and a corresponding storage pin of the plurality of storage pins, (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins; Fig 2)
wherein the corresponding storage pin is configured to be connected to the corresponding set of storage capacitors of the plurality of sets of storage capacitors. (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins; Fig 2)
As per claim 9, Carpenter JR. as modified discloses an IC chip wherein the node is embodied as a pin of the IC chip, and wherein the plurality of blocking circuits are provided from outside the IC chip. (SCarpenter JR. : Fig 2 illustrates SW1/SW2 are not integrated within eFUSE) & (Narayanan: switches 228 are not integrated with eFuse or controller 210; Fig. 2)
As per claim 10, Carpenter JR. as modified discloses an IC chip further comprising: a plurality of control pins, each control pin of the plurality of control pins is adapted to output a control signal for controlling a corresponding blocking circuit of the plurality of blocking circuits. (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins for which control signals are transmitted; Fig 2)
As per claim 11, Carpenter JR. as modified discloses an IC chip wherein each blocking circuit of the plurality of blocking circuits comprises a controllable pass device or a controllable switch device having a first terminal configured to be connected to the node, a second terminal configured to be connected to the corresponding set of storage capacitors and a control terminal used to control the controllable pass device or the controllable switch device ON or OFF. (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins for which independent control signals are transmitted; Fig 2)
As per claim 12, Carpenter JR. as modified discloses an IC chip wherein the converter circuit is operated to generate a storage voltage from the input voltage or the bus voltage to charge the plurality of sets of storage capacitors during the normal operation, and wherein the converter circuit is operated to provide the bus voltage from the storage voltage that is powered from the energy stored in the at least one operational set of storage capacitors in the event of power loss. (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins for which independent control signals are transmitted to provide back up power; Fig 2) & ( Carpenter JR. : Fig. 1 further illustrates that when VIN at input 203 is then suddenly lost, for example, due to a condition like a power brown out condition or a power cord disconnection event, then the eFuse turns off immediately and the fault signal is asserted that causes the second switch SW2 202 responds by turning on. Because of that, switch SW1 is turned to an open state during this power loss event )
As per claim 13, Carpenter JR. as modified discloses an IC chip wherein the converter circuit includes:a first transistor having a first terminal that is connected to a switch node and a second terminal that is coupled to a node adapted to be coupled to the plurality of sets of storage capacitors; anda second transistor having a first terminal that is connected to ground and a second terminal that is connected to the switch node. (Narayanan: nodes for each storage capacitors are coupled with GPIOs Pins for which independent control signals that are transmitted to plurality of switches 228 to provide back up power; Fig 2) & ( Carpenter JR. : Fig. 1 further illustrates that when VIN at input 203 is then suddenly lost, for example, due to a condition like a power brown out condition or a power cord disconnection event, then the eFuse turns off immediately and the fault signal is asserted that causes the second switch SW2 202 responds by turning on. Because of that, switch SW1 is turned to an open state during this power loss event )
As per claim 14, Carpenter JR. as modified discloses an IC chip wherein the first transistor and the second transistor are integrated in the IC chip. (Narayanan: Switches 228 are integrated within storage device; Fig 2)
As per claim 15, Carpenter JR. as modified discloses an IC chip the first transistor and the second transistor are placed outside the IC chip. (Narayanan: Switches 228 are not integrated eFuse/controller ; Fig 2)
As per claim 17, Carpenter JR. as modified discloses an IC chip wherein the controller is further configured to generate a plurality of control signals based on signals indicative of failed sets of storage capacitors of the plurality sets of storage capacitors, and wherein the plurality of control signals are configured to control a disconnection of the failed sets of storage capacitors from the at least one operational sets of storage capacitors. (¶ [0010] discloses peak power requirements even when one or more capacitors/banks fail by controlling each of the switching components 228 independently either directly or through a multiplexer circuit (MUX) (not shown). Fig 2)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2018/0323699 (hereinafter, “Carpenter JR.”) in view of U.S. Publication No. 2018/0308527 (hereinafter, “Narayanan”) and further view of U.S. Publication No. 2022/0224225 (hereinafter, “Chen”).
As per claim 16, Carpenter JR. as modified does not distinctly disclose an IC chip wherein an inductor is coupled between the switch node and the output pin.
However, Chen explicitly discloses an IC chip wherein an inductor is coupled between the switch node and the output pin.(inductor coupled to surge protection circuit where voltages with phases A-C; Fig3)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Carpenter JR.as modified and Chen because all references are in the same field of endeavor. Chen’s teaching of inductor coupled to surge protection circuit where voltages with phases A-C would enhance Carpenter JR. 's as modified system by preventing surges, thus enhancing circuit design by smoothing power supplied.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
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