DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/08/2026 has been entered.
Claims 1, 3, 14, and 20 have been amended. Claims 1-2, 5-7, 14-19, and 21 are pending.
Applicants' arguments with respect to claims 1-2, 5-7, 14-19, and 21 have been considered
but are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 14-19, and 21 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ryu et al. "herein Ryu" (U.S. PN: 11,508,456) in view of Fisch et al. "herein" (U.S. PN: 8,064,274) further in view of an Official Notice.
As per claims 1 and 14:
An apparatus and a method comprising: a memory bank comprising: a first column plane
comprising a first number of a first plurality of bit lines associated with a column select signal;
and a second column plane comprising a second number of a second plurality of bit lines
associated with the column select signal, wherein first plurality of bit lines includes a different
number of bit lines than the second plurality of bit lines (see col. 5, lines 42-67 to col. 6, lines 1-
16) and a column decoder configured to provide the column select signal and activate the first
plurality of bit lines in the first column plane and the second number of the second plurality of
bit lines in the second colunm plane, wherein the first column plane is configured to store data
and the second column plane is configured to store parity bits, wherein a size of the first column plane is lager than a size of the second column plane (see col. 5, lines 42-67 to col. 6,
lines 1-46 and see col. 11, lines 7-63).
Ryu substantially teaches the claimed invention described in claim 1 (as indicated above).
However, Fisch does not explicitly teach wherein the first plurality of bit lines includes a
different number of bit lines than the second plurality of bit lines
Fisch, in an analogous art, teaches wherein the first plurality of bit lines includes a
different number of bit lines than the second plurality of bit lines (see col. 5, lines 25-30 and col.
6, lines 15-20). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ryu with the teachings of Fisch by including the first plurality of bit lines having a different number of bit lines than the second plurality of bit
lines. This modification would have been obvious to one of ordinary skill in the art, before the
effective filing date of the invention because one of ordinary skill in the art would have
recognized that by including the first plurality of bit lines having a different number of bit lines
than the second plurality of bit lines would increase the flexibility of a column repair operation and repairing block fail. (see col. 14, lines 1-4 and col. 21, lines 41-44).
The combination Ryu and Fisch do not explicitly teach that the size of the first column plane is larger than the size of the second column plane. However, the examiner takes an Official Notice that it would have been obvious to one of ordinary skill in the art that the parity bits which are configured to be stored in the second column plane are typically much smaller than the data configured to be stored in the first column plane. For example, in RAID systems, parity is stored in a separate disk or memory location and is not as large as the data columns. This would have been obvious because the well-established in the art use different column plane sizes such as lager column plane for storing data and smaller column plane for storing parity bits and in addition to that parity bits are known to be extra bits added to the data for detecting or correcting errors.
As per claim 2:
Ryu and Fisch in the above rejection teach an error correction code (ECC) circuit
configured to detect and correct an error based on the data and the parity bits (see col. 6, lines
38-46).
As per claim 5:
Ryu and Fisch in the above rejection teach a third column plane including the first
number of a third plurality of bit lines associated with a column signal associated with a
defective memory cell in one of the first column plane and the second column plane, wherein the
third plurality of bit lines has the same number of bit lines as the first plurality of bit lines (see
col. 4, lines 63-67 to col. 4, lines 1-31 in Ryu and (see col. 5, lines 25-30 and col. 6, lines 15-20
in Fisch).
As per claim 6:
Ryu and Fisch in the above rejection teach wherein the first number of the plurality of bit
lines activated by the column select signal is greater than the number of the second plurality of
bit lines activated by the column select signal (see col. 8, lines 10-25 and col. 11, lines 7-63 in
Ryu).
As per claim 7:
Ryu and Fisch in the above rejection teach wherein the first plurality of bit lines includes
eight bit lines and the second plurality of bit lines includes six bit lines first number is 8 and the
second number is 6 (see col. 8, lines 10-25 and col. 11, lines 7-63 in Ryu and (see col. 5, lines
25-30 and col. 6, lines 15-20 in Fisch).
As per claim 15:
Ryu and Fisch in the above rejection teach locating an error, correcting the error, or
combinations thereof in the first plurality of bit lines in the first column plane based on the
second plurality of bit lines with an error correction code (ECC) circuit (see figure 18 element
col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
As per claim 16:
Ryu and Fisch in the above rejection teach wherein the access operation is a read
operation, the read operation comprises: amplifying, by a sense amplifier, read data from a bit
line of the first plurality of bit lines in the first column plane; transferring the amplified read data
to an input/output circuit via the ECC circuit (see col. 18, lines 33-67 to col. 19, lines 1-18 in
Ryu).
As per claim 17:
Ryu and Fisch in the above rejection teach wherein the access operation is a write
operation, the write operation comprises: transferring write data from the ECC circuit; and
writing the write data in a memory cell coupled to an associated bit line of the first plurality of
bit lines in the first column plane (see col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
As per claim 18:
Ryu and Fisch in the above rejection teach wherein the write operation further comprises:
generating parity bits based on the write data; and providing the parity bits by the ECC circuit to
the memory cell (see col. 20, lines 58-67 in Ryu).
As per claim 19:
Ryu and Fisch in the above rejection teach wherein the first number of bit lines included
in the first plurality of bit lines is greater than the second number of bit lines included in the
second plurality of bit lines (see col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
Allowable Subject Matter
Claims 3, 4, and 20 are allowed.
Claims 8-13 were previously allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights