DETAILED ACTION
FINAL REJECTION
Applicants' response filed 02/03/26 has been considered.
Claims 1, 5-7 and 14, 19-20 have been amended. Claims 1-20 are pending.
Rejections under 35 USC 101 and 112 are withdrawn in light of amendments.Applicants' arguments with respect to claims 1-2, 5-7 and 14-19 have been considered but are moot in view of new grounds of rejection (Rye et al in view of Fisch et al.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 and 14-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ryu et al. "herein Ryu” (U.S. PN: 11,508,456) in view of Fisch et al. “herein” (U.S. PN: 8,064,274).
As per claims 1 and 14:
An apparatus and a method comprising: a memory bank comprising: a first column plane comprising a first number of a first plurality of bit lines associated with a column select signal; and a second column plane comprising a second number of a second plurality of bit lines associated with the column select signal, wherein first plurality of bit lines includes a different number of bit lines than the second plurality of bit lines (see col. 5, lines 42-67 to col. 6, lines 1-16) and a column decoder configured to provide the column select signal and activate the first plurality of bit lines in the first column plane and the second number of the second plurality of bit lines in the second colunm plane, wherein the first column plane is configured to store data and the second column plane is configured to store parity bits (see col. 5, lines 42-67 to col. 6, lines 1-46 and see col. 11, lines 7-63).
Ryu substantially teaches the claimed invention described in claim 1 (as indicated above).
However, Fisch does not explicitly teach wherein the first plurality of bit lines includes a different number of bit lines than the second plurality of bit lines
Fisch, in an analogous art, teaches wherein the first plurality of bit lines includes a different number of bit lines than the second plurality of bit lines (see col. 5, lines 25-30 and col. 6, lines 15-20).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ryu with the teachings of Fisch by including the first plurality of bit lines having a different number of bit lines than the second plurality of bit lines.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that by including the first plurality of bit lines having a different number of bit lines than the second plurality of bit lines would
As per claim 2:
Ryu and Fisch in the above rejection teach an error correction code (ECC) circuit
configured to detect and correct an error based on the data and the parity bits (see col. 6, lines
38-46).
As per claim 5:
Ryu and Fisch in the above rejection teach a third column plane including the first number of a third plurality of bit lines associated with a column signal associated with a defective memory cell in one of the first column plane and the second column plane, wherein the third plurality of bit lines has the same number of bit lines as the first plurality of bit lines (see col. 4, lines 63-67 to col. 4, lines 1-31 in Ryu and (see col. 5, lines 25-30 and col. 6, lines 15-20 in Fisch).
As per claim 6:
Ryu and Fisch in the above rejection teach wherein the first number of the plurality of bit lines activated by the column select signal is greater than the number of the second plurality of bit lines activated by the column select signal (see col. 8, lines 10-25 and col. 11, lines 7-63 in Ryu).
As per claim 7:
Ryu and Fisch in the above rejection teach wherein the first plurality of bit lines includes eight bit lines and the second plurality of bit lines includes six bit lines first number is 8 and the second number is 6 (see col. 8, lines 10-25 and col. 11, lines 7-63 in Ryu and (see col. 5, lines 25-30 and col. 6, lines 15-20 in Fisch).
As per claim 15:
Ryu and Fisch in the above rejection teach locating an error, correcting the error, or
combinations thereof in the first plurality of bit lines in the first column plane based on the
second plurality of bit lines with an error correction code (ECC) circuit (see figure 18 element
col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
As per claim 16:
Ryu and Fisch in the above rejection teach wherein the access operation is a read operation, the read operation comprises: amplifying, by a sense amplifier, read data from a bit line of the first plurality of bit lines in the first column plane; transferring the amplified read data to an input/output circuit via the ECC circuit (see col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
As per claim 17:
Ryu and Fisch in the above rejection teach wherein the access operation is a write operation, the write operation comprises: transferring write data from the ECC circuit; and writing the write data in a memory cell coupled to an associated bit line of the first plurality of bit lines in the first column plane (see col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
As per claim 18:
Ryu and Fisch in the above rejection teach wherein the write operation further comprises:
generating parity bits based on the write data; and providing the parity bits by the ECC circuit to
the memory cell (see col. 20, lines 58-67 in Ryu).
As per claim 19:
Ryu and Fisch in the above rejection teach wherein the first number of bit lines included in the first plurality of bit lines is greater than the second number of bit lines included in the second plurality of bit lines (see col. 18, lines 33-67 to col. 19, lines 1-18 in Ryu).
Allowable Subject Matter
Claims 8-13 were previously allowed.
Claims 3, 4, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111 (c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112