DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species 1 directed to claims 1-13 in the reply filed on 5/4/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “antenna” and “plurality of apertures are defined in one or more of the walls or the roof” as described in claims 12 and 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ono et al. (US PG. Pub. 2005/0168961).
Regarding claim 1 – Ono teaches an electronic module (fig. 23) comprising: a printed circuit board (PCB) stack-up (30 [paragraph 0082] Ono states, “circuit board 30”) including at least one electrically conductive layer (120 [paragraph 0086] Ono states, “ First circuit board 20 and second circuit board 30 are each formed of electrodes 120, conductive via holes (hereinafter referred to as via hole) 130 and insulating members 140”) and a plurality of electrically non-conductive layers (140), the PCB stack-up (30) having a first surface (top surface) and a second surface (bottom surface) reverse of the first surface (see fig. 23), the PCB stack-up (30) defining a first plurality of bond pads (see bond pads connected to components 160 and connected to walls 490) on the first surface (top surface of 30); a plurality of walls (490, see four walls of as shown in figure 24B [paragraph 0156] Ono states, “relay frame 490”), each wall defining a first end (bottom surface of frame 490) and a second end (top surface of frame 490) reverse of the first end (see fig. 23), the first end of each wall mounted to the first plurality of bond pads (see bond pads connected between 490 and 30), the plurality of walls extending outward from the first surface and defining an interior cavity (see cavity having components 160 and 150 thereon) between opposing surfaces of the plurality of walls (claimed structure shown in figure 23); and a roof (20 [paragraph 0155] Ono states, “circuit board 20”) attached to the second end (top surface of 490) of each wall, the roof (20) extending over the interior cavity parallel to the first surface (see fig. 23), the roof (20) defining a third surface (bottom surface of 20) opposing the first surface (top surface of 30) of the PCB stack-up (30), the roof (20) defining a fourth surface (top surface of 20) that is reverse of the third surface, wherein the interior cavity is an enclosed space defined by the first surface, the third surface of the roof (20), and the opposing surfaces of the plurality of walls (490; claimed structure shown in figure 23).
Regarding claim 2 – Ono teaches the electronic module of claim 1, wherein the plurality of electrically non-conductive layers (fig. 23, 140) of the PCB stack-up (30) are composed of cured resin ([paragraph 0087] Ono states, “First circuit board 20 and second circuit board 30 can be made of general resin”).
Regarding claim 3 – Ono teaches the electronic module of claim 1, comprising a semiconductor die (fig. 23, 160 [paragraph 0086] Ono states, “electric components 150 and 160 are general passive components such as semiconductor elements including ICs and LSIs, resistors, capacitors and inductors. Alternatively, it is possible to mount bare chip electronic components by flip chip mounting or wire bonding connection”) mounted to the first surface (top surface of 30) of the PCB stack-up (30) in the interior cavity (claimed structure shown in figure 23).
Regarding claim 4 – Ono teaches the electronic module of claim 1, wherein the roof (fig. 23, 20) defines a third plurality of bond pads (bond pads shown on lower surface of roof 20) on the third surface, wherein the roof (20) is attached to the second end (top surface of wall 490) of each wall with conductive adhesive (40 [paragraph 0082] Ono states, “Connection members 40 can be solder balls, micro connectors, heat seal connectors, anisotropic conductive films, soldering bumps or other kinds of bumps”) bonding the third plurality of bond pads to the second end of each wall (claimed structure shown in figure 23).
Regarding claim 6 – Ono teaches the electronic module of claim 1, wherein the plurality of walls (fig. 23, 490) include at least one conductive via (500 [paragraph 0154] via holes 500) extending from the first end (bottom surface of wall 490) to the second end (top surface of wall 490) of a wall of the plurality of walls (490), the at least one conductive via (500) coupled to at least one circuit feature (connected to circuit features 120 & 130 of the PCB stack-up 30) of the at least one electrically conductive layer (120) of the PCB stack-up (30) and coupled to at least one circuit feature (circuit feature 120 & 130 of roof 20) of the roof (20).
Regarding claim 7 – Ono teaches the electronic module of claim 6, wherein the circuit features (fig. 23, circuit feature 120 & 130 of roof 20) of the roof (20) include at least one conductive via (130) extending from the third surface (bottom surface of 20) to the fourth surface (top surface of 20), the at least one conductive via (130) of the roof (20) electrically coupled to the at least one conductive via (500) in the plurality of walls (490).
Regarding claim 8 – Ono teaches the electronic module of claim 7, wherein the roof (fig. 23, 20) includes a fourth plurality of bond pads (see bond pads on top surface of roof 20) on the fourth surface (top surface of roof 20), the fourth plurality of bond pads electrically coupled to the at least one conductive via (130) in the roof (20).
Regarding claim 9 – Ono teaches the electronic module of claim 6, comprising a semiconductor die (fig. 23, component 150 mounted on bottom surface of roof 20 [paragraph 0086] Ono states, “electric components 150 and 160 are general passive components such as semiconductor elements including ICs and LSIs, resistors, capacitors and inductors. Alternatively, it is possible to mount bare chip electronic components by flip chip mounting or wire bonding connection”) mounted to the third surface (bottom surface of roof 20) of the roof (20), wherein the circuit features of the roof (20) include traces (120) electrically coupling the semiconductor die (150) to the at least one conductive via (500) in the plurality of walls (490 [paragraph 0154] Ono states, “The electrodes of first circuit board 20 and the electrodes of second circuit board 30 are connected with each other electrically and mechanically through connection members 40, and via holes 500”).
Regarding claim 11 – Ono teaches the electronic module of claim 1, wherein the roof (fig. 23, 20) is a PCB stack-up comprising at least one electrically conductive layer (120) and a plurality of electrically non-conductive layers (140 [paragraph 0086] Ono states, “First circuit board 20 and second circuit board 30 are each formed of electrodes 120, conductive via holes (hereinafter referred to as via hole) 130 and insulating members 140”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. in view of Isaak (US PG. Pub. 2001/0054758).
Regarding claim 5 – Ono teaches the electronic module of claim 1, but fails to teach wherein the roof is attached to the second end of each wall with cured resin.
Isaak teaches an electronic module (figs. 1-3, 10) wherein the roof (upper layer 12 [paragraph 0038] Isaak states, “base layer 12”) is attached to the second end (upper end of wall 34) of each wall (34 [paragraph 0037] Isaak states, “interconnect frame 34”) with cured resin (49 [paragraph 0037] Isaak states, “The anisotropic epoxy 49 comprises a fast cure epoxy component 50 which contains small conductive particles 51 uniformly dispersed there within”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electronic module having a die within an internal cavity formed by a PCB, roof and plurality of walls as taught by Ono with the roof being attached second end of each wall with cured resin as taught by Isaak because Isaak states regarding the anisotropic epoxy, “By controlling the size of the particles, bridging between adjacent pads can be eliminated, thus allowing for the achievement of fine pitch between the pads. Since flux is not used, post assembly cleaning is not required. Also, the composition of the particles does not include any toxic metal such as lead” [paragraph 0010].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. in view of Ha et al. (US PG. Pub. 2022/0256705).
Regarding claim 10 – Ono teaches the electronic module of claim 6, but fails to teach wherein each wall is a PCB stack-up comprising multiple non-conductive layers, each non-conductive layer defining a pad thereon and a conductive via extending from the pad to a pad of an adjacent non-conductive layer.
Ha teaches wherein each wall (fig. 14A, 1400A [paragraph 0136] Ha states, “The interposer may include: a first region 1400B having a first height (hb) and including the first layer 1401; and a second region 1400A having a second height (ha)”) is a PCB stack-up comprising multiple non-conductive layers (1401 & 1411 [paragraph 0133] Ha states, “the first layer 1401 and the second layer 1411”), each non-conductive layer (1401 & 1411) defining a pad (1407 & 1417 [paragraph 0132 & 0133] Ha state, “first conductive pads 1407…second conductive pad 1417”) thereon and a conductive via (1405 & 1415 [paragraph 0133] Ha states, “conductive members 1405…conductive member 1415”) extending from the pad (1407) to a pad (1417)of an adjacent non-conductive layer (1411).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electronic module having a die within an internal cavity formed by a PCB, roof and plurality of walls as taught by Ono with each wall is a PCB stack-up including inner pads and vias that connected between non-conductive layers as taught by Ha because this additional circuitry will increase the wiring density of the electronic module allowing for increased bandwidth between the roof/second PCB and the PCB stack-up.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. in view of Ajioka et al. (US PG. Pub. 2004/0264156).
Regarding claim 12 – Ono teaches the electronic module of claim 1 having a die within an internal cavity (see rejection to claim 1 above), but fails to teach comprising an antenna in or on the roof, the antenna electrically coupled to a component disposed in the internal cavity.
Ajioka teaches an electronic module (fig. 1, 10 [paragraph 0020] Ajioka states, “the electronic component module 10”) comprising an antenna (18 [paragraph 0037] Ajioka states, “patch antennas 18”) in or on the roof (11a), the antenna (18) electrically coupled ([claim 2] Ajioka states, “said antenna is connected to said corresponding electronic components”) to a component (17 [paragraph 0024] Ajioka states, “electronic components 17”) disposed in the internal cavity (16 [paragraph 0022] Ajioka states, “cavities 16”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electronic module having a die within an internal cavity formed by a PCB, roof and plurality of walls as taught by Ono with an antenna on the roof and electrically coupled to a component disposed in the internal cavity as taught by Ajioka because Ajioka states, “t the one or more antennas transmit/receive radio waves in at least any one of the first frequency band and the second frequency band, the one or more antennas connected to the corresponding electronic components” [paragraph 0009]. The antenna feature will allow for wireless communication increasing the portability of the electronic module.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. in view of Lee et al. (US PG. Pub. 2024/0015881).
Regarding claim 13 – Ono teaches the electronic module of claim 1, but fails to teach wherein a plurality of apertures are defined in one or more of the walls or the roof for circulating liquid into and out of the internal cavity.
Lee teaches an electronic module (fig. 2d, 100) wherein a plurality of apertures (136 & 138 [paragraph 0023] Lee states, “inlet fitting 136…outlet fitting 138”) are defined in one or more of the walls or the roof (102 [paragraph 0023] Lee states, “PCB 102”) for circulating liquid (coolant [paragraph 0024] Lee states, “cooling liquid is used. The PCB assembly can also support cryogenic coolant in the cooling passage 108”) into and out of the internal cavity (108 [paragraph 0023] Lee states, “colling path 108 for ingress of coolant from an external source into the cooling path 108”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electronic module having a die within an internal cavity formed by a PCB, roof and plurality of walls as taught by Ono with the roof having a plurality of apertures for circulating liquid coolant into and out of the internal cavity as taught by Lee because Lee states, “The systems and methods described herein can be used to provide cooling of heat generating components included with PCBs” [paragraph 0018].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
IIDA et al. (US PG. Pub. 2020/0205289) discloses an interposer and electronic device.
Wimmer (US PG. Pub. 2008/0278922) discloses a hardware protection system for sensitive electronic-data modules protecting against external manipulations.
Kato et al. (US PG. Pub. 2024/0179843) discloses an electronic circuit board.
Ha et al. (US PG. Pub. 2021/0014970) discloses an electronic device including interposer.
Cheng (US PG. Pub. 2013/0201648) discloses a stacked substrate structure.
Sadineni et al. (US PG. Pub. 2024/0387345) discloses a circuit board device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Prosecution Insights