Prosecution Insights
Last updated: July 17, 2026
Application No. 18/738,803

SYSTEMS AND METHODS FOR LOW-POWER FULLY DIGITAL RATE CONVERSION USING PRE- OR POST- JITTER NOISE REDUCTION

Final Rejection §103
Filed
Jun 10, 2024
Priority
Jun 27, 2023 — provisional 63/510,606
Examiner
SHIBEROU, MAHELET
Art Unit
2171
Tech Center
2100 — Computer Architecture & Software
Assignee
Qorvo US Inc.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
423 granted / 576 resolved
+18.4% vs TC avg
Strong +27% interview lift
Without
With
+26.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
601
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
90.6%
+50.6% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 576 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the Amendment filed on 3/19/2026. Claims 1-20 are pending in the case. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20110224996, hereinafter Wang) in view of Perez Lara et al. (US 20230422062 A1, hereinafter Perez Lara). As to independent claim 1, Wang teaches a method for digital audio conversion (“Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time.” abstract) comprising: receiving, at a first sampling rate, a digital audio data stream at a device (“An encoded digital signal may then be transmitted to a receiving device 11 via a communications channel 36. Communications channel 36 may any mechanism for wireless or wired communication. For example, communications channel 36 may be a network such as the Internet. Communications channel 36 may instead be a cellular network, a telephony network, or any other form of communications that enables the transmission of digital data to receiving device 11.” Paragraph 0067. “Plot 101 illustrates samples of the input signal at a sample rate, paragraph 0090, Fig. 9); generating, by a clock connected to the device (local clock 40b), a second sampling rate (“Devices may compensate for a mismatch between a source clock and a local clock by one of two methods. According to a first method of mismatch compensation, samples may be added or removed from an input digital signal to compensate for clock rate mismatch.” Paragraph 0071, Plot 102-103 in fig. 9, paragraph 0090), and sampling the digital audio data stream at the second sampling rate to generate a second digital audio data stream (“FIG. 10 illustrates a scenario where a local clock has been determined to be faster than a source clock of an input signal. Plot 111 illustrates samples of the input signal at a sample rate Plot 112 illustrates operation of a sample rate converter to adjust a sampling rate of the input signal. Because the local clock is operating slower than the source clock, a timing of output samples may be sped up. Plot 113 shows playback of a sample rate converted signal. According to this example, because a conversion rate was modified based on a detected clock rate mismatch, signal processing circuitry (e.g., a digital to analog converter DAC) may playback the output samples without significant error, because the signal processing circuitry is operating based on the local clock to which the conversion rate was synchronized.” Paragraph 0091); and transmitting the second digital audio data stream to a digital-to-analog conversion codec configured to output analog data to a speaker (“Controller 18 includes a signal processor 14, a sampler 15, and a sampling rate converter 20. Signal processor 14 processes a digital signal received from codec 13 at an input sampling frequency. Sampling rate converter 20 may convert the input sampling frequency to a desired output sampling frequency…Where a digital input signal represents audio data, the analog signal may be audible sound that is communicated to a user by speakers of device 10 or speakers coupled to device 10 (e.g., headphones).” Paragraph 0034). Wang does not appear to expressly teach wherein the second sampling rate approximates the first sampling rate by selecting cycles of the clock closest to the cycles of the first sampling rate. Perez Lara teaches wherein the second sampling rate approximates the first sampling rate by selecting cycles of the clock closest to the cycles of the first sampling rate (“As shown in FIG. 1B, …using the polyphase interpolator module 160) may identify a particular representative output sample time that is closest to a particular output sample time (e.g., t[2m] or t[2n+1])). The test system 110 (e.g., using the polyphase interpolator module 160) may therefore generate a corresponding output sample value (e.g., y[2m] or y[2n+1]) based on the representative output sample time and a corresponding input sample value (x[2s] and x[2s+1]) of the input sample data.” Paragraph 0023,0053). Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang to comprise wherein the second sampling rate approximates the first sampling rate by selecting cycles of the clock closest to the cycles of the first sampling rate. One would have been motivated to make such a combination to reduce “the usage of computing resources (e.g., processing resources, memory resources, communication resources, and/or power resources,)”, Perez Lara [0024]. As to dependent claim 2, Wang teaches the method of claim 1, Wang further teaches wherein the clock has a frequency between 16 MHz and 200 MHz (FIGS. 9 and 10 are conceptual diagrams depicting detected clock rate. Examiner notes that any frequencies may be available depending on the clock’s function within the device). As to dependent claim 3, Wang teaches the method of claim 1, Wang further teaches wherein the digital audio data stream is received over Bluetooth (“For example, communications channel 36 may be a network such as the Internet. Communications channel 36 may instead be a cellular network, a telephony network, or any other form of communications that enables the transmission of digital data to receiving device 11.” Paragraph 0067. As to dependent claim 4, Wang teaches the method of claim 1, Wang further teaches wherein the digital audio data stream is received over Wi-Fi (“In various embodiments, the one or more antenna (For example, communications channel 36 may be a network such as the Internet. Communications channel 36 may instead be a cellular network, a telephony network, or any other form of communications that enables the transmission of digital data to receiving device 11.” Paragraph 0067). As to dependent claim 5, Wang teaches the method of claim 1, Wang further teaches wherein the first sampling rate includes a sampling frequency error (“Plot 101 illustrates samples of the input signal at a sample rate” Paragraph 0090). Perez Lara further teaches sampling frequence error correction – paragraph 0018-0019. As to dependent claim 6, Wang teaches the method of claim 5, Wang further teaches the method comprising estimating, at the device, the sampling frequency error (“Plot 101 illustrates samples of the input signal at a sample rate f.sub.i.” Paragraph 0090). Perez Lara further teaches sampling frequence error correction – paragraph 0018-0019. As to dependent claim 7, Wang teaches the method of claim 1, Wang further teaches the method further teaches wherein the generating a second sampling rate further comprises correcting for a jitter error (“lack of synchronization between source clock 31A, 31B and local clock 40A, 40B may result in a reduction in the quality of playback of a digital signal. For example, if the source clock is slower than a local device clock, device 11 may run out of samples of the input digital signal for playback, which may result in a playback gap when reproducing the input signal for playback. In another example, if source clock 31A, 31B is faster than local clock 40A, 40B, then un-played samples may be lost, which may result in degradation of audio quality.” Paragraph 0070). As to dependent claim 8, Wang teaches the method of claim 7, Wang further teaches wherein the jitter error is corrected using interpolation (“Up-sampler 22 may support arbitrary rational up-sampling rates to convert the input sampling frequency to the desired intermediate sampling frequency by performing up-sampling and interpolation.” Paragraph 0039). Claims 9-20 are substantially the same as claims 1-8 and are therefore rejected under the same rationale. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Miller US 20050062622 Method and system for converting digital samples to an analog signal. Kong et al. US 20110182444 teaches Method And System For Handling The Processing Of Bluetooth Data During Multi-Path Multi-Rate Audio Processing. Astrom et al. US 20120170767 teaches processing audio data for use in a communication session. S0rensen et al. US 20180151187 teaches audio signal processing. Boehlke US 20150195651 teaches a wireless speaker unit includes a radio transceiver oscillator which provides timing signals to a pulse width modulator and to a sample rate controller that provides a variable oversampling signal to a delta sigma modulator. The variable oversampling signal determined by a sampling rate of the digital audio signal. Wakeland et al. US 20130236032 teaches adjusting a data rate of a digital audio stream based on dynamically determine audio layback system capabilities. Volkov et al. US 20210410090 Synchronization of Audio Streams And Sampling Rate For Wireless Communication. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAHELET SHIBEROU whose telephone number is (571)270-7493. The examiner can normally be reached Monday-Friday 9:00 AM-5:00 PM Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kieu Vu can be reached at 571-272-4057. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MAHELET SHIBEROU/Primary Examiner, Art Unit 2171
Read full office action

Prosecution Timeline

Jun 10, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §103
Mar 19, 2026
Response Filed
Jun 12, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+26.7%)
2y 9m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 576 resolved cases by this examiner. Grant probability derived from career allowance rate.

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