DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 10, 12,13, 14, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eleftheriou et al (USP 10,079,058).
Regarding claim 1, Eleftherious discloses an architecture in figure 2 that teaches an analog circuit (200) having plurality of first row (201,202) which a data signal for computations is input and one or more second rows (203) which is calibrations signal for error calibration is input (see col. 1 lines 45-67 and col. 2 lines 1-2), and a plurality of columns (204, 205,206) connected to the plurality of rows (201,202) and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of row (201,202,203)s in response to an input of the data signal and the calibration signal (col. 2, lines 3-22) (see figures 2 and 6 and their description for more details).
Regarding claim 2, Eleftheriou teaches wherein the plurality of rows (201, 202, 203, 210) is connected to the plurality of columns (204, 205, 206) through resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33) and resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33), among the resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33), connecting the one or more second rows (203) to the plurality of columns (204, 205, 206) have a weight value for the error calibration (Col 2, lines 3-52) (see figures 2 and 6).
Regarding claim 10, Eleftheriou teaches wherein, in response inputting to the computation result of the analog computing circuit to another analog computing circuit, a computation result of one or more columns of the plurality of columns is input to the other analog computing circuit for error calibration of the other analog computing circuit (see col 2).
Regarding claim 12, Eleftheriou teaches the analog computing circuit operates normally based on a computation result of columns connected to one of one or more ADCs connected to the plurality of columns (see col. 2).
Regarding claim 13, claim 13 is claiming similar function and limitations of claim 1 in method format. Therefore, claim 13 is rejected as well as rejected in claim 1, such as: Eleftherious discloses an architecture in figure 2 that teaches an analog circuit (200) having plurality of first row (201,202) which a data signal for computations is input and one or more second rows (203) which is calibrations signal for error calibration is input (see col. 1 lines 45-67 and col. 2 lines 1-2), and a plurality of columns (204, 205,206) connected to the plurality of rows (201,202) and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of row (201,202,203)s in response to an input of the data signal and the calibration signal (col. 2, lines 3-22) (see figures 2 and 6 and their description for more details).
Regarding claim 14, claim 14 is claiming similar function and limitations of claim 2 in method format. Therefore, claim 14 is rejected as well as rejected in claim 2, such as: Eleftheriou teaches wherein the plurality of rows (201, 202, 203, 210) is connected to the plurality of columns (204, 205, 206) through resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33) and resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33), among the resistive elements (R11, R12, R13, R21, R22, R23, R31, R32, R33), connecting the one or more second rows (203) to the plurality of columns (204, 205, 206) have a weight value for the error calibration (Col 2, lines 3-52) (see figures 2 and 6).
Regarding claim 18, claim 18 is claiming similar function and limitations of claim 10 in method format. Therefore, claim 18 is rejected as well as rejected in claim 10, such as: Eleftheriou teaches wherein, in response inputting to the computation result of the analog computing circuit to another analog computing circuit, a computation result of one or more columns of the plurality of columns is input to the other analog computing circuit for error calibration of the other analog computing circuit (see col 2).
Regarding claim 19, claim 19 is claiming similar function and limitations of claim 12 in method format. Therefore, claim 19 is rejected as well as rejected in claim 12, such as: Eleftheriou teaches the analog computing circuit operates normally based on a computation result of columns connected to one of one or more ADCs connected to the plurality of columns (see col. 2).
Regarding claim 20, claim 20 is claiming similar function and limitations of claims 1 and 13 in manufacturing format. Therefore, claim 20 is rejected as well as rejected in claims 1 or 13, such as: Eleftherious discloses an architecture in figure 2 that teaches an analog circuit (200) having plurality of first row (201,202) which a data signal for computations is input and one or more second rows (203) which is calibrations signal for error calibration is input (see col. 1 lines 45-67 and col. 2 lines 1-2), and a plurality of columns (204, 205,206) connected to the plurality of rows (201,202) and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of row (201,202,203)s in response to an input of the data signal and the calibration signal (col. 2, lines 3-22) (see figures 2 and 6 and their description for more details).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the plurality of columns is connected to one or more analog-to-digital converters (ADCs), and a calibration signal transmitted to columns connected to one of the one or more ADCs and a weight value of resistive elements connected to the columns connected to the one of the one or more ADCs are determined based on calibration values of the columns connected to the one of the one or more ADCs and a calibration value of one of the one or more ADCs.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration value of the one of the one or more ADCs is determined to be either one of: a value determined based on the calibration values of the columns; and one of the calibration values of the columns.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration value of the one of the one or more ADCs is determined to be an average value of the calibration values of the columns connected to the one of the one or more ADCs.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration value of the one of the one or more ADCs is determined to be a maximum value of the calibration values of the columns connected to the one of the one or more ADCs.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration value of the one of the one or more ADCs is determined to be a minimum value of the calibration values of the columns connected to the one of the one or more ADCs.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein a number of the one or more second rows is determined based on a range of an error for the error calibration, a range of the calibration signal, and a range of a weight value that resistive elements connecting the one or more second rows to the plurality of columns are configured to have.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein an amount of computations that the analog computing circuit is configured to compute at a time decreases as a number of the one or more second rows increases.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein a weight value of resistive elements that transmit the data signal is 0 among resistive elements connected to the one or more columns of the plurality of columns.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the plurality of columns is connected to one or more analog-to-digital converters (ADCs), and a calibration signal transmitted to columns connected to one of the one or more ADCs and a weight value of resistive elements connected to the columns connected to the one of the one or more ADCs are determined based on a calibration value of the columns connected to the one of the one or more ADCs and a calibration value of the one of the one or more ADCs.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the plurality of columns is connected to one or more analog-to-digital converters (ADCs), and a calibration signal transmitted to columns connected to one of the one or more ADCs and a weight value of resistive elements connected to the columns connected to the one of the one or more ADCs are determined based on a calibration value of the columns connected to the one of the one or more ADCs and a calibration value of the one of the one or more ADCs.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein an amount of computations that the analog computing circuit is configured to compute at a time decreases as a number of the one or more second rows increases.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845